arch/arm/mach-versal/cpu.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2016 - 2018 Xilinx, Inc.
   4  * Michal Simek <[email protected]>
   5  */
   6
   7 #include <common.h>
   8 #include <asm/armv8/mmu.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/hardware.h>
  11 #include <asm/arch/sys_proto.h>
  12 #include <asm/cache.h>
  13
  14 DECLARE_GLOBAL_DATA_PTR;
  15
  16 #define VERSAL_MEM_MAP_USED     5
  17
  18 #define DRAM_BANKS CONFIG_NR_DRAM_BANKS
  19
  20 #if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
  21 #define TCM_MAP 1
  22 #else
  23 #define TCM_MAP 0
  24 #endif
  25
  26 /* +1 is end of list which needs to be empty */
  27 #define VERSAL_MEM_MAP_MAX (VERSAL_MEM_MAP_USED + DRAM_BANKS + TCM_MAP + 1)
  28
  29 static struct mm_region versal_mem_map[VERSAL_MEM_MAP_MAX] = {
  30         {
  31                 .virt = 0x80000000UL,
  32                 .phys = 0x80000000UL,
  33                 .size = 0x70000000UL,
  34                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  35                          PTE_BLOCK_NON_SHARE |
  36                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  37         }, {
  38                 .virt = 0xf0000000UL,
  39                 .phys = 0xf0000000UL,
  40                 .size = 0x0fe00000UL,
  41                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  42                          PTE_BLOCK_NON_SHARE |
  43                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  44         }, {
  45                 .virt = 0x400000000UL,
  46                 .phys = 0x400000000UL,
  47                 .size = 0x200000000UL,
  48                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  49                          PTE_BLOCK_NON_SHARE |
  50                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  51         }, {
  52                 .virt = 0x600000000UL,
  53                 .phys = 0x600000000UL,
  54                 .size = 0x800000000UL,
  55                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  56                          PTE_BLOCK_INNER_SHARE
  57         }, {
  58                 .virt = 0xe00000000UL,
  59                 .phys = 0xe00000000UL,
  60                 .size = 0xf200000000UL,
  61                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  62                          PTE_BLOCK_NON_SHARE |
  63                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  64         }
  65 };
  66
  67 void mem_map_fill(void)
  68 {
  69         int banks = VERSAL_MEM_MAP_USED;
  70
  71 #if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
  72         versal_mem_map[banks].virt = 0xffe00000UL;
  73         versal_mem_map[banks].phys = 0xffe00000UL;
  74         versal_mem_map[banks].size = 0x00200000UL;
  75         versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  76                                       PTE_BLOCK_INNER_SHARE;
  77         banks = banks + 1;
  78 #endif
  79
  80         for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  81                 /* Zero size means no more DDR that's this is end */
  82                 if (!gd->bd->bi_dram[i].size)
  83                         break;
  84
  85 #if defined(CONFIG_VERSAL_NO_DDR)
  86                 if (gd->bd->bi_dram[i].start < 0x80000000UL ||
  87                     gd->bd->bi_dram[i].start > 0x100000000UL) {
  88                         printf("Ignore caches over %llx/%llx\n",
  89                                gd->bd->bi_dram[i].start,
  90                                gd->bd->bi_dram[i].size);
  91                         continue;
  92                 }
  93 #endif
  94                 versal_mem_map[banks].virt = gd->bd->bi_dram[i].start;
  95                 versal_mem_map[banks].phys = gd->bd->bi_dram[i].start;
  96                 versal_mem_map[banks].size = gd->bd->bi_dram[i].size;
  97                 versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  98                                               PTE_BLOCK_INNER_SHARE;
  99                 banks = banks + 1;
 100         }
 101 }
 102
 103 struct mm_region *mem_map = versal_mem_map;
 104
 105 u64 get_page_table_size(void)
 106 {
 107         return 0x14000;
 108 }
 109
 110 #if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU)
 111 int arm_reserve_mmu(void)
 112 {
 113         tcm_init(TCM_LOCK);
 114         gd->arch.tlb_size = PGTABLE_SIZE;
 115         gd->arch.tlb_addr = VERSAL_TCM_BASE_ADDR;
 116
 117         return 0;
 118 }
 119 #endif