arch/arm/dts/mt7986.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2022 MediaTek Inc.
   4  * Author: Sam Shih <[email protected]>
   5  */
   6
   7 #include <dt-bindings/interrupt-controller/irq.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/phy/phy.h>
  10 #include <dt-bindings/clock/mt7986-clk.h>
  11 #include <dt-bindings/reset/mt7629-reset.h>
  12 #include <dt-bindings/pinctrl/mt65xx.h>
  13
  14 / {
  15         compatible = "mediatek,mt7986";
  16         interrupt-parent = <&gic>;
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         config {
  21                 u-boot,mmc-env-partition = "u-boot-env";
  22         };
  23
  24         cpus {
  25                 #address-cells = <1>;
  26                 #size-cells = <0>;
  27                 cpu0: cpu@0 {
  28                         device_type = "cpu";
  29                         compatible = "arm,cortex-a53";
  30                         reg = <0x0>;
  31                         mediatek,hwver = <&hwver>;
  32                 };
  33                 cpu1: cpu@1 {
  34                         device_type = "cpu";
  35                         compatible = "arm,cortex-a53";
  36                         reg = <0x1>;
  37                         mediatek,hwver = <&hwver>;
  38                 };
  39                 cpu2: cpu@2 {
  40                         device_type = "cpu";
  41                         compatible = "arm,cortex-a53";
  42                         reg = <0x2>;
  43                         mediatek,hwver = <&hwver>;
  44                 };
  45                 cpu3: cpu@3 {
  46                         device_type = "cpu";
  47                         compatible = "arm,cortex-a53";
  48                         reg = <0x3>;
  49                         mediatek,hwver = <&hwver>;
  50                 };
  51         };
  52
  53         dummy_clk: dummy12m {
  54                 compatible = "fixed-clock";
  55                 clock-frequency = <12000000>;
  56                 #clock-cells = <0>;
  57                 /* must need this line, or uart uanable to get dummy_clk */
  58                 bootph-all;
  59         };
  60
  61         hwver: hwver {
  62                 compatible = "mediatek,hwver", "syscon";
  63                 reg = <0x8000000 0x1000>;
  64         };
  65
  66         timer {
  67                 compatible = "arm,armv8-timer";
  68                 interrupt-parent = <&gic>;
  69                 clock-frequency = <13000000>;
  70                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
  71                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
  72                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
  73                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
  74                 arm,cpu-registers-not-fw-configured;
  75         };
  76
  77         timer0: timer@10008000 {
  78                 compatible = "mediatek,mt7986-timer";
  79                 reg = <0x10008000 0x1000>;
  80                 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
  81                 clocks = <&topckgen CLK_TOP_F26M_SEL>;
  82                 clock-names = "gpt-clk";
  83                 bootph-all;
  84         };
  85
  86         watchdog: watchdog@1001c000 {
  87                 compatible = "mediatek,mt7986-wdt";
  88                 reg = <0x1001c000 0x1000>;
  89                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
  90                 #reset-cells = <1>;
  91                 status = "disabled";
  92         };
  93
  94         gic: interrupt-controller@c000000 {
  95                 compatible = "arm,gic-v3";
  96                 #interrupt-cells = <3>;
  97                 interrupt-parent = <&gic>;
  98                 interrupt-controller;
  99                 reg = <0x0c000000 0x40000>,  /* GICD */
 100                       <0x0c080000 0x200000>; /* GICR */
 101
 102                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 103         };
 104
 105         fixed_plls: apmixedsys@1001E000 {
 106                 compatible = "mediatek,mt7986-fixed-plls";
 107                 reg = <0x1001E000 0x1000>;
 108                 #clock-cells = <1>;
 109         };
 110
 111         topckgen: topckgen@1001B000 {
 112                 compatible = "mediatek,mt7986-topckgen";
 113                 reg = <0x1001B000 0x1000>;
 114                 clock-parent = <&fixed_plls>;
 115                 #clock-cells = <1>;
 116         };
 117
 118         infracfg: infracfg@10001040 {
 119                 compatible = "mediatek,mt7986-infracfg";
 120                 reg = <0x10001000 0x1000>;
 121                 clock-parent = <&topckgen>;
 122                 #clock-cells = <1>;
 123         };
 124
 125         pinctrl: pinctrl@1001f000 {
 126                 compatible = "mediatek,mt7986-pinctrl";
 127                 reg = <0x1001f000 0x1000>,
 128                       <0x11c30000 0x1000>,
 129                       <0x11c40000 0x1000>,
 130                       <0x11e20000 0x1000>,
 131                       <0x11e30000 0x1000>,
 132                       <0x11f00000 0x1000>,
 133                       <0x11f10000 0x1000>,
 134                       <0x1000b000 0x1000>;
 135                 reg-names = "gpio_base", "iocfg_rt_base", "iocfg_rb_base",
 136                             "iocfg_lt_base", "iocfg_lb_base", "iocfg_tr_base",
 137                             "iocfg_tl_base", "eint";
 138                 gpio: gpio-controller {
 139                         gpio-controller;
 140                         #gpio-cells = <2>;
 141                 };
 142         };
 143
 144         pwm: pwm@10048000 {
 145                 compatible = "mediatek,mt7986-pwm";
 146                 reg = <0x10048000 0x1000>;
 147                 #clock-cells = <1>;
 148                 #pwm-cells = <2>;
 149                 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
 150                 clocks = <&topckgen CLK_TOP_PWM_SEL>,
 151                          <&infracfg CLK_INFRA_PWM_BSEL>,
 152                          <&infracfg CLK_INFRA_PWM1_CK>,
 153                          <&infracfg CLK_INFRA_PWM2_CK>;
 154                 assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>,
 155                                   <&infracfg CLK_INFRA_PWM_BSEL>,
 156                                   <&infracfg CLK_INFRA_PWM1_SEL>,
 157                                   <&infracfg CLK_INFRA_PWM2_SEL>;
 158                 assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D4>,
 159                                          <&topckgen CLK_TOP_PWM_SEL>,
 160                                          <&topckgen CLK_TOP_PWM_SEL>,
 161                                          <&topckgen CLK_TOP_PWM_SEL>;
 162                 clock-names = "top", "main", "pwm1", "pwm2";
 163                 status = "disabled";
 164                 bootph-all;
 165         };
 166
 167         uart0: serial@11002000 {
 168                 compatible = "mediatek,hsuart";
 169                 reg = <0x11002000 0x400>;
 170                 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
 171                 clocks = <&infracfg CLK_INFRA_UART0_CK>;
 172                 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
 173                                   <&infracfg CLK_INFRA_UART0_SEL>;
 174                 assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
 175                                          <&topckgen CLK_TOP_UART_SEL>;
 176                 mediatek,force-highspeed;
 177                 status = "disabled";
 178                 bootph-all;
 179         };
 180
 181         uart1: serial@11003000 {
 182                 compatible = "mediatek,hsuart";
 183                 reg = <0x11003000 0x400>;
 184                 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
 185                 clocks = <&infracfg CLK_INFRA_UART1_CK>;
 186                 assigned-clocks = <&infracfg CLK_INFRA_UART1_SEL>;
 187                 assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
 188                 mediatek,force-highspeed;
 189                 status = "disabled";
 190         };
 191
 192         uart2: serial@11004000 {
 193                 compatible = "mediatek,hsuart";
 194                 reg = <0x11004000 0x400>;
 195                 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
 196                 clocks = <&infracfg CLK_INFRA_UART2_CK>;
 197                 assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>;
 198                 assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
 199                 mediatek,force-highspeed;
 200                 status = "disabled";
 201         };
 202
 203         snand: snand@11005000 {
 204                 compatible = "mediatek,mt7986-snand";
 205                 reg = <0x11005000 0x1000>,
 206                       <0x11006000 0x1000>;
 207                 reg-names = "nfi", "ecc";
 208                 clocks = <&infracfg CLK_INFRA_SPINFI1_CK>,
 209                          <&infracfg CLK_INFRA_NFI1_CK>,
 210                          <&infracfg CLK_INFRA_NFI_HCK_CK>;
 211                 clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
 212                 assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
 213                                   <&topckgen CLK_TOP_NFI1X_SEL>;
 214                 assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D8>,
 215                                          <&topckgen CLK_TOP_MPLL_D8>;
 216                 status = "disabled";
 217         };
 218
 219         ethsys: syscon@15000000 {
 220                 compatible = "mediatek,mt7986-ethsys", "syscon";
 221                 reg = <0x15000000 0x1000>;
 222                 clock-parent = <&topckgen>;
 223                 #clock-cells = <1>;
 224                 #reset-cells = <1>;
 225         };
 226
 227         eth: ethernet@15100000 {
 228                 compatible = "mediatek,mt7986-eth", "syscon";
 229                 reg = <0x15100000 0x20000>;
 230                 resets = <&ethsys ETHSYS_FE_RST>;
 231                 reset-names = "fe";
 232                 mediatek,ethsys = <&ethsys>;
 233                 mediatek,sgmiisys = <&sgmiisys0>;
 234                 #address-cells = <1>;
 235                 #size-cells = <0>;
 236                 status = "disabled";
 237         };
 238
 239         sgmiisys0: syscon@10060000 {
 240                 compatible = "mediatek,mt7986-sgmiisys", "syscon";
 241                 reg = <0x10060000 0x1000>;
 242                 #clock-cells = <1>;
 243         };
 244
 245         sgmiisys1: syscon@10070000 {
 246                 compatible = "mediatek,mt7986-sgmiisys", "syscon";
 247                 reg = <0x10070000 0x1000>;
 248                 #clock-cells = <1>;
 249         };
 250
 251         spi0: spi@1100a000 {
 252                 compatible = "mediatek,ipm-spi";
 253                 reg = <0x1100a000 0x100>;
 254                 clocks = <&infracfg CLK_INFRA_SPI0_CK>,
 255                          <&topckgen CLK_TOP_SPI_SEL>;
 256                 assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>,
 257                                   <&infracfg CLK_INFRA_SPI0_SEL>;
 258                 assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D2>,
 259                                          <&topckgen CLK_TOP_SPI_SEL>;
 260                 clock-names = "sel-clk", "spi-clk";
 261                 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 262                 status = "disabled";
 263         };
 264
 265         spi1: spi@1100b000 {
 266                 compatible = "mediatek,ipm-spi";
 267                 reg = <0x1100b000 0x100>;
 268                 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 269                 status = "disabled";
 270         };
 271
 272         mmc0: mmc@11230000 {
 273                 compatible = "mediatek,mt7986-mmc";
 274                 reg = <0x11230000 0x1000>,
 275                       <0x11C20000 0x1000>;
 276                 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 277                 clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
 278                         <&topckgen CLK_TOP_EMMC_250M_SEL>,
 279                         <&infracfg CLK_INFRA_MSDC_CK>;
 280                 assigned-clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
 281                                   <&topckgen CLK_TOP_EMMC_250M_SEL>;
 282                 assigned-clock-parents = <&fixed_plls CLK_APMIXED_MPLL>,
 283                                          <&topckgen CLK_TOP_NET1PLL_D5_D2>;
 284                 clock-names = "source", "hclk", "source_cg";
 285                 status = "disabled";
 286         };
 287
 288         xhci: xhci@11200000 {
 289                 compatible = "mediatek,mt7986-xhci",
 290                              "mediatek,mtk-xhci";
 291                 reg = <0x11200000 0x2e00>,
 292                       <0x11203e00 0x0100>;
 293                 reg-names = "mac", "ippc";
 294                 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
 295                 phys = <&u2port0 PHY_TYPE_USB2>,
 296                        <&u3port0 PHY_TYPE_USB3>,
 297                        <&u2port1 PHY_TYPE_USB2>;
 298                 clocks = <&dummy_clk>,
 299                          <&dummy_clk>,
 300                          <&dummy_clk>,
 301                          <&dummy_clk>,
 302                          <&dummy_clk>;
 303                 clock-names = "sys_ck",
 304                               "xhci_ck",
 305                               "ref_ck",
 306                               "mcu_ck",
 307                               "dma_ck";
 308                 tpl-support;
 309                 status = "okay";
 310         };
 311
 312         usbtphy: usb-phy@11e10000 {
 313                 compatible = "mediatek,mt7986",
 314                              "mediatek,generic-tphy-v2";
 315                 #address-cells = <1>;
 316                 #size-cells = <1>;
 317                 status = "okay";
 318
 319                 u2port0: usb-phy@11e10000 {
 320                         reg = <0x11e10000 0x700>;
 321                         clocks = <&dummy_clk>;
 322                         clock-names = "ref";
 323                         #phy-cells = <1>;
 324                         status = "okay";
 325                 };
 326
 327                 u3port0: usb-phy@11e10700 {
 328                         reg = <0x11e10700 0x900>;
 329                         clocks = <&dummy_clk>;
 330                         clock-names = "ref";
 331                         #phy-cells = <1>;
 332                         status = "okay";
 333                 };
 334
 335                 u2port1: usb-phy@11e11000 {
 336                         reg = <0x11e11000 0x700>;
 337                         clocks = <&dummy_clk>;
 338                         clock-names = "ref";
 339                         #phy-cells = <1>;
 340                         status = "okay";
 341                 };
 342         };
 343 };