2 * Copyright 2008, Freescale Semiconductor, Inc
5 * Based vaguely on the Linux code
7 * SPDX-License-Identifier: GPL-2.0+
14 #include <dm/device-internal.h>
20 #include <linux/list.h>
22 #include "mmc_private.h"
24 __weak int board_mmc_getwp(struct mmc *mmc)
29 int mmc_getwp(struct mmc *mmc)
33 wp = board_mmc_getwp(mmc);
36 if (mmc->cfg->ops->getwp)
37 wp = mmc->cfg->ops->getwp(mmc);
45 __weak int board_mmc_getcd(struct mmc *mmc)
50 int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
54 #ifdef CONFIG_MMC_TRACE
58 printf("CMD_SEND:%d\n", cmd->cmdidx);
59 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
60 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
62 printf("\t\tRET\t\t\t %d\n", ret);
64 switch (cmd->resp_type) {
66 printf("\t\tMMC_RSP_NONE\n");
69 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
73 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
77 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
79 printf("\t\t \t\t 0x%08X \n",
81 printf("\t\t \t\t 0x%08X \n",
83 printf("\t\t \t\t 0x%08X \n",
86 printf("\t\t\t\t\tDUMPING DATA\n");
87 for (i = 0; i < 4; i++) {
89 printf("\t\t\t\t\t%03d - ", i*4);
90 ptr = (u8 *)&cmd->response[i];
92 for (j = 0; j < 4; j++)
93 printf("%02X ", *ptr--);
98 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
102 printf("\t\tERROR MMC rsp not supported\n");
107 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
112 int mmc_send_status(struct mmc *mmc, int timeout)
115 int err, retries = 5;
116 #ifdef CONFIG_MMC_TRACE
120 cmd.cmdidx = MMC_CMD_SEND_STATUS;
121 cmd.resp_type = MMC_RSP_R1;
122 if (!mmc_host_is_spi(mmc))
123 cmd.cmdarg = mmc->rca << 16;
126 err = mmc_send_cmd(mmc, &cmd, NULL);
128 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
129 (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
132 else if (cmd.response[0] & MMC_STATUS_MASK) {
133 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
134 printf("Status Error: 0x%08X\n",
139 } else if (--retries < 0)
148 #ifdef CONFIG_MMC_TRACE
149 status = (cmd.response[0] & MMC_STATUS_CURR_STATE) >> 9;
150 printf("CURR STATE:%d\n", status);
153 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
154 printf("Timeout waiting card ready\n");
162 int mmc_set_blocklen(struct mmc *mmc, int len)
169 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
170 cmd.resp_type = MMC_RSP_R1;
173 return mmc_send_cmd(mmc, &cmd, NULL);
176 static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
180 struct mmc_data data;
183 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
185 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
187 if (mmc->high_capacity)
190 cmd.cmdarg = start * mmc->read_bl_len;
192 cmd.resp_type = MMC_RSP_R1;
195 data.blocks = blkcnt;
196 data.blocksize = mmc->read_bl_len;
197 data.flags = MMC_DATA_READ;
199 if (mmc_send_cmd(mmc, &cmd, &data))
203 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
205 cmd.resp_type = MMC_RSP_R1b;
206 if (mmc_send_cmd(mmc, &cmd, NULL)) {
207 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
208 printf("mmc fail to send stop cmd\n");
218 ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst)
220 ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
225 struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
227 int dev_num = block_dev->devnum;
229 lbaint_t cur, blocks_todo = blkcnt;
234 struct mmc *mmc = find_mmc_device(dev_num);
238 err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
242 if ((start + blkcnt) > block_dev->lba) {
243 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
244 printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
245 start + blkcnt, block_dev->lba);
250 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
251 debug("%s: Failed to set blocklen\n", __func__);
256 cur = (blocks_todo > mmc->cfg->b_max) ?
257 mmc->cfg->b_max : blocks_todo;
258 if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
259 debug("%s: Failed to read blocks\n", __func__);
264 dst += cur * mmc->read_bl_len;
265 } while (blocks_todo > 0);
270 static int mmc_go_idle(struct mmc *mmc)
277 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
279 cmd.resp_type = MMC_RSP_NONE;
281 err = mmc_send_cmd(mmc, &cmd, NULL);
291 static int sd_send_op_cond(struct mmc *mmc)
298 cmd.cmdidx = MMC_CMD_APP_CMD;
299 cmd.resp_type = MMC_RSP_R1;
302 err = mmc_send_cmd(mmc, &cmd, NULL);
307 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
308 cmd.resp_type = MMC_RSP_R3;
311 * Most cards do not answer if some reserved bits
312 * in the ocr are set. However, Some controller
313 * can set bit 7 (reserved for low voltages), but
314 * how to manage low voltages SD card is not yet
317 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
318 (mmc->cfg->voltages & 0xff8000);
320 if (mmc->version == SD_VERSION_2)
321 cmd.cmdarg |= OCR_HCS;
323 err = mmc_send_cmd(mmc, &cmd, NULL);
328 if (cmd.response[0] & OCR_BUSY)
337 if (mmc->version != SD_VERSION_2)
338 mmc->version = SD_VERSION_1_0;
340 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
341 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
342 cmd.resp_type = MMC_RSP_R3;
345 err = mmc_send_cmd(mmc, &cmd, NULL);
351 mmc->ocr = cmd.response[0];
353 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
359 static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
364 cmd.cmdidx = MMC_CMD_SEND_OP_COND;
365 cmd.resp_type = MMC_RSP_R3;
367 if (use_arg && !mmc_host_is_spi(mmc))
368 cmd.cmdarg = OCR_HCS |
369 (mmc->cfg->voltages &
370 (mmc->ocr & OCR_VOLTAGE_MASK)) |
371 (mmc->ocr & OCR_ACCESS_MODE);
373 err = mmc_send_cmd(mmc, &cmd, NULL);
376 mmc->ocr = cmd.response[0];
380 static int mmc_send_op_cond(struct mmc *mmc)
384 /* Some cards seem to need this */
387 /* Asking to the card its capabilities */
388 for (i = 0; i < 2; i++) {
389 err = mmc_send_op_cond_iter(mmc, i != 0);
393 /* exit if not busy (flag seems to be inverted) */
394 if (mmc->ocr & OCR_BUSY)
397 mmc->op_cond_pending = 1;
401 static int mmc_complete_op_cond(struct mmc *mmc)
408 mmc->op_cond_pending = 0;
409 if (!(mmc->ocr & OCR_BUSY)) {
410 start = get_timer(0);
412 err = mmc_send_op_cond_iter(mmc, 1);
415 if (mmc->ocr & OCR_BUSY)
417 if (get_timer(start) > timeout)
423 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
424 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
425 cmd.resp_type = MMC_RSP_R3;
428 err = mmc_send_cmd(mmc, &cmd, NULL);
433 mmc->ocr = cmd.response[0];
436 mmc->version = MMC_VERSION_UNKNOWN;
438 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
445 static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
448 struct mmc_data data;
451 /* Get the Card Status Register */
452 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
453 cmd.resp_type = MMC_RSP_R1;
456 data.dest = (char *)ext_csd;
458 data.blocksize = MMC_MAX_BLOCK_LEN;
459 data.flags = MMC_DATA_READ;
461 err = mmc_send_cmd(mmc, &cmd, &data);
467 static int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
473 cmd.cmdidx = MMC_CMD_SWITCH;
474 cmd.resp_type = MMC_RSP_R1b;
475 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
479 ret = mmc_send_cmd(mmc, &cmd, NULL);
481 /* Waiting for the ready status */
483 ret = mmc_send_status(mmc, timeout);
489 static int mmc_change_freq(struct mmc *mmc)
491 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
497 if (mmc_host_is_spi(mmc))
500 /* Only version 4 supports high-speed */
501 if (mmc->version < MMC_VERSION_4)
504 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
506 err = mmc_send_ext_csd(mmc, ext_csd);
511 cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf;
513 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1);
518 /* Now check to see that it worked */
519 err = mmc_send_ext_csd(mmc, ext_csd);
524 /* No high-speed support */
525 if (!ext_csd[EXT_CSD_HS_TIMING])
528 /* High Speed is set, there are two types: 52MHz and 26MHz */
529 if (cardtype & EXT_CSD_CARD_TYPE_52) {
530 if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
531 mmc->card_caps |= MMC_MODE_DDR_52MHz;
532 mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
534 mmc->card_caps |= MMC_MODE_HS;
540 static int mmc_set_capacity(struct mmc *mmc, int part_num)
544 mmc->capacity = mmc->capacity_user;
548 mmc->capacity = mmc->capacity_boot;
551 mmc->capacity = mmc->capacity_rpmb;
557 mmc->capacity = mmc->capacity_gp[part_num - 4];
563 mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
568 int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
572 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
573 (mmc->part_config & ~PART_ACCESS_MASK)
574 | (part_num & PART_ACCESS_MASK));
577 * Set the capacity if the switch succeeded or was intended
578 * to return to representing the raw device.
580 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
581 ret = mmc_set_capacity(mmc, part_num);
582 mmc_get_blk_desc(mmc)->hwpart = part_num;
588 int mmc_hwpart_config(struct mmc *mmc,
589 const struct mmc_hwpart_conf *conf,
590 enum mmc_hwpart_conf_mode mode)
596 u32 max_enh_size_mult;
597 u32 tot_enh_size_mult = 0;
600 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
602 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
605 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
606 printf("eMMC >= 4.4 required for enhanced user data area\n");
610 if (!(mmc->part_support & PART_SUPPORT)) {
611 printf("Card does not support partitioning\n");
615 if (!mmc->hc_wp_grp_size) {
616 printf("Card does not define HC WP group size\n");
620 /* check partition alignment and total enhanced size */
621 if (conf->user.enh_size) {
622 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
623 conf->user.enh_start % mmc->hc_wp_grp_size) {
624 printf("User data enhanced area not HC WP group "
628 part_attrs |= EXT_CSD_ENH_USR;
629 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
630 if (mmc->high_capacity) {
631 enh_start_addr = conf->user.enh_start;
633 enh_start_addr = (conf->user.enh_start << 9);
639 tot_enh_size_mult += enh_size_mult;
641 for (pidx = 0; pidx < 4; pidx++) {
642 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
643 printf("GP%i partition not HC WP group size "
644 "aligned\n", pidx+1);
647 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
648 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
649 part_attrs |= EXT_CSD_ENH_GP(pidx);
650 tot_enh_size_mult += gp_size_mult[pidx];
654 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
655 printf("Card does not support enhanced attribute\n");
659 err = mmc_send_ext_csd(mmc, ext_csd);
664 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
665 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
666 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
667 if (tot_enh_size_mult > max_enh_size_mult) {
668 printf("Total enhanced size exceeds maximum (%u > %u)\n",
669 tot_enh_size_mult, max_enh_size_mult);
673 /* The default value of EXT_CSD_WR_REL_SET is device
674 * dependent, the values can only be changed if the
675 * EXT_CSD_HS_CTRL_REL bit is set. The values can be
676 * changed only once and before partitioning is completed. */
677 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
678 if (conf->user.wr_rel_change) {
679 if (conf->user.wr_rel_set)
680 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
682 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
684 for (pidx = 0; pidx < 4; pidx++) {
685 if (conf->gp_part[pidx].wr_rel_change) {
686 if (conf->gp_part[pidx].wr_rel_set)
687 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
689 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
693 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
694 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
695 puts("Card does not support host controlled partition write "
696 "reliability settings\n");
700 if (ext_csd[EXT_CSD_PARTITION_SETTING] &
701 EXT_CSD_PARTITION_SETTING_COMPLETED) {
702 printf("Card already partitioned\n");
706 if (mode == MMC_HWPART_CONF_CHECK)
709 /* Partitioning requires high-capacity size definitions */
710 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
711 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
712 EXT_CSD_ERASE_GROUP_DEF, 1);
717 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
719 /* update erase group size to be high-capacity */
720 mmc->erase_grp_size =
721 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
725 /* all OK, write the configuration */
726 for (i = 0; i < 4; i++) {
727 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
728 EXT_CSD_ENH_START_ADDR+i,
729 (enh_start_addr >> (i*8)) & 0xFF);
733 for (i = 0; i < 3; i++) {
734 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
735 EXT_CSD_ENH_SIZE_MULT+i,
736 (enh_size_mult >> (i*8)) & 0xFF);
740 for (pidx = 0; pidx < 4; pidx++) {
741 for (i = 0; i < 3; i++) {
742 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
743 EXT_CSD_GP_SIZE_MULT+pidx*3+i,
744 (gp_size_mult[pidx] >> (i*8)) & 0xFF);
749 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
750 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
754 if (mode == MMC_HWPART_CONF_SET)
757 /* The WR_REL_SET is a write-once register but shall be
758 * written before setting PART_SETTING_COMPLETED. As it is
759 * write-once we can only write it when completing the
761 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
762 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
763 EXT_CSD_WR_REL_SET, wr_rel_set);
768 /* Setting PART_SETTING_COMPLETED confirms the partition
769 * configuration but it only becomes effective after power
770 * cycle, so we do not adjust the partition related settings
771 * in the mmc struct. */
773 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
774 EXT_CSD_PARTITION_SETTING,
775 EXT_CSD_PARTITION_SETTING_COMPLETED);
782 int mmc_getcd(struct mmc *mmc)
786 cd = board_mmc_getcd(mmc);
789 if (mmc->cfg->ops->getcd)
790 cd = mmc->cfg->ops->getcd(mmc);
798 static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
801 struct mmc_data data;
803 /* Switch the frequency */
804 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
805 cmd.resp_type = MMC_RSP_R1;
806 cmd.cmdarg = (mode << 31) | 0xffffff;
807 cmd.cmdarg &= ~(0xf << (group * 4));
808 cmd.cmdarg |= value << (group * 4);
810 data.dest = (char *)resp;
813 data.flags = MMC_DATA_READ;
815 return mmc_send_cmd(mmc, &cmd, &data);
819 static int sd_change_freq(struct mmc *mmc)
823 ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2);
824 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
825 struct mmc_data data;
830 if (mmc_host_is_spi(mmc))
833 /* Read the SCR to find out if this card supports higher speeds */
834 cmd.cmdidx = MMC_CMD_APP_CMD;
835 cmd.resp_type = MMC_RSP_R1;
836 cmd.cmdarg = mmc->rca << 16;
838 err = mmc_send_cmd(mmc, &cmd, NULL);
843 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
844 cmd.resp_type = MMC_RSP_R1;
850 data.dest = (char *)scr;
853 data.flags = MMC_DATA_READ;
855 err = mmc_send_cmd(mmc, &cmd, &data);
864 mmc->scr[0] = __be32_to_cpu(scr[0]);
865 mmc->scr[1] = __be32_to_cpu(scr[1]);
867 switch ((mmc->scr[0] >> 24) & 0xf) {
869 mmc->version = SD_VERSION_1_0;
872 mmc->version = SD_VERSION_1_10;
875 mmc->version = SD_VERSION_2;
876 if ((mmc->scr[0] >> 15) & 0x1)
877 mmc->version = SD_VERSION_3;
880 mmc->version = SD_VERSION_1_0;
884 if (mmc->scr[0] & SD_DATA_4BIT)
885 mmc->card_caps |= MMC_MODE_4BIT;
887 /* Version 1.0 doesn't support switching */
888 if (mmc->version == SD_VERSION_1_0)
893 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
894 (u8 *)switch_status);
899 /* The high-speed function is busy. Try again */
900 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
904 /* If high-speed isn't supported, we return */
905 if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED))
909 * If the host doesn't support SD_HIGHSPEED, do not switch card to
910 * HIGHSPEED mode even if the card support SD_HIGHSPPED.
911 * This can avoid furthur problem when the card runs in different
912 * mode between the host.
914 if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) &&
915 (mmc->cfg->host_caps & MMC_MODE_HS)))
918 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status);
923 if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000)
924 mmc->card_caps |= MMC_MODE_HS;
929 /* frequency bases */
930 /* divided by 10 to be nice to platforms without floating point */
931 static const int fbase[] = {
938 /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
939 * to platforms without floating point.
941 static const u8 multipliers[] = {
960 static void mmc_set_ios(struct mmc *mmc)
962 if (mmc->cfg->ops->set_ios)
963 mmc->cfg->ops->set_ios(mmc);
966 void mmc_set_clock(struct mmc *mmc, uint clock)
968 if (clock > mmc->cfg->f_max)
969 clock = mmc->cfg->f_max;
971 if (clock < mmc->cfg->f_min)
972 clock = mmc->cfg->f_min;
979 static void mmc_set_bus_width(struct mmc *mmc, uint width)
981 mmc->bus_width = width;
986 static int mmc_startup(struct mmc *mmc)
990 u64 cmult, csize, capacity;
992 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
993 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
995 bool has_parts = false;
997 struct blk_desc *bdesc;
999 #ifdef CONFIG_MMC_SPI_CRC_ON
1000 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
1001 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
1002 cmd.resp_type = MMC_RSP_R1;
1004 err = mmc_send_cmd(mmc, &cmd, NULL);
1011 /* Put the Card in Identify Mode */
1012 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
1013 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
1014 cmd.resp_type = MMC_RSP_R2;
1017 err = mmc_send_cmd(mmc, &cmd, NULL);
1022 memcpy(mmc->cid, cmd.response, 16);
1025 * For MMC cards, set the Relative Address.
1026 * For SD cards, get the Relatvie Address.
1027 * This also puts the cards into Standby State
1029 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1030 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
1031 cmd.cmdarg = mmc->rca << 16;
1032 cmd.resp_type = MMC_RSP_R6;
1034 err = mmc_send_cmd(mmc, &cmd, NULL);
1040 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
1043 /* Get the Card-Specific Data */
1044 cmd.cmdidx = MMC_CMD_SEND_CSD;
1045 cmd.resp_type = MMC_RSP_R2;
1046 cmd.cmdarg = mmc->rca << 16;
1048 err = mmc_send_cmd(mmc, &cmd, NULL);
1050 /* Waiting for the ready status */
1051 mmc_send_status(mmc, timeout);
1056 mmc->csd[0] = cmd.response[0];
1057 mmc->csd[1] = cmd.response[1];
1058 mmc->csd[2] = cmd.response[2];
1059 mmc->csd[3] = cmd.response[3];
1061 if (mmc->version == MMC_VERSION_UNKNOWN) {
1062 int version = (cmd.response[0] >> 26) & 0xf;
1066 mmc->version = MMC_VERSION_1_2;
1069 mmc->version = MMC_VERSION_1_4;
1072 mmc->version = MMC_VERSION_2_2;
1075 mmc->version = MMC_VERSION_3;
1078 mmc->version = MMC_VERSION_4;
1081 mmc->version = MMC_VERSION_1_2;
1086 /* divide frequency by 10, since the mults are 10x bigger */
1087 freq = fbase[(cmd.response[0] & 0x7)];
1088 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
1090 mmc->tran_speed = freq * mult;
1092 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
1093 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
1096 mmc->write_bl_len = mmc->read_bl_len;
1098 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
1100 if (mmc->high_capacity) {
1101 csize = (mmc->csd[1] & 0x3f) << 16
1102 | (mmc->csd[2] & 0xffff0000) >> 16;
1105 csize = (mmc->csd[1] & 0x3ff) << 2
1106 | (mmc->csd[2] & 0xc0000000) >> 30;
1107 cmult = (mmc->csd[2] & 0x00038000) >> 15;
1110 mmc->capacity_user = (csize + 1) << (cmult + 2);
1111 mmc->capacity_user *= mmc->read_bl_len;
1112 mmc->capacity_boot = 0;
1113 mmc->capacity_rpmb = 0;
1114 for (i = 0; i < 4; i++)
1115 mmc->capacity_gp[i] = 0;
1117 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
1118 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
1120 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
1121 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
1123 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
1124 cmd.cmdidx = MMC_CMD_SET_DSR;
1125 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
1126 cmd.resp_type = MMC_RSP_NONE;
1127 if (mmc_send_cmd(mmc, &cmd, NULL))
1128 printf("MMC: SET_DSR failed\n");
1131 /* Select the card, and put it into Transfer Mode */
1132 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1133 cmd.cmdidx = MMC_CMD_SELECT_CARD;
1134 cmd.resp_type = MMC_RSP_R1;
1135 cmd.cmdarg = mmc->rca << 16;
1136 err = mmc_send_cmd(mmc, &cmd, NULL);
1143 * For SD, its erase group is always one sector
1145 mmc->erase_grp_size = 1;
1146 mmc->part_config = MMCPART_NOAVAILABLE;
1147 if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) {
1148 /* check ext_csd version and capacity */
1149 err = mmc_send_ext_csd(mmc, ext_csd);
1152 if (ext_csd[EXT_CSD_REV] >= 2) {
1154 * According to the JEDEC Standard, the value of
1155 * ext_csd's capacity is valid if the value is more
1158 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
1159 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
1160 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
1161 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
1162 capacity *= MMC_MAX_BLOCK_LEN;
1163 if ((capacity >> 20) > 2 * 1024)
1164 mmc->capacity_user = capacity;
1167 switch (ext_csd[EXT_CSD_REV]) {
1169 mmc->version = MMC_VERSION_4_1;
1172 mmc->version = MMC_VERSION_4_2;
1175 mmc->version = MMC_VERSION_4_3;
1178 mmc->version = MMC_VERSION_4_41;
1181 mmc->version = MMC_VERSION_4_5;
1184 mmc->version = MMC_VERSION_5_0;
1187 mmc->version = MMC_VERSION_5_1;
1191 /* The partition data may be non-zero but it is only
1192 * effective if PARTITION_SETTING_COMPLETED is set in
1193 * EXT_CSD, so ignore any data if this bit is not set,
1194 * except for enabling the high-capacity group size
1195 * definition (see below). */
1196 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
1197 EXT_CSD_PARTITION_SETTING_COMPLETED);
1199 /* store the partition info of emmc */
1200 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
1201 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
1202 ext_csd[EXT_CSD_BOOT_MULT])
1203 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
1204 if (part_completed &&
1205 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
1206 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
1208 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
1210 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
1212 for (i = 0; i < 4; i++) {
1213 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
1214 uint mult = (ext_csd[idx + 2] << 16) +
1215 (ext_csd[idx + 1] << 8) + ext_csd[idx];
1218 if (!part_completed)
1220 mmc->capacity_gp[i] = mult;
1221 mmc->capacity_gp[i] *=
1222 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1223 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1224 mmc->capacity_gp[i] <<= 19;
1227 if (part_completed) {
1228 mmc->enh_user_size =
1229 (ext_csd[EXT_CSD_ENH_SIZE_MULT+2] << 16) +
1230 (ext_csd[EXT_CSD_ENH_SIZE_MULT+1] << 8) +
1231 ext_csd[EXT_CSD_ENH_SIZE_MULT];
1232 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1233 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1234 mmc->enh_user_size <<= 19;
1235 mmc->enh_user_start =
1236 (ext_csd[EXT_CSD_ENH_START_ADDR+3] << 24) +
1237 (ext_csd[EXT_CSD_ENH_START_ADDR+2] << 16) +
1238 (ext_csd[EXT_CSD_ENH_START_ADDR+1] << 8) +
1239 ext_csd[EXT_CSD_ENH_START_ADDR];
1240 if (mmc->high_capacity)
1241 mmc->enh_user_start <<= 9;
1245 * Host needs to enable ERASE_GRP_DEF bit if device is
1246 * partitioned. This bit will be lost every time after a reset
1247 * or power off. This will affect erase size.
1251 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
1252 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
1255 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1256 EXT_CSD_ERASE_GROUP_DEF, 1);
1261 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
1264 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
1265 /* Read out group size from ext_csd */
1266 mmc->erase_grp_size =
1267 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
1269 * if high capacity and partition setting completed
1270 * SEC_COUNT is valid even if it is smaller than 2 GiB
1271 * JEDEC Standard JESD84-B45, 6.2.4
1273 if (mmc->high_capacity && part_completed) {
1274 capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
1275 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
1276 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
1277 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
1278 capacity *= MMC_MAX_BLOCK_LEN;
1279 mmc->capacity_user = capacity;
1282 /* Calculate the group size from the csd value. */
1283 int erase_gsz, erase_gmul;
1284 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
1285 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
1286 mmc->erase_grp_size = (erase_gsz + 1)
1290 mmc->hc_wp_grp_size = 1024
1291 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1292 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1294 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
1297 err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
1302 err = sd_change_freq(mmc);
1304 err = mmc_change_freq(mmc);
1309 /* Restrict card's capabilities by what the host can do */
1310 mmc->card_caps &= mmc->cfg->host_caps;
1313 if (mmc->card_caps & MMC_MODE_4BIT) {
1314 cmd.cmdidx = MMC_CMD_APP_CMD;
1315 cmd.resp_type = MMC_RSP_R1;
1316 cmd.cmdarg = mmc->rca << 16;
1318 err = mmc_send_cmd(mmc, &cmd, NULL);
1322 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1323 cmd.resp_type = MMC_RSP_R1;
1325 err = mmc_send_cmd(mmc, &cmd, NULL);
1329 mmc_set_bus_width(mmc, 4);
1332 if (mmc->card_caps & MMC_MODE_HS)
1333 mmc->tran_speed = 50000000;
1335 mmc->tran_speed = 25000000;
1336 } else if (mmc->version >= MMC_VERSION_4) {
1337 /* Only version 4 of MMC supports wider bus widths */
1340 /* An array of possible bus widths in order of preference */
1341 static unsigned ext_csd_bits[] = {
1342 EXT_CSD_DDR_BUS_WIDTH_8,
1343 EXT_CSD_DDR_BUS_WIDTH_4,
1344 EXT_CSD_BUS_WIDTH_8,
1345 EXT_CSD_BUS_WIDTH_4,
1346 EXT_CSD_BUS_WIDTH_1,
1349 /* An array to map CSD bus widths to host cap bits */
1350 static unsigned ext_to_hostcaps[] = {
1351 [EXT_CSD_DDR_BUS_WIDTH_4] =
1352 MMC_MODE_DDR_52MHz | MMC_MODE_4BIT,
1353 [EXT_CSD_DDR_BUS_WIDTH_8] =
1354 MMC_MODE_DDR_52MHz | MMC_MODE_8BIT,
1355 [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,
1356 [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,
1359 /* An array to map chosen bus width to an integer */
1360 static unsigned widths[] = {
1364 for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {
1365 unsigned int extw = ext_csd_bits[idx];
1366 unsigned int caps = ext_to_hostcaps[extw];
1369 * If the bus width is still not changed,
1370 * don't try to set the default again.
1371 * Otherwise, recover from switch attempts
1372 * by switching to 1-bit bus width.
1374 if (extw == EXT_CSD_BUS_WIDTH_1 &&
1375 mmc->bus_width == 1) {
1381 * Check to make sure the card and controller support
1382 * these capabilities
1384 if ((mmc->card_caps & caps) != caps)
1387 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1388 EXT_CSD_BUS_WIDTH, extw);
1393 mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0;
1394 mmc_set_bus_width(mmc, widths[idx]);
1396 err = mmc_send_ext_csd(mmc, test_csd);
1401 /* Only compare read only fields */
1402 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1403 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1404 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1405 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1406 ext_csd[EXT_CSD_REV]
1407 == test_csd[EXT_CSD_REV] &&
1408 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1409 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1410 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1411 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
1420 if (mmc->card_caps & MMC_MODE_HS) {
1421 if (mmc->card_caps & MMC_MODE_HS_52MHz)
1422 mmc->tran_speed = 52000000;
1424 mmc->tran_speed = 26000000;
1428 mmc_set_clock(mmc, mmc->tran_speed);
1430 /* Fix the block length for DDR mode */
1431 if (mmc->ddr_mode) {
1432 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
1433 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
1436 /* fill in device description */
1437 bdesc = mmc_get_blk_desc(mmc);
1441 bdesc->blksz = mmc->read_bl_len;
1442 bdesc->log2blksz = LOG2(bdesc->blksz);
1443 bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
1444 #if !defined(CONFIG_SPL_BUILD) || \
1445 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
1446 !defined(CONFIG_USE_TINY_PRINTF))
1447 sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
1448 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
1449 (mmc->cid[3] >> 16) & 0xffff);
1450 sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
1451 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
1452 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
1453 (mmc->cid[2] >> 24) & 0xff);
1454 sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
1455 (mmc->cid[2] >> 16) & 0xf);
1457 bdesc->vendor[0] = 0;
1458 bdesc->product[0] = 0;
1459 bdesc->revision[0] = 0;
1461 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
1468 static int mmc_send_if_cond(struct mmc *mmc)
1473 cmd.cmdidx = SD_CMD_SEND_IF_COND;
1474 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
1475 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
1476 cmd.resp_type = MMC_RSP_R7;
1478 err = mmc_send_cmd(mmc, &cmd, NULL);
1483 if ((cmd.response[0] & 0xff) != 0xaa)
1484 return UNUSABLE_ERR;
1486 mmc->version = SD_VERSION_2;
1491 /* board-specific MMC power initializations. */
1492 __weak void board_mmc_power_init(void)
1496 int mmc_start_init(struct mmc *mmc)
1500 /* we pretend there's no card when init is NULL */
1501 if (mmc_getcd(mmc) == 0 || mmc->cfg->ops->init == NULL) {
1503 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1504 printf("MMC: no card present\n");
1512 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
1513 mmc_adapter_card_type_ident();
1515 board_mmc_power_init();
1517 /* made sure it's not NULL earlier */
1518 err = mmc->cfg->ops->init(mmc);
1524 mmc_set_bus_width(mmc, 1);
1525 mmc_set_clock(mmc, 1);
1527 /* Reset the Card */
1528 err = mmc_go_idle(mmc);
1533 /* The internal partition reset to user partition(0) at every CMD0*/
1534 mmc_get_blk_desc(mmc)->hwpart = 0;
1536 /* Test for SD version 2 */
1537 err = mmc_send_if_cond(mmc);
1539 /* Now try to get the SD card's operating condition */
1540 err = sd_send_op_cond(mmc);
1542 /* If the command timed out, we check for an MMC card */
1543 if (err == TIMEOUT) {
1544 err = mmc_send_op_cond(mmc);
1547 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1548 printf("Card did not respond to voltage select!\n");
1550 return UNUSABLE_ERR;
1555 mmc->init_in_progress = 1;
1560 static int mmc_complete_init(struct mmc *mmc)
1564 mmc->init_in_progress = 0;
1565 if (mmc->op_cond_pending)
1566 err = mmc_complete_op_cond(mmc);
1569 err = mmc_startup(mmc);
1577 int mmc_init(struct mmc *mmc)
1581 #ifdef CONFIG_DM_MMC
1582 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
1589 start = get_timer(0);
1591 if (!mmc->init_in_progress)
1592 err = mmc_start_init(mmc);
1595 err = mmc_complete_init(mmc);
1596 debug("%s: %d, time %lu\n", __func__, err, get_timer(start));
1600 int mmc_set_dsr(struct mmc *mmc, u16 val)
1606 /* CPU-specific MMC initializations */
1607 __weak int cpu_mmc_init(bd_t *bis)
1612 /* board-specific MMC initializations. */
1613 __weak int board_mmc_init(bd_t *bis)
1618 void mmc_set_preinit(struct mmc *mmc, int preinit)
1620 mmc->preinit = preinit;
1623 #if defined(CONFIG_DM_MMC) && defined(CONFIG_SPL_BUILD)
1624 static int mmc_probe(bd_t *bis)
1628 #elif defined(CONFIG_DM_MMC)
1629 static int mmc_probe(bd_t *bis)
1633 struct udevice *dev;
1635 ret = uclass_get(UCLASS_MMC, &uc);
1640 * Try to add them in sequence order. Really with driver model we
1641 * should allow holes, but the current MMC list does not allow that.
1642 * So if we request 0, 1, 3 we will get 0, 1, 2.
1644 for (i = 0; ; i++) {
1645 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev);
1649 uclass_foreach_dev(dev, uc) {
1650 ret = device_probe(dev);
1652 printf("%s - probe failed: %d\n", dev->name, ret);
1658 static int mmc_probe(bd_t *bis)
1660 if (board_mmc_init(bis) < 0)
1667 int mmc_initialize(bd_t *bis)
1669 static int initialized = 0;
1671 if (initialized) /* Avoid initializing mmc multiple times */
1678 ret = mmc_probe(bis);
1682 #ifndef CONFIG_SPL_BUILD
1683 print_mmc_devices(',');
1690 #ifdef CONFIG_SUPPORT_EMMC_BOOT
1692 * This function changes the size of boot partition and the size of rpmb
1693 * partition present on EMMC devices.
1696 * struct *mmc: pointer for the mmc device strcuture
1697 * bootsize: size of boot partition
1698 * rpmbsize: size of rpmb partition
1700 * Returns 0 on success.
1703 int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
1704 unsigned long rpmbsize)
1709 /* Only use this command for raw EMMC moviNAND. Enter backdoor mode */
1710 cmd.cmdidx = MMC_CMD_RES_MAN;
1711 cmd.resp_type = MMC_RSP_R1b;
1712 cmd.cmdarg = MMC_CMD62_ARG1;
1714 err = mmc_send_cmd(mmc, &cmd, NULL);
1716 debug("mmc_boot_partition_size_change: Error1 = %d\n", err);
1720 /* Boot partition changing mode */
1721 cmd.cmdidx = MMC_CMD_RES_MAN;
1722 cmd.resp_type = MMC_RSP_R1b;
1723 cmd.cmdarg = MMC_CMD62_ARG2;
1725 err = mmc_send_cmd(mmc, &cmd, NULL);
1727 debug("mmc_boot_partition_size_change: Error2 = %d\n", err);
1730 /* boot partition size is multiple of 128KB */
1731 bootsize = (bootsize * 1024) / 128;
1733 /* Arg: boot partition size */
1734 cmd.cmdidx = MMC_CMD_RES_MAN;
1735 cmd.resp_type = MMC_RSP_R1b;
1736 cmd.cmdarg = bootsize;
1738 err = mmc_send_cmd(mmc, &cmd, NULL);
1740 debug("mmc_boot_partition_size_change: Error3 = %d\n", err);
1743 /* RPMB partition size is multiple of 128KB */
1744 rpmbsize = (rpmbsize * 1024) / 128;
1745 /* Arg: RPMB partition size */
1746 cmd.cmdidx = MMC_CMD_RES_MAN;
1747 cmd.resp_type = MMC_RSP_R1b;
1748 cmd.cmdarg = rpmbsize;
1750 err = mmc_send_cmd(mmc, &cmd, NULL);
1752 debug("mmc_boot_partition_size_change: Error4 = %d\n", err);
1759 * Modify EXT_CSD[177] which is BOOT_BUS_WIDTH
1760 * based on the passed in values for BOOT_BUS_WIDTH, RESET_BOOT_BUS_WIDTH
1763 * Returns 0 on success.
1765 int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode)
1769 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_BUS_WIDTH,
1770 EXT_CSD_BOOT_BUS_WIDTH_MODE(mode) |
1771 EXT_CSD_BOOT_BUS_WIDTH_RESET(reset) |
1772 EXT_CSD_BOOT_BUS_WIDTH_WIDTH(width));
1780 * Modify EXT_CSD[179] which is PARTITION_CONFIG (formerly BOOT_CONFIG)
1781 * based on the passed in values for BOOT_ACK, BOOT_PARTITION_ENABLE and
1784 * Returns 0 on success.
1786 int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access)
1790 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
1791 EXT_CSD_BOOT_ACK(ack) |
1792 EXT_CSD_BOOT_PART_NUM(part_num) |
1793 EXT_CSD_PARTITION_ACCESS(access));
1801 * Modify EXT_CSD[162] which is RST_n_FUNCTION based on the given value
1802 * for enable. Note that this is a write-once field for non-zero values.
1804 * Returns 0 on success.
1806 int mmc_set_rst_n_function(struct mmc *mmc, u8 enable)
1808 return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_RST_N_FUNCTION,