1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/spi/renesas,rzv2m-csi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/V2M Clocked Serial Interface (CSI)
14 - $ref: spi-controller.yaml#
18 const: renesas,rzv2m-csi
28 - description: The clock used to generate the output clock (CSICLK)
29 - description: Internal clock to access the registers (PCLK)
45 The CSI Slave Selection (SS) pin won't be used to enable transmission and
46 reception. Only available when in target mode.
60 renesas,csi-no-ss: [ spi-slave ]
62 unevaluatedProperties: false
66 #include <dt-bindings/interrupt-controller/arm-gic.h>
67 #include <dt-bindings/clock/r9a09g011-cpg.h>
69 compatible = "renesas,rzv2m-csi";
70 reg = <0xa4020200 0x80>;
71 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
72 clocks = <&cpg CPG_MOD R9A09G011_CSI4_CLK>,
73 <&cpg CPG_MOD R9A09G011_CPERI_GRPH_PCLK>;
74 clock-names = "csiclk", "pclk";
75 resets = <&cpg R9A09G011_CSI_GPH_PRESETN>;
76 power-domains = <&cpg>;