board/congatec/cgtqmx6eval/cgtqmx6eval.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
   4  * Based on mx6qsabrelite.c file
   5  * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
   6  * Leo Sartre, <[email protected]>
   7  */
   8
   9 #include <common.h>
  10 #include <init.h>
  11 #include <net.h>
  12 #include <asm/global_data.h>
  13 #include <asm/io.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/imx-regs.h>
  16 #include <asm/arch/iomux.h>
  17 #include <asm/arch/mx6-pins.h>
  18 #include <asm/gpio.h>
  19 #include <asm/mach-imx/iomux-v3.h>
  20 #include <asm/mach-imx/sata.h>
  21 #include <asm/mach-imx/boot_mode.h>
  22 #include <asm/mach-imx/mxc_i2c.h>
  23 #include <asm/arch/sys_proto.h>
  24 #include <asm/arch/mxc_hdmi.h>
  25 #include <asm/arch/crm_regs.h>
  26 #include <env.h>
  27 #include <mmc.h>
  28 #include <fsl_esdhc_imx.h>
  29 #include <i2c.h>
  30 #include <input.h>
  31 #include <linux/delay.h>
  32 #include <power/pmic.h>
  33 #include <power/pfuze100_pmic.h>
  34 #include <linux/fb.h>
  35 #include <ipu_pixfmt.h>
  36 #include <malloc.h>
  37 #include <miiphy.h>
  38 #include <netdev.h>
  39 #include <micrel.h>
  40 #include <spi_flash.h>
  41 #include <spi.h>
  42
  43 DECLARE_GLOBAL_DATA_PTR;
  44
  45 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |\
  46         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  47
  48 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |\
  49         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  50
  51 #define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
  52         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  53         PAD_CTL_DSE_40ohm | PAD_CTL_HYS |                       \
  54         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  55
  56 #define SPI_PAD_CTRL (PAD_CTL_HYS |                             \
  57         PAD_CTL_SPEED_MED |             \
  58         PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  59
  60 #define MX6Q_QMX6_PFUZE_MUX             IMX_GPIO_NR(6, 9)
  61
  62
  63 #define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  64         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
  65         PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
  66
  67 int dram_init(void)
  68 {
  69         gd->ram_size = imx_ddr_size();
  70
  71         return 0;
  72 }
  73
  74 static iomux_v3_cfg_t const uart2_pads[] = {
  75         IOMUX_PADS(PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  76         IOMUX_PADS(PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  77 };
  78
  79 #ifndef CONFIG_SPL_BUILD
  80 static iomux_v3_cfg_t const usdhc2_pads[] = {
  81         IOMUX_PADS(PAD_SD2_CLK__SD2_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  82         IOMUX_PADS(PAD_SD2_CMD__SD2_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  83         IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  84         IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  85         IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  86         IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  87         IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  88 };
  89
  90 static iomux_v3_cfg_t const usdhc3_pads[] = {
  91         IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  92         IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  93         IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  94         IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  95         IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  96         IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  97         IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  98         IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  99         IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 100         IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 101         IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 102 };
 103 #endif
 104
 105 static iomux_v3_cfg_t const usdhc4_pads[] = {
 106         IOMUX_PADS(PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 107         IOMUX_PADS(PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 108         IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 109         IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 110         IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 111         IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 112         IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 113         IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 114         IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 115         IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 116         IOMUX_PADS(PAD_NANDF_D6__GPIO2_IO06    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 117 };
 118
 119 static iomux_v3_cfg_t const usb_otg_pads[] = {
 120         IOMUX_PADS(PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)),
 121         IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
 122 };
 123
 124 static iomux_v3_cfg_t enet_pads_ksz9031[] = {
 125         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 126         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 127         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 128         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 129         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 130         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 131         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 132         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 133         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 134         IOMUX_PADS(PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 135         IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 136         IOMUX_PADS(PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 137         IOMUX_PADS(PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 138         IOMUX_PADS(PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 139         IOMUX_PADS(PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 140 };
 141
 142 static iomux_v3_cfg_t enet_pads_final_ksz9031[] = {
 143         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 144         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 145         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 146         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 147         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 148         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 149 };
 150
 151 static iomux_v3_cfg_t enet_pads_ar8035[] = {
 152         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 153         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 154         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 155         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 156         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 157         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 158         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 159         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 160         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 161         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 162         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 163         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 164         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 165         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 166         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 167 };
 168
 169 static iomux_v3_cfg_t const ecspi1_pads[] = {
 170         IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 171         IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 172         IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 173         IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 174 };
 175
 176 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 177 struct i2c_pads_info mx6q_i2c_pad_info1 = {
 178         .scl = {
 179                 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
 180                 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
 181                 .gp = IMX_GPIO_NR(4, 12)
 182         },
 183         .sda = {
 184                 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
 185                 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 186                 .gp = IMX_GPIO_NR(4, 13)
 187         }
 188 };
 189
 190 struct i2c_pads_info mx6dl_i2c_pad_info1 = {
 191         .scl = {
 192                 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
 193                 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
 194                 .gp = IMX_GPIO_NR(4, 12)
 195         },
 196         .sda = {
 197                 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
 198                 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 199                 .gp = IMX_GPIO_NR(4, 13)
 200         }
 201 };
 202
 203 #define I2C_PMIC        1       /* I2C2 port is used to connect to the PMIC */
 204
 205 struct interface_level {
 206         char *name;
 207         uchar value;
 208 };
 209
 210 static struct interface_level mipi_levels[] = {
 211         {"0V0", 0x00},
 212         {"2V5", 0x17},
 213 };
 214
 215 /* setup board specific PMIC */
 216 int power_init_board(void)
 217 {
 218         struct pmic *p;
 219         u32 id1, id2, i;
 220         int ret;
 221         char const *lv_mipi;
 222
 223         /* configure I2C multiplexer */
 224         gpio_direction_output(MX6Q_QMX6_PFUZE_MUX, 1);
 225
 226         power_pfuze100_init(I2C_PMIC);
 227         p = pmic_get("PFUZE100");
 228         if (!p)
 229                 return -EINVAL;
 230
 231         ret = pmic_probe(p);
 232         if (ret)
 233                 return ret;
 234
 235         pmic_reg_read(p, PFUZE100_DEVICEID, &id1);
 236         pmic_reg_read(p, PFUZE100_REVID, &id2);
 237         printf("PFUZE100 Rev. [%02x/%02x] detected\n", id1, id2);
 238
 239         if (id2 >= 0x20)
 240                 return 0;
 241
 242         /* set level of MIPI if specified */
 243         lv_mipi = env_get("lv_mipi");
 244         if (lv_mipi)
 245                 return 0;
 246
 247         for (i = 0; i < ARRAY_SIZE(mipi_levels); i++) {
 248                 if (!strcmp(mipi_levels[i].name, lv_mipi)) {
 249                         printf("set MIPI level %s\n", mipi_levels[i].name);
 250                         ret = pmic_reg_write(p, PFUZE100_VGEN4VOL,
 251                                              mipi_levels[i].value);
 252                         if (ret)
 253                                 return ret;
 254                 }
 255         }
 256
 257         return 0;
 258 }
 259
 260 int board_eth_init(struct bd_info *bis)
 261 {
 262         struct phy_device *phydev;
 263         struct mii_dev *bus;
 264         unsigned short id1, id2;
 265         int ret;
 266
 267         /* check whether KSZ9031 or AR8035 has to be configured */
 268         SETUP_IOMUX_PADS(enet_pads_ar8035);
 269
 270         /* phy reset */
 271         gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
 272         udelay(2000);
 273         gpio_set_value(IMX_GPIO_NR(3, 23), 1);
 274         udelay(500);
 275
 276         bus = fec_get_miibus(IMX_FEC_BASE, -1);
 277         if (!bus)
 278                 return -EINVAL;
 279         phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
 280         if (!phydev) {
 281                 printf("Error: phy device not found.\n");
 282                 ret = -ENODEV;
 283                 goto free_bus;
 284         }
 285
 286         /* get the PHY id */
 287         id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2);
 288         id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3);
 289
 290         if ((id1 == 0x22) && ((id2 & 0xFFF0) == 0x1620)) {
 291                 /* re-configure for Micrel KSZ9031 */
 292                 printf("configure Micrel KSZ9031 Ethernet Phy at address %d\n",
 293                        phydev->addr);
 294
 295                 /* phy reset: gpio3-23 */
 296                 gpio_set_value(IMX_GPIO_NR(3, 23), 0);
 297                 gpio_set_value(IMX_GPIO_NR(6, 30), (phydev->addr >> 2));
 298                 gpio_set_value(IMX_GPIO_NR(6, 25), 1);
 299                 gpio_set_value(IMX_GPIO_NR(6, 27), 1);
 300                 gpio_set_value(IMX_GPIO_NR(6, 28), 1);
 301                 gpio_set_value(IMX_GPIO_NR(6, 29), 1);
 302                 SETUP_IOMUX_PADS(enet_pads_ksz9031);
 303                 gpio_set_value(IMX_GPIO_NR(6, 24), 1);
 304                 udelay(500);
 305                 gpio_set_value(IMX_GPIO_NR(3, 23), 1);
 306                 SETUP_IOMUX_PADS(enet_pads_final_ksz9031);
 307         } else if ((id1 == 0x004d) && (id2 == 0xd072)) {
 308                 /* configure Atheros AR8035 - actually nothing to do */
 309                 printf("configure Atheros AR8035 Ethernet Phy at address %d\n",
 310                        phydev->addr);
 311         } else {
 312                 printf("Unknown Ethernet-Phy: 0x%04x 0x%04x\n", id1, id2);
 313                 ret = -EINVAL;
 314                 goto free_phydev;
 315         }
 316
 317         ret = fec_probe(bis, -1, IMX_FEC_BASE, bus, phydev);
 318         if (ret)
 319                 goto free_phydev;
 320
 321         return 0;
 322
 323 free_phydev:
 324         free(phydev);
 325 free_bus:
 326         free(bus);
 327         return ret;
 328 }
 329
 330 int mx6_rgmii_rework(struct phy_device *phydev)
 331 {
 332         unsigned short id1, id2;
 333         unsigned short val;
 334
 335         /* check whether KSZ9031 or AR8035 has to be configured */
 336         id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2);
 337         id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3);
 338
 339         if ((id1 == 0x22) && ((id2 & 0xFFF0) == 0x1620)) {
 340                 /* finalize phy configuration for Micrel KSZ9031 */
 341                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2);
 342                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 4);
 343                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2);
 344                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x0000);
 345
 346                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2);
 347                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 5);
 348                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2);
 349                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, MII_KSZ9031_MOD_REG);
 350
 351                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2);
 352                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 6);
 353                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2);
 354                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0xFFFF);
 355
 356                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2);
 357                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 8);
 358                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2);
 359                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x3FFF);
 360
 361                 /* fix KSZ9031 link up issue */
 362                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 0x0);
 363                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x4);
 364                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_NO_POST_INC);
 365                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x6);
 366                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_REG);
 367                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x3);
 368                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_NO_POST_INC);
 369                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x1A80);
 370         }
 371
 372         if ((id1 == 0x004d) && (id2 == 0xd072)) {
 373                 /* enable AR8035 ouput a 125MHz clk from CLK_25M */
 374                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 0x7);
 375                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, MII_KSZ9031_MOD_DATA_POST_INC_RW | 0x16);
 376                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_NO_POST_INC | 0x7);
 377                 val = phy_read(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA);
 378                 val &= 0xfe63;
 379                 val |= 0x18;
 380                 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, val);
 381
 382                 /* introduce tx clock delay */
 383                 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 384                 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 385                 val |= 0x0100;
 386                 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 387
 388                 /* disable hibernation */
 389                 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0xb);
 390                 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 391                 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3c40);
 392         }
 393         return 0;
 394 }
 395
 396 int board_phy_config(struct phy_device *phydev)
 397 {
 398         mx6_rgmii_rework(phydev);
 399
 400         if (phydev->drv->config)
 401                 phydev->drv->config(phydev);
 402
 403         return 0;
 404 }
 405
 406 static void setup_iomux_uart(void)
 407 {
 408         SETUP_IOMUX_PADS(uart2_pads);
 409 }
 410
 411 #ifdef CONFIG_MXC_SPI
 412 static void setup_spi(void)
 413 {
 414         SETUP_IOMUX_PADS(ecspi1_pads);
 415         gpio_direction_output(IMX_GPIO_NR(3, 19), 0);
 416 }
 417 #endif
 418
 419 #ifdef CONFIG_FSL_ESDHC_IMX
 420 static struct fsl_esdhc_cfg usdhc_cfg[] = {
 421         {USDHC2_BASE_ADDR},
 422         {USDHC3_BASE_ADDR},
 423         {USDHC4_BASE_ADDR},
 424 };
 425
 426 int board_mmc_getcd(struct mmc *mmc)
 427 {
 428         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 429         int ret = 0;
 430
 431         switch (cfg->esdhc_base) {
 432         case USDHC2_BASE_ADDR:
 433                 gpio_direction_input(IMX_GPIO_NR(1, 4));
 434                 ret = !gpio_get_value(IMX_GPIO_NR(1, 4));
 435                 break;
 436         case USDHC3_BASE_ADDR:
 437                 ret = 1;        /* eMMC is always present */
 438                 break;
 439         case USDHC4_BASE_ADDR:
 440                 gpio_direction_input(IMX_GPIO_NR(2, 6));
 441                 ret = !gpio_get_value(IMX_GPIO_NR(2, 6));
 442                 break;
 443         default:
 444                 printf("Bad USDHC interface\n");
 445         }
 446
 447         return ret;
 448 }
 449
 450 int board_mmc_init(struct bd_info *bis)
 451 {
 452 #ifndef CONFIG_SPL_BUILD
 453         s32 status = 0;
 454         int i;
 455
 456         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 457         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 458         usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 459
 460         SETUP_IOMUX_PADS(usdhc2_pads);
 461         SETUP_IOMUX_PADS(usdhc3_pads);
 462         SETUP_IOMUX_PADS(usdhc4_pads);
 463
 464         for (i = 0; i < ARRAY_SIZE(usdhc_cfg); i++) {
 465                 status = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 466                 if (status)
 467                         return status;
 468         }
 469
 470         return 0;
 471 #else
 472         SETUP_IOMUX_PADS(usdhc4_pads);
 473         usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
 474         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 475         gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 476
 477         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 478 #endif
 479 }
 480 #endif
 481
 482 int board_ehci_hcd_init(int port)
 483 {
 484         switch (port) {
 485         case 0:
 486                 SETUP_IOMUX_PADS(usb_otg_pads);
 487                 /*
 488                  * set daisy chain for otg_pin_id on 6q.
 489                  * for 6dl, this bit is reserved
 490                  */
 491                 imx_iomux_set_gpr_register(1, 13, 1, 1);
 492                 break;
 493         case 1:
 494                 /* nothing to do */
 495                 break;
 496         default:
 497                 printf("Invalid USB port: %d\n", port);
 498                 return -EINVAL;
 499         }
 500
 501         return 0;
 502 }
 503
 504 int board_ehci_power(int port, int on)
 505 {
 506         switch (port) {
 507         case 0:
 508                 break;
 509         case 1:
 510                 gpio_direction_output(IMX_GPIO_NR(5, 5), on);
 511                 break;
 512         default:
 513                 printf("Invalid USB port: %d\n", port);
 514                 return -EINVAL;
 515         }
 516
 517         return 0;
 518 }
 519
 520 struct display_info_t {
 521         int bus;
 522         int addr;
 523         int pixfmt;
 524         int (*detect)(struct display_info_t const *dev);
 525         void (*enable)(struct display_info_t const *dev);
 526         struct fb_videomode mode;
 527 };
 528
 529 static void disable_lvds(struct display_info_t const *dev)
 530 {
 531         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 532
 533         clrbits_le32(&iomux->gpr[2], IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
 534                      IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
 535 }
 536
 537 static void do_enable_hdmi(struct display_info_t const *dev)
 538 {
 539         disable_lvds(dev);
 540         imx_enable_hdmi_phy();
 541 }
 542
 543 static struct display_info_t const displays[] = {
 544 {
 545         .bus = -1,
 546         .addr = 0,
 547         .pixfmt = IPU_PIX_FMT_RGB666,
 548         .detect = NULL,
 549         .enable = NULL,
 550         .mode = {
 551                 .name =
 552                 "Hannstar-XGA",
 553                 .refresh = 60,
 554                 .xres = 1024,
 555                 .yres = 768,
 556                 .pixclock = 15385,
 557                 .left_margin = 220,
 558                 .right_margin = 40,
 559                 .upper_margin = 21,
 560                 .lower_margin = 7,
 561                 .hsync_len = 60,
 562                 .vsync_len = 10,
 563                 .sync = FB_SYNC_EXT,
 564                 .vmode = FB_VMODE_NONINTERLACED } },
 565 {
 566         .bus = -1,
 567         .addr = 0,
 568         .pixfmt = IPU_PIX_FMT_RGB24,
 569         .detect = NULL,
 570         .enable = do_enable_hdmi,
 571         .mode = {
 572                 .name = "HDMI",
 573                 .refresh = 60,
 574                 .xres = 1024,
 575                 .yres = 768,
 576                 .pixclock = 15385,
 577                 .left_margin = 220,
 578                 .right_margin = 40,
 579                 .upper_margin = 21,
 580                 .lower_margin = 7,
 581                 .hsync_len = 60,
 582                 .vsync_len = 10,
 583                 .sync = FB_SYNC_EXT,
 584                 .vmode = FB_VMODE_NONINTERLACED } }
 585 };
 586
 587 int board_video_skip(void)
 588 {
 589         int i;
 590         int ret;
 591         char const *panel = env_get("panel");
 592         if (!panel) {
 593                 for (i = 0; i < ARRAY_SIZE(displays); i++) {
 594                         struct display_info_t const *dev = displays + i;
 595                         if (dev->detect && dev->detect(dev)) {
 596                                 panel = dev->mode.name;
 597                                 printf("auto-detected panel %s\n", panel);
 598                                 break;
 599                         }
 600                 }
 601                 if (!panel) {
 602                         panel = displays[0].mode.name;
 603                         printf("No panel detected: default to %s\n", panel);
 604                         i = 0;
 605                 }
 606         } else {
 607                 for (i = 0; i < ARRAY_SIZE(displays); i++) {
 608                         if (!strcmp(panel, displays[i].mode.name))
 609                                 break;
 610                 }
 611         }
 612         if (i < ARRAY_SIZE(displays)) {
 613                 ret = ipuv3_fb_init(&displays[i].mode, 0, displays[i].pixfmt);
 614                 if (!ret) {
 615                         if (displays[i].enable)
 616                                 displays[i].enable(displays + i);
 617                         printf("Display: %s (%ux%u)\n",
 618                                displays[i].mode.name, displays[i].mode.xres,
 619                                displays[i].mode.yres);
 620                 } else
 621                         printf("LCD %s cannot be configured: %d\n",
 622                                displays[i].mode.name, ret);
 623         } else {
 624                 printf("unsupported panel %s\n", panel);
 625                 return -EINVAL;
 626         }
 627
 628         return 0;
 629 }
 630
 631 int ipu_displays_init(void)
 632 {
 633         return board_video_skip();
 634 }
 635
 636 static void setup_display(void)
 637 {
 638         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 639         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 640         int reg;
 641
 642         enable_ipu_clock();
 643         imx_setup_hdmi();
 644
 645         /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
 646         setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK |
 647                      MXC_CCM_CCGR3_LDB_DI1_MASK);
 648
 649         /* set LDB0, LDB1 clk select to 011/011 */
 650         reg = readl(&mxc_ccm->cs2cdr);
 651         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
 652                  MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 653         reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
 654                 (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 655         writel(reg, &mxc_ccm->cs2cdr);
 656
 657         setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV |
 658                      MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV);
 659
 660         setbits_le32(&mxc_ccm->chsccdr, CHSCCDR_CLK_SEL_LDB_DI0 <<
 661                      MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET |
 662                      CHSCCDR_CLK_SEL_LDB_DI0 <<
 663                      MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
 664
 665         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 666                 | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
 667                 | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 668                 | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 669                 | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 670                 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 671                 | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 672                 | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
 673                 | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
 674         writel(reg, &iomux->gpr[2]);
 675
 676         reg = readl(&iomux->gpr[3]);
 677         reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
 678                        IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) |
 679                 (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
 680                  IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
 681         writel(reg, &iomux->gpr[3]);
 682 }
 683
 684 /*
 685  * Do not overwrite the console
 686  * Use always serial for U-Boot console
 687  */
 688 int overwrite_console(void)
 689 {
 690         return 1;
 691 }
 692
 693 int board_early_init_f(void)
 694 {
 695         setup_iomux_uart();
 696 #ifdef CONFIG_MXC_SPI
 697         setup_spi();
 698 #endif
 699         return 0;
 700 }
 701
 702 int board_init(void)
 703 {
 704         /* address of boot parameters */
 705         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 706
 707
 708         if (is_mx6dq())
 709                 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
 710         else
 711                 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
 712
 713         setup_display();
 714
 715 #ifdef CONFIG_SATA
 716         setup_sata();
 717 #endif
 718
 719         return 0;
 720 }
 721
 722 int checkboard(void)
 723 {
 724         char *type = "unknown";
 725
 726         if (is_cpu_type(MXC_CPU_MX6Q))
 727                 type = "Quad";
 728         else if (is_cpu_type(MXC_CPU_MX6D))
 729                 type = "Dual";
 730         else if (is_cpu_type(MXC_CPU_MX6DL))
 731                 type = "Dual-Lite";
 732         else if (is_cpu_type(MXC_CPU_MX6SOLO))
 733                 type = "Solo";
 734
 735         printf("Board: conga-QMX6 %s\n", type);
 736
 737         return 0;
 738 }
 739
 740 #ifdef CONFIG_MXC_SPI
 741 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 742 {
 743         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -EINVAL;
 744 }
 745 #endif
 746
 747 #ifdef CONFIG_CMD_BMODE
 748 static const struct boot_mode board_boot_modes[] = {
 749         /* 4 bit bus width */
 750         {"mmc0",        MAKE_CFGVAL(0x50, 0x20, 0x00, 0x00)},
 751         {"mmc1",        MAKE_CFGVAL(0x50, 0x38, 0x00, 0x00)},
 752         {NULL,          0},
 753 };
 754 #endif
 755
 756 int misc_init_r(void)
 757 {
 758 #ifdef CONFIG_CMD_BMODE
 759         add_board_boot_modes(board_boot_modes);
 760 #endif
 761         return 0;
 762 }
 763
 764 int board_late_init(void)
 765 {
 766 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 767         if (is_mx6dq())
 768                 env_set("board_rev", "MX6Q");
 769         else
 770                 env_set("board_rev", "MX6DL");
 771 #endif
 772
 773         return 0;
 774 }
 775
 776 #ifdef CONFIG_SPL_BUILD
 777 #include <asm/arch/mx6-ddr.h>
 778 #include <spl.h>
 779 #include <linux/libfdt.h>
 780 #include <spi_flash.h>
 781 #include <spi.h>
 782
 783 const struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = {
 784         .dram_sdclk_0 =  0x00000030,
 785         .dram_sdclk_1 =  0x00000030,
 786         .dram_cas =  0x00000030,
 787         .dram_ras =  0x00000030,
 788         .dram_reset =  0x00000030,
 789         .dram_sdcke0 =  0x00003000,
 790         .dram_sdcke1 =  0x00003000,
 791         .dram_sdba2 =  0x00000000,
 792         .dram_sdodt0 =  0x00000030,
 793         .dram_sdodt1 =  0x00000030,
 794         .dram_sdqs0 =  0x00000030,
 795         .dram_sdqs1 =  0x00000030,
 796         .dram_sdqs2 =  0x00000030,
 797         .dram_sdqs3 =  0x00000030,
 798         .dram_sdqs4 =  0x00000030,
 799         .dram_sdqs5 =  0x00000030,
 800         .dram_sdqs6 =  0x00000030,
 801         .dram_sdqs7 =  0x00000030,
 802         .dram_dqm0 =  0x00000030,
 803         .dram_dqm1 =  0x00000030,
 804         .dram_dqm2 =  0x00000030,
 805         .dram_dqm3 =  0x00000030,
 806         .dram_dqm4 =  0x00000030,
 807         .dram_dqm5 =  0x00000030,
 808         .dram_dqm6 =  0x00000030,
 809         .dram_dqm7 =  0x00000030,
 810 };
 811
 812 static const struct mx6sdl_iomux_ddr_regs mx6dl_ddr_ioregs = {
 813         .dram_sdclk_0 = 0x00000030,
 814         .dram_sdclk_1 = 0x00000030,
 815         .dram_cas =     0x00000030,
 816         .dram_ras =     0x00000030,
 817         .dram_reset =   0x00000030,
 818         .dram_sdcke0 =  0x00003000,
 819         .dram_sdcke1 =  0x00003000,
 820         .dram_sdba2 =   0x00000000,
 821         .dram_sdodt0 =  0x00000030,
 822         .dram_sdodt1 =  0x00000030,
 823         .dram_sdqs0 =   0x00000030,
 824         .dram_sdqs1 =   0x00000030,
 825         .dram_sdqs2 =   0x00000030,
 826         .dram_sdqs3 =   0x00000030,
 827         .dram_sdqs4 =   0x00000030,
 828         .dram_sdqs5 =   0x00000030,
 829         .dram_sdqs6 =   0x00000030,
 830         .dram_sdqs7 =   0x00000030,
 831         .dram_dqm0 =    0x00000030,
 832         .dram_dqm1 =    0x00000030,
 833         .dram_dqm2 =    0x00000030,
 834         .dram_dqm3 =    0x00000030,
 835         .dram_dqm4 =    0x00000030,
 836         .dram_dqm5 =    0x00000030,
 837         .dram_dqm6 =    0x00000030,
 838         .dram_dqm7 =    0x00000030,
 839 };
 840
 841 const struct mx6dq_iomux_grp_regs mx6q_grp_ioregs = {
 842         .grp_ddr_type =  0x000C0000,
 843         .grp_ddrmode_ctl =  0x00020000,
 844         .grp_ddrpke =  0x00000000,
 845         .grp_addds =  0x00000030,
 846         .grp_ctlds =  0x00000030,
 847         .grp_ddrmode =  0x00020000,
 848         .grp_b0ds =  0x00000030,
 849         .grp_b1ds =  0x00000030,
 850         .grp_b2ds =  0x00000030,
 851         .grp_b3ds =  0x00000030,
 852         .grp_b4ds =  0x00000030,
 853         .grp_b5ds =  0x00000030,
 854         .grp_b6ds =  0x00000030,
 855         .grp_b7ds =  0x00000030,
 856 };
 857
 858 static const struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
 859         .grp_ddr_type = 0x000c0000,
 860         .grp_ddrmode_ctl = 0x00020000,
 861         .grp_ddrpke = 0x00000000,
 862         .grp_addds = 0x00000030,
 863         .grp_ctlds = 0x00000030,
 864         .grp_ddrmode = 0x00020000,
 865         .grp_b0ds = 0x00000030,
 866         .grp_b1ds = 0x00000030,
 867         .grp_b2ds = 0x00000030,
 868         .grp_b3ds = 0x00000030,
 869         .grp_b4ds = 0x00000030,
 870         .grp_b5ds = 0x00000030,
 871         .grp_b6ds = 0x00000030,
 872         .grp_b7ds = 0x00000030,
 873 };
 874
 875 const struct mx6_mmdc_calibration mx6q_mmcd_calib = {
 876         .p0_mpwldectrl0 =  0x0016001A,
 877         .p0_mpwldectrl1 =  0x0023001C,
 878         .p1_mpwldectrl0 =  0x0028003A,
 879         .p1_mpwldectrl1 =  0x001F002C,
 880         .p0_mpdgctrl0 =  0x43440354,
 881         .p0_mpdgctrl1 =  0x033C033C,
 882         .p1_mpdgctrl0 =  0x43300368,
 883         .p1_mpdgctrl1 =  0x03500330,
 884         .p0_mprddlctl =  0x3228242E,
 885         .p1_mprddlctl =  0x2C2C2636,
 886         .p0_mpwrdlctl =  0x36323A38,
 887         .p1_mpwrdlctl =  0x42324440,
 888 };
 889
 890 const struct mx6_mmdc_calibration mx6q_2g_mmcd_calib = {
 891         .p0_mpwldectrl0 =  0x00080016,
 892         .p0_mpwldectrl1 =  0x001D0016,
 893         .p1_mpwldectrl0 =  0x0018002C,
 894         .p1_mpwldectrl1 =  0x000D001D,
 895         .p0_mpdgctrl0 =    0x43200334,
 896         .p0_mpdgctrl1 =    0x0320031C,
 897         .p1_mpdgctrl0 =    0x0344034C,
 898         .p1_mpdgctrl1 =    0x03380314,
 899         .p0_mprddlctl =    0x3E36383A,
 900         .p1_mprddlctl =    0x38363240,
 901         .p0_mpwrdlctl =    0x36364238,
 902         .p1_mpwrdlctl =    0x4230423E,
 903 };
 904
 905 static const struct mx6_mmdc_calibration mx6s_mmcd_calib = {
 906         .p0_mpwldectrl0 =  0x00480049,
 907         .p0_mpwldectrl1 =  0x00410044,
 908         .p0_mpdgctrl0 =    0x42480248,
 909         .p0_mpdgctrl1 =    0x023C023C,
 910         .p0_mprddlctl =    0x40424644,
 911         .p0_mpwrdlctl =    0x34323034,
 912 };
 913
 914 const struct mx6_mmdc_calibration mx6dl_mmcd_calib = {
 915         .p0_mpwldectrl0 =  0x0043004B,
 916         .p0_mpwldectrl1 =  0x003A003E,
 917         .p1_mpwldectrl0 =  0x0047004F,
 918         .p1_mpwldectrl1 =  0x004E0061,
 919         .p0_mpdgctrl0 =    0x42500250,
 920         .p0_mpdgctrl1 =    0x0238023C,
 921         .p1_mpdgctrl0 =    0x42640264,
 922         .p1_mpdgctrl1 =    0x02500258,
 923         .p0_mprddlctl =    0x40424846,
 924         .p1_mprddlctl =    0x46484842,
 925         .p0_mpwrdlctl =    0x38382C30,
 926         .p1_mpwrdlctl =    0x34343430,
 927 };
 928
 929 static struct mx6_ddr3_cfg mem_ddr_2g = {
 930         .mem_speed = 1600,
 931         .density = 2,
 932         .width = 16,
 933         .banks = 8,
 934         .rowaddr = 14,
 935         .coladdr = 10,
 936         .pagesz = 2,
 937         .trcd = 1310,
 938         .trcmin = 4875,
 939         .trasmin = 3500,
 940 };
 941
 942 static struct mx6_ddr3_cfg mem_ddr_4g = {
 943         .mem_speed = 1600,
 944         .density = 4,
 945         .width = 16,
 946         .banks = 8,
 947         .rowaddr = 15,
 948         .coladdr = 10,
 949         .pagesz = 2,
 950         .trcd = 1310,
 951         .trcmin = 4875,
 952         .trasmin = 3500,
 953 };
 954
 955 static void ccgr_init(void)
 956 {
 957         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 958
 959         writel(0x00C03F3F, &ccm->CCGR0);
 960         writel(0x0030FC03, &ccm->CCGR1);
 961         writel(0x0FFFC000, &ccm->CCGR2);
 962         writel(0x3FF00000, &ccm->CCGR3);
 963         writel(0x00FFF300, &ccm->CCGR4);
 964         writel(0x0F0000C3, &ccm->CCGR5);
 965         writel(0x000003FF, &ccm->CCGR6);
 966 }
 967
 968 /* Define a minimal structure so that the part number can be read via SPL */
 969 struct mfgdata {
 970         unsigned char tsize;
 971         /* size of checksummed part in bytes */
 972         unsigned char ckcnt;
 973         /* checksum corrected byte */
 974         unsigned char cksum;
 975         /* decimal serial number, packed BCD */
 976         unsigned char serial[6];
 977          /* part number, right justified, ASCII */
 978         unsigned char pn[16];
 979 };
 980
 981 static void conv_ascii(unsigned char *dst, unsigned char *src, int len)
 982 {
 983         int remain = len;
 984         unsigned char *sptr = src;
 985         unsigned char *dptr = dst;
 986
 987         while (remain) {
 988                 if (*sptr) {
 989                         *dptr = *sptr;
 990                         dptr++;
 991                 }
 992                 sptr++;
 993                 remain--;
 994         }
 995         *dptr = 0x0;
 996 }
 997
 998 #define CFG_MFG_ADDR_OFFSET     (spi->size - SZ_16K)
 999 static bool is_2gb(void)
1000 {
1001         struct spi_flash *spi;
1002         int ret;
1003         char buf[sizeof(struct mfgdata)];
1004         struct mfgdata *data = (struct mfgdata *)buf;
1005         unsigned char outbuf[32];
1006
1007         spi = spi_flash_probe(CONFIG_ENV_SPI_BUS,
1008                               CONFIG_ENV_SPI_CS,
1009                               CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
1010         ret = spi_flash_read(spi, CFG_MFG_ADDR_OFFSET, sizeof(struct mfgdata),
1011                              buf);
1012         if (ret)
1013                 return false;
1014
1015         /* Congatec Part Numbers 104 and 105 have 2GiB of RAM */
1016         conv_ascii(outbuf, data->pn, sizeof(data->pn));
1017         if (!memcmp(outbuf, "016104", 6) || !memcmp(outbuf, "016105", 6))
1018                 return true;
1019         else
1020                 return false;
1021 }
1022
1023 static void spl_dram_init(int width)
1024 {
1025         struct mx6_ddr_sysinfo sysinfo = {
1026                 /* width of data bus:0=16,1=32,2=64 */
1027                 .dsize = width / 32,
1028                 /* config for full 4GB range so that get_mem_size() works */
1029                 .cs_density = 32, /* 32Gb per CS */
1030                 /* single chip select */
1031                 .ncs = 1,
1032                 .cs1_mirror = 0,
1033                 .rtt_wr = 2,
1034                 .rtt_nom = 2,
1035                 .walat = 0,
1036                 .ralat = 5,
1037                 .mif3_mode = 3,
1038                 .bi_on = 1,
1039                 .sde_to_rst = 0x0d,
1040                 .rst_to_cke = 0x20,
1041                 .refsel = 1,    /* Refresh cycles at 32KHz */
1042                 .refr = 7,      /* 8 refresh commands per refresh cycle */
1043         };
1044
1045         if (is_cpu_type(MXC_CPU_MX6Q) && is_2gb()) {
1046                 mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs);
1047                 mx6_dram_cfg(&sysinfo, &mx6q_2g_mmcd_calib, &mem_ddr_4g);
1048                 return;
1049         }
1050
1051         if (is_mx6dq()) {
1052                 mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs);
1053                 mx6_dram_cfg(&sysinfo, &mx6q_mmcd_calib, &mem_ddr_2g);
1054         } else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
1055                 sysinfo.walat = 1;
1056                 mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs);
1057                 mx6_dram_cfg(&sysinfo, &mx6s_mmcd_calib, &mem_ddr_4g);
1058         } else if (is_cpu_type(MXC_CPU_MX6DL)) {
1059                 sysinfo.walat = 1;
1060                 mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs);
1061                 mx6_dram_cfg(&sysinfo, &mx6dl_mmcd_calib, &mem_ddr_2g);
1062         }
1063 }
1064
1065 void board_init_f(ulong dummy)
1066 {
1067         /* setup AIPS and disable watchdog */
1068         arch_cpu_init();
1069
1070         ccgr_init();
1071         gpr_init();
1072
1073         /* iomux and setup of i2c */
1074         board_early_init_f();
1075
1076         /* setup GP timer */
1077         timer_init();
1078
1079         /* UART clocks enabled and gd valid - init serial console */
1080         preloader_console_init();
1081
1082         /* Needed for malloc() to work in SPL prior to board_init_r() */
1083         spl_init();
1084
1085         /* DDR initialization */
1086         if (is_cpu_type(MXC_CPU_MX6SOLO))
1087                 spl_dram_init(32);
1088         else
1089                 spl_dram_init(64);
1090
1091         /* Clear the BSS. */
1092         memset(__bss_start, 0, __bss_end - __bss_start);
1093
1094         /* load/boot image from boot device */
1095         board_init_r(NULL, 0);
1096 }
1097 #endif