1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
6 #include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
7 #include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>
8 #include <dt-bindings/gpio/meson-a1-gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/power/meson-a1-power.h>
12 #include <dt-bindings/reset/amlogic,meson-a1-reset.h>
15 compatible = "amlogic,a1";
17 interrupt-parent = <&gic>;
27 compatible = "arm,cortex-a35";
29 enable-method = "psci";
30 next-level-cache = <&l2>;
35 compatible = "arm,cortex-a35";
37 enable-method = "psci";
38 next-level-cache = <&l2>;
49 compatible = "amlogic,meson-gxbb-efuse";
50 clocks = <&clkc_periphs CLKID_OTP>;
53 secure-monitor = <&sm>;
54 power-domains = <&pwrc PWRC_OTP_ID>;
58 compatible = "arm,psci-1.0";
68 compatible = "shared-dma-pool";
70 size = <0x0 0x800000>;
71 alignment = <0x0 0x400000>;
77 compatible = "amlogic,meson-gxbb-sm";
79 pwrc: power-controller {
80 compatible = "amlogic,meson-a1-pwrc";
81 #power-domain-cells = <1>;
86 compatible = "simple-bus";
92 compatible = "amlogic,a1-spifc";
93 reg = <0x0 0xfd000400 0x0 0x290>;
94 clocks = <&clkc_periphs CLKID_SPIFC>;
97 power-domains = <&pwrc PWRC_SPIFC_ID>;
102 compatible = "simple-bus";
103 reg = <0x0 0xfe000000 0x0 0x1000000>;
104 #address-cells = <2>;
106 ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>;
108 reset: reset-controller@0 {
109 compatible = "amlogic,meson-a1-reset";
110 reg = <0x0 0x0 0x0 0x8c>;
114 periphs_pinctrl: pinctrl@400 {
115 compatible = "amlogic,meson-a1-periphs-pinctrl";
116 #address-cells = <2>;
121 reg = <0x0 0x0400 0x0 0x003c>,
122 <0x0 0x0480 0x0 0x0118>;
123 reg-names = "mux", "gpio";
126 gpio-ranges = <&periphs_pinctrl 0 0 62>;
129 i2c0_f11_pins: i2c0-f11 {
131 groups = "i2c0_sck_f11",
135 drive-strength-microamp = <3000>;
139 i2c0_f9_pins: i2c0-f9 {
141 groups = "i2c0_sck_f9",
145 drive-strength-microamp = <3000>;
149 i2c1_x_pins: i2c1-x {
151 groups = "i2c1_sck_x",
155 drive-strength-microamp = <3000>;
159 i2c1_a_pins: i2c1-a {
161 groups = "i2c1_sck_a",
165 drive-strength-microamp = <3000>;
169 i2c2_x0_pins: i2c2-x0 {
171 groups = "i2c2_sck_x0",
175 drive-strength-microamp = <3000>;
179 i2c2_x15_pins: i2c2-x15 {
181 groups = "i2c2_sck_x15",
185 drive-strength-microamp = <3000>;
189 i2c2_a4_pins: i2c2-a4 {
191 groups = "i2c2_sck_a4",
195 drive-strength-microamp = <3000>;
199 i2c2_a8_pins: i2c2-a8 {
201 groups = "i2c2_sck_a8",
205 drive-strength-microamp = <3000>;
209 i2c3_x_pins: i2c3-x {
211 groups = "i2c3_sck_x",
215 drive-strength-microamp = <3000>;
219 i2c3_f_pins: i2c3-f {
221 groups = "i2c3_sck_f",
225 drive-strength-microamp = <3000>;
229 uart_a_pins: uart-a {
231 groups = "uart_a_tx",
237 uart_a_cts_rts_pins: uart-a-cts-rts {
239 groups = "uart_a_cts",
248 groups = "sdcard_d0_x",
258 groups = "sdcard_clk_x";
264 sdio_clk_gate_pins: sdio-clk-gate {
266 groups = "sdcard_clk_x";
285 gpio_intc: interrupt-controller@440 {
286 compatible = "amlogic,meson-a1-gpio-intc",
287 "amlogic,meson-gpio-intc";
288 reg = <0x0 0x0440 0x0 0x14>;
289 interrupt-controller;
290 #interrupt-cells = <2>;
291 amlogic,channel-interrupts =
292 <49 50 51 52 53 54 55 56>;
295 clkc_periphs: clock-controller@800 {
296 compatible = "amlogic,a1-peripherals-clkc";
297 reg = <0 0x800 0 0x104>;
299 clocks = <&clkc_pll CLKID_FCLK_DIV2>,
300 <&clkc_pll CLKID_FCLK_DIV3>,
301 <&clkc_pll CLKID_FCLK_DIV5>,
302 <&clkc_pll CLKID_FCLK_DIV7>,
303 <&clkc_pll CLKID_HIFI_PLL>,
305 clock-names = "fclk_div2", "fclk_div3",
306 "fclk_div5", "fclk_div7",
311 compatible = "amlogic,meson-axg-i2c";
313 reg = <0x0 0x1400 0x0 0x20>;
314 interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>;
315 #address-cells = <1>;
317 clocks = <&clkc_periphs CLKID_I2C_M_A>;
318 power-domains = <&pwrc PWRC_I2C_ID>;
321 uart_AO: serial@1c00 {
322 compatible = "amlogic,meson-a1-uart",
323 "amlogic,meson-ao-uart";
324 reg = <0x0 0x1c00 0x0 0x18>;
325 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
326 clocks = <&xtal>, <&xtal>, <&xtal>;
327 clock-names = "xtal", "pclk", "baud";
331 uart_AO_B: serial@2000 {
332 compatible = "amlogic,meson-a1-uart",
333 "amlogic,meson-ao-uart";
334 reg = <0x0 0x2000 0x0 0x18>;
335 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
336 clocks = <&xtal>, <&xtal>, <&xtal>;
337 clock-names = "xtal", "pclk", "baud";
342 compatible = "amlogic,meson-g12a-saradc",
343 "amlogic,meson-saradc";
344 reg = <0x0 0x2c00 0x0 0x48>;
345 #io-channel-cells = <1>;
346 power-domains = <&pwrc PWRC_I2C_ID>;
347 interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>;
349 <&clkc_periphs CLKID_SARADC_EN>,
350 <&clkc_periphs CLKID_SARADC>,
351 <&clkc_periphs CLKID_SARADC_SEL>;
352 clock-names = "clkin", "core",
353 "adc_clk", "adc_sel";
358 compatible = "amlogic,meson-axg-i2c";
360 reg = <0x0 0x5c00 0x0 0x20>;
361 interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
362 #address-cells = <1>;
364 clocks = <&clkc_periphs CLKID_I2C_M_B>;
365 power-domains = <&pwrc PWRC_I2C_ID>;
369 compatible = "amlogic,meson-axg-i2c";
371 reg = <0x0 0x6800 0x0 0x20>;
372 interrupts = <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>;
373 #address-cells = <1>;
375 clocks = <&clkc_periphs CLKID_I2C_M_C>;
376 power-domains = <&pwrc PWRC_I2C_ID>;
380 compatible = "amlogic,meson-axg-i2c";
382 reg = <0x0 0x6c00 0x0 0x20>;
383 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>;
384 #address-cells = <1>;
386 clocks = <&clkc_periphs CLKID_I2C_M_D>;
387 power-domains = <&pwrc PWRC_I2C_ID>;
390 usb2_phy1: phy@4000 {
391 compatible = "amlogic,a1-usb2-phy";
392 clocks = <&clkc_periphs CLKID_USB_PHY_IN>;
393 clock-names = "xtal";
394 reg = <0x0 0x4000 0x0 0x60>;
395 resets = <&reset RESET_USBPHY>;
398 power-domains = <&pwrc PWRC_USB_ID>;
402 compatible = "amlogic,meson-rng";
403 reg = <0x0 0x5118 0x0 0x4>;
404 power-domains = <&pwrc PWRC_OTP_ID>;
407 sec_AO: ao-secure@5a20 {
408 compatible = "amlogic,meson-gx-ao-secure", "syscon";
409 reg = <0x0 0x5a20 0x0 0x140>;
413 clkc_pll: pll-clock-controller@7c80 {
414 compatible = "amlogic,a1-pll-clkc";
415 reg = <0 0x7c80 0 0x18c>;
417 clocks = <&clkc_periphs CLKID_FIXPLL_IN>,
418 <&clkc_periphs CLKID_HIFIPLL_IN>;
419 clock-names = "fixpll_in", "hifipll_in";
423 compatible = "amlogic,meson-axg-mmc";
424 reg = <0x0 0x10000 0x0 0x800>;
425 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
426 clocks = <&clkc_periphs CLKID_SD_EMMC_A>,
427 <&clkc_periphs CLKID_SD_EMMC>,
428 <&clkc_pll CLKID_FCLK_DIV2>;
429 clock-names = "core",
432 assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_SEL2>;
433 assigned-clock-parents = <&xtal>;
434 resets = <&reset RESET_SD_EMMC_A>;
435 power-domains = <&pwrc PWRC_SD_EMMC_ID>;
442 compatible = "amlogic,meson-a1-usb-ctrl";
443 reg = <0x0 0xfe004400 0x0 0xa0>;
444 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
445 #address-cells = <2>;
449 clocks = <&clkc_periphs CLKID_USB_CTRL>,
450 <&clkc_periphs CLKID_USB_BUS>,
451 <&clkc_periphs CLKID_USB_CTRL_IN>;
452 clock-names = "usb_ctrl", "usb_bus", "xtal_usb_ctrl";
453 resets = <&reset RESET_USBCTRL>;
454 reset-name = "usb_ctrl";
459 phy-names = "usb2-phy1";
462 compatible = "snps,dwc3";
463 reg = <0x0 0xff400000 0x0 0x100000>;
464 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
466 snps,dis_u2_susphy_quirk;
467 snps,quirk-frame-length-adjustment = <0x20>;
468 snps,parkmode-disable-ss-quirk;
472 compatible = "amlogic,meson-a1-usb", "snps,dwc2";
473 reg = <0x0 0xff500000 0x0 0x40000>;
474 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
476 phy-names = "usb2-phy";
477 clocks = <&clkc_periphs CLKID_USB_PHY>;
479 dr_mode = "peripheral";
480 g-rx-fifo-size = <192>;
481 g-np-tx-fifo-size = <128>;
482 g-tx-fifo-size = <128 128 16 16 16>;
486 gic: interrupt-controller@ff901000 {
487 compatible = "arm,gic-400";
488 reg = <0x0 0xff901000 0x0 0x1000>,
489 <0x0 0xff902000 0x0 0x2000>,
490 <0x0 0xff904000 0x0 0x2000>,
491 <0x0 0xff906000 0x0 0x2000>;
492 interrupt-controller;
493 interrupts = <GIC_PPI 9
494 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
495 #interrupt-cells = <3>;
496 #address-cells = <0>;
501 compatible = "arm,armv8-timer";
502 interrupts = <GIC_PPI 13
503 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
505 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
507 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
509 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
513 compatible = "fixed-clock";
514 clock-frequency = <24000000>;
515 clock-output-names = "xtal";