arch/arm/dts/juno-motherboard.dtsi

   1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
   2 /*
   3  * ARM Juno Platform motherboard peripherals
   4  *
   5  * Copyright (c) 2013-2014 ARM Ltd
   6  *
   7  * This file is licensed under a dual GPLv2 or BSD license.
   8  *
   9  */
  10
  11 / {
  12         mb_clk24mhz: clk24mhz {
  13                 compatible = "fixed-clock";
  14                 #clock-cells = <0>;
  15                 clock-frequency = <24000000>;
  16                 clock-output-names = "juno_mb:clk24mhz";
  17         };
  18
  19         mb_clk25mhz: clk25mhz {
  20                 compatible = "fixed-clock";
  21                 #clock-cells = <0>;
  22                 clock-frequency = <25000000>;
  23                 clock-output-names = "juno_mb:clk25mhz";
  24         };
  25
  26         v2m_refclk1mhz: refclk1mhz {
  27                 compatible = "fixed-clock";
  28                 #clock-cells = <0>;
  29                 clock-frequency = <1000000>;
  30                 clock-output-names = "juno_mb:refclk1mhz";
  31         };
  32
  33         v2m_refclk32khz: refclk32khz {
  34                 compatible = "fixed-clock";
  35                 #clock-cells = <0>;
  36                 clock-frequency = <32768>;
  37                 clock-output-names = "juno_mb:refclk32khz";
  38         };
  39
  40         mb_fixed_3v3: mcc-sb-3v3 {
  41                 compatible = "regulator-fixed";
  42                 regulator-name = "MCC_SB_3V3";
  43                 regulator-min-microvolt = <3300000>;
  44                 regulator-max-microvolt = <3300000>;
  45                 regulator-always-on;
  46         };
  47
  48         gpio-keys {
  49                 compatible = "gpio-keys";
  50
  51                 power-button {
  52                         debounce-interval = <50>;
  53                         wakeup-source;
  54                         linux,code = <116>;
  55                         label = "POWER";
  56                         gpios = <&iofpga_gpio0 0 0x4>;
  57                 };
  58                 home-button {
  59                         debounce-interval = <50>;
  60                         wakeup-source;
  61                         linux,code = <102>;
  62                         label = "HOME";
  63                         gpios = <&iofpga_gpio0 1 0x4>;
  64                 };
  65                 rlock-button {
  66                         debounce-interval = <50>;
  67                         wakeup-source;
  68                         linux,code = <152>;
  69                         label = "RLOCK";
  70                         gpios = <&iofpga_gpio0 2 0x4>;
  71                 };
  72                 vol-up-button {
  73                         debounce-interval = <50>;
  74                         wakeup-source;
  75                         linux,code = <115>;
  76                         label = "VOL+";
  77                         gpios = <&iofpga_gpio0 3 0x4>;
  78                 };
  79                 vol-down-button {
  80                         debounce-interval = <50>;
  81                         wakeup-source;
  82                         linux,code = <114>;
  83                         label = "VOL-";
  84                         gpios = <&iofpga_gpio0 4 0x4>;
  85                 };
  86                 nmi-button {
  87                         debounce-interval = <50>;
  88                         wakeup-source;
  89                         linux,code = <99>;
  90                         label = "NMI";
  91                         gpios = <&iofpga_gpio0 5 0x4>;
  92                 };
  93         };
  94
  95         bus@8000000 {
  96                 compatible = "simple-bus";
  97                 #address-cells = <2>;
  98                 #size-cells = <1>;
  99                 ranges = <0 0x8000000 0 0x8000000 0x18000000>;
 100
 101                 motherboard-bus@8000000 {
 102                         compatible = "arm,vexpress,v2p-p1", "simple-bus";
 103                         #address-cells = <2>;  /* SMB chipselect number and offset */
 104                         #size-cells = <1>;
 105                         ranges = <0 0 0 0x08000000 0x04000000>,
 106                                  <1 0 0 0x14000000 0x04000000>,
 107                                  <2 0 0 0x18000000 0x04000000>,
 108                                  <3 0 0 0x1c000000 0x04000000>,
 109                                  <4 0 0 0x0c000000 0x04000000>,
 110                                  <5 0 0 0x10000000 0x04000000>;
 111                         arm,hbi = <0x252>;
 112                         arm,vexpress,site = <0>;
 113
 114                         flash@0 {
 115                                 /* 2 * 32MiB NOR Flash memory mounted on CS0 */
 116                                 compatible = "arm,vexpress-flash", "cfi-flash";
 117                                 reg = <0 0x00000000 0x04000000>;
 118                                 bank-width = <4>;
 119                                 /*
 120                                  * Unfortunately, accessing the flash disturbs
 121                                  * the CPU idle states (suspend) and CPU
 122                                  * hotplug of the platform. For this reason,
 123                                  * flash hardware access is disabled by default.
 124                                  */
 125                                 status = "disabled";
 126                                 partitions {
 127                                         compatible = "arm,arm-firmware-suite";
 128                                 };
 129                         };
 130
 131                         ethernet@200000000 {
 132                                 compatible = "smsc,lan9118", "smsc,lan9115";
 133                                 reg = <2 0x00000000 0x10000>;
 134                                 interrupts = <3>;
 135                                 phy-mode = "mii";
 136                                 reg-io-width = <4>;
 137                                 smsc,irq-active-high;
 138                                 smsc,irq-push-pull;
 139                                 clocks = <&mb_clk25mhz>;
 140                                 vdd33a-supply = <&mb_fixed_3v3>;
 141                                 vddvario-supply = <&mb_fixed_3v3>;
 142                         };
 143
 144                         iofpga-bus@300000000 {
 145                                 compatible = "simple-bus";
 146                                 #address-cells = <1>;
 147                                 #size-cells = <1>;
 148                                 ranges = <0 3 0 0x200000>;
 149
 150                                 v2m_sysctl: sysctl@20000 {
 151                                         compatible = "arm,sp810", "arm,primecell";
 152                                         reg = <0x020000 0x1000>;
 153                                         clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&mb_clk24mhz>;
 154                                         clock-names = "refclk", "timclk", "apb_pclk";
 155                                         #clock-cells = <1>;
 156                                         clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
 157                                         assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
 158                                         assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
 159                                 };
 160
 161                                 apbregs@10000 {
 162                                         compatible = "syscon", "simple-mfd";
 163                                         reg = <0x010000 0x1000>;
 164
 165                                         led0 {
 166                                                 compatible = "register-bit-led";
 167                                                 offset = <0x08>;
 168                                                 mask = <0x01>;
 169                                                 label = "vexpress:0";
 170                                                 linux,default-trigger = "heartbeat";
 171                                                 default-state = "on";
 172                                         };
 173                                         led1 {
 174                                                 compatible = "register-bit-led";
 175                                                 offset = <0x08>;
 176                                                 mask = <0x02>;
 177                                                 label = "vexpress:1";
 178                                                 linux,default-trigger = "mmc0";
 179                                                 default-state = "off";
 180                                         };
 181                                         led2 {
 182                                                 compatible = "register-bit-led";
 183                                                 offset = <0x08>;
 184                                                 mask = <0x04>;
 185                                                 label = "vexpress:2";
 186                                                 linux,default-trigger = "cpu0";
 187                                                 default-state = "off";
 188                                         };
 189                                         led3 {
 190                                                 compatible = "register-bit-led";
 191                                                 offset = <0x08>;
 192                                                 mask = <0x08>;
 193                                                 label = "vexpress:3";
 194                                                 linux,default-trigger = "cpu1";
 195                                                 default-state = "off";
 196                                         };
 197                                         led4 {
 198                                                 compatible = "register-bit-led";
 199                                                 offset = <0x08>;
 200                                                 mask = <0x10>;
 201                                                 label = "vexpress:4";
 202                                                 linux,default-trigger = "cpu2";
 203                                                 default-state = "off";
 204                                         };
 205                                         led5 {
 206                                                 compatible = "register-bit-led";
 207                                                 offset = <0x08>;
 208                                                 mask = <0x20>;
 209                                                 label = "vexpress:5";
 210                                                 linux,default-trigger = "cpu3";
 211                                                 default-state = "off";
 212                                         };
 213                                         led6 {
 214                                                 compatible = "register-bit-led";
 215                                                 offset = <0x08>;
 216                                                 mask = <0x40>;
 217                                                 label = "vexpress:6";
 218                                                 default-state = "off";
 219                                         };
 220                                         led7 {
 221                                                 compatible = "register-bit-led";
 222                                                 offset = <0x08>;
 223                                                 mask = <0x80>;
 224                                                 label = "vexpress:7";
 225                                                 default-state = "off";
 226                                         };
 227                                 };
 228
 229                                 mmc@50000 {
 230                                         compatible = "arm,pl180", "arm,primecell";
 231                                         reg = <0x050000 0x1000>;
 232                                         interrupts = <5>;
 233                                         /* cd-gpios = <&v2m_mmc_gpios 0 0>;
 234                                         wp-gpios = <&v2m_mmc_gpios 1 0>; */
 235                                         max-frequency = <12000000>;
 236                                         vmmc-supply = <&mb_fixed_3v3>;
 237                                         clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
 238                                         clock-names = "mclk", "apb_pclk";
 239                                 };
 240
 241                                 kmi@60000 {
 242                                         compatible = "arm,pl050", "arm,primecell";
 243                                         reg = <0x060000 0x1000>;
 244                                         interrupts = <8>;
 245                                         clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
 246                                         clock-names = "KMIREFCLK", "apb_pclk";
 247                                 };
 248
 249                                 kmi@70000 {
 250                                         compatible = "arm,pl050", "arm,primecell";
 251                                         reg = <0x070000 0x1000>;
 252                                         interrupts = <8>;
 253                                         clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
 254                                         clock-names = "KMIREFCLK", "apb_pclk";
 255                                 };
 256
 257                                 watchdog@f0000 {
 258                                         compatible = "arm,sp805", "arm,primecell";
 259                                         reg = <0x0f0000 0x10000>;
 260                                         interrupts = <7>;
 261                                         clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
 262                                         clock-names = "wdog_clk", "apb_pclk";
 263                                 };
 264
 265                                 v2m_timer01: timer@110000 {
 266                                         compatible = "arm,sp804", "arm,primecell";
 267                                         reg = <0x110000 0x10000>;
 268                                         interrupts = <9>;
 269                                         clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&mb_clk24mhz>;
 270                                         clock-names = "timclken1", "timclken2", "apb_pclk";
 271                                 };
 272
 273                                 v2m_timer23: timer@120000 {
 274                                         compatible = "arm,sp804", "arm,primecell";
 275                                         reg = <0x120000 0x10000>;
 276                                         interrupts = <9>;
 277                                         clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&mb_clk24mhz>;
 278                                         clock-names = "timclken1", "timclken2", "apb_pclk";
 279                                 };
 280
 281                                 rtc@170000 {
 282                                         compatible = "arm,pl031", "arm,primecell";
 283                                         reg = <0x170000 0x10000>;
 284                                         interrupts = <0>;
 285                                         clocks = <&soc_smc50mhz>;
 286                                         clock-names = "apb_pclk";
 287                                 };
 288
 289                                 iofpga_gpio0: gpio@1d0000 {
 290                                         compatible = "arm,pl061", "arm,primecell";
 291                                         reg = <0x1d0000 0x1000>;
 292                                         interrupts = <6>;
 293                                         clocks = <&soc_smc50mhz>;
 294                                         clock-names = "apb_pclk";
 295                                         gpio-controller;
 296                                         #gpio-cells = <2>;
 297                                         interrupt-controller;
 298                                         #interrupt-cells = <2>;
 299                                 };
 300                         };
 301                 };
 302         };
 303 };