arch/arm/dts/bcm6856.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (C) 2020 Philippe Reynes <[email protected]>
   4  * Copyright 2022 Broadcom Ltd.
   5  */
   6
   7 #include <dt-bindings/interrupt-controller/irq.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9
  10 / {
  11         compatible = "brcm,bcm6856", "brcm,bcmbca";
  12         #address-cells = <2>;
  13         #size-cells = <2>;
  14
  15         interrupt-parent = <&gic>;
  16
  17         cpus {
  18                 #address-cells = <2>;
  19                 #size-cells = <0>;
  20
  21                 B53_0: cpu@0 {
  22                         compatible = "brcm,brahma-b53";
  23                         device_type = "cpu";
  24                         reg = <0x0 0x0>;
  25                         next-level-cache = <&L2_0>;
  26                         enable-method = "psci";
  27                 };
  28
  29                 B53_1: cpu@1 {
  30                         compatible = "brcm,brahma-b53";
  31                         device_type = "cpu";
  32                         reg = <0x0 0x1>;
  33                         next-level-cache = <&L2_0>;
  34                         enable-method = "psci";
  35                 };
  36
  37                 L2_0: l2-cache0 {
  38                         compatible = "cache";
  39                 };
  40         };
  41
  42         timer {
  43                 compatible = "arm,armv8-timer";
  44                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  45                         <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  46                         <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  47                         <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
  48         };
  49
  50         pmu: pmu {
  51                 compatible = "arm,cortex-a53-pmu";
  52                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
  53                         <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
  54                 interrupt-affinity = <&B53_0>, <&B53_1>;
  55         };
  56
  57         clocks: clocks {
  58                 bootph-all;
  59
  60                 periph_clk:periph-clk {
  61                         compatible = "fixed-clock";
  62                         #clock-cells = <0>;
  63                         clock-frequency = <200000000>;
  64                 };
  65
  66                 hsspi_pll: hsspi-pll {
  67                         compatible = "fixed-factor-clock";
  68                         #clock-cells = <0>;
  69                         clocks = <&periph_clk>;
  70                         clock-mult = <2>;
  71                         clock-div = <1>;
  72                 };
  73
  74                 wdt_clk: wdt-clk {
  75                         compatible = "fixed-factor-clock";
  76                         #clock-cells = <0>;
  77                         clocks = <&periph_clk>;
  78                         clock-div = <4>;
  79                         clock-mult = <1>;
  80                 };
  81         };
  82
  83         psci {
  84                 compatible = "arm,psci-0.2";
  85                 method = "smc";
  86         };
  87
  88         axi@81000000 {
  89                 compatible = "simple-bus";
  90                 #address-cells = <1>;
  91                 #size-cells = <1>;
  92                 ranges = <0x0 0x0 0x81000000 0x8000>;
  93
  94                 gic: interrupt-controller@1000 {
  95                         compatible = "arm,gic-400";
  96                         #interrupt-cells = <3>;
  97                         interrupt-controller;
  98                         reg = <0x1000 0x1000>, /* GICD */
  99                                 <0x2000 0x2000>, /* GICC */
 100                                 <0x4000 0x2000>, /* GICH */
 101                                 <0x6000 0x2000>; /* GICV */
 102                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
 103                                         IRQ_TYPE_LEVEL_HIGH)>;
 104                 };
 105         };
 106
 107         bus@ff800000 {
 108                 compatible = "simple-bus";
 109                 #address-cells = <1>;
 110                 #size-cells = <1>;
 111                 ranges = <0x0 0x0 0xff800000 0x800000>;
 112                 bootph-all;
 113
 114                 uart0: serial@640 {
 115                         compatible = "brcm,bcm6345-uart";
 116                         reg = <0x640 0x18>;
 117                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 118                         clocks = <&periph_clk>;
 119                         clock-names = "refclk";
 120                         status = "disabled";
 121                 };
 122
 123                 wdt1: watchdog@480 {
 124                         compatible = "brcm,bcm6345-wdt";
 125                         reg = <0x480 0x14>;
 126                         clocks = <&wdt_clk>;
 127                 };
 128
 129                 wdt2: watchdog@4c0 {
 130                         compatible = "brcm,bcm6345-wdt";
 131                         reg = <0x4c0 0x14>;
 132                         clocks = <&wdt_clk>;
 133                 };
 134
 135                 wdt-reboot {
 136                         compatible = "wdt-reboot";
 137                         wdt = <&wdt1>;
 138                 };
 139
 140                 leds: led-controller@800 {
 141                         compatible = "brcm,bcm6858-leds";
 142                         reg = <0x800 0xe4>;
 143
 144                         status = "disabled";
 145                 };
 146
 147                 gpio0: gpio-controller@500 {
 148                         compatible = "brcm,bcm6345-gpio";
 149                         reg = <0x500 0x4>,
 150                               <0x520 0x4>;
 151                         gpio-controller;
 152                         #gpio-cells = <2>;
 153
 154                         status = "disabled";
 155                 };
 156
 157                 gpio1: gpio-controller@504 {
 158                         compatible = "brcm,bcm6345-gpio";
 159                         reg = <0x504 0x4>,
 160                               <0x524 0x4>;
 161                         gpio-controller;
 162                         #gpio-cells = <2>;
 163
 164                         status = "disabled";
 165                 };
 166
 167                 gpio2: gpio-controller@508 {
 168                         compatible = "brcm,bcm6345-gpio";
 169                         reg = <0x508 0x4>,
 170                               <0x528 0x4>;
 171                         gpio-controller;
 172                         #gpio-cells = <2>;
 173
 174                         status = "disabled";
 175                 };
 176
 177                 gpio3: gpio-controller@50c {
 178                         compatible = "brcm,bcm6345-gpio";
 179                         reg = <0x50c 0x4>,
 180                               <0x52c 0x4>;
 181                         gpio-controller;
 182                         #gpio-cells = <2>;
 183
 184                         status = "disabled";
 185                 };
 186
 187                 gpio4: gpio-controller@510 {
 188                         compatible = "brcm,bcm6345-gpio";
 189                         reg = <0x510 0x4>,
 190                               <0x530 0x4>;
 191                         gpio-controller;
 192                         #gpio-cells = <2>;
 193
 194                         status = "disabled";
 195                 };
 196
 197                 gpio5: gpio-controller@514 {
 198                         compatible = "brcm,bcm6345-gpio";
 199                         reg = <0x514 0x4>,
 200                               <0x534 0x4>;
 201                         gpio-controller;
 202                         #gpio-cells = <2>;
 203
 204                         status = "disabled";
 205                 };
 206
 207                 gpio6: gpio-controller@518 {
 208                         compatible = "brcm,bcm6345-gpio";
 209                         reg = <0x518 0x4>,
 210                               <0x538 0x4>;
 211                         gpio-controller;
 212                         #gpio-cells = <2>;
 213
 214                         status = "disabled";
 215                 };
 216
 217                 gpio7: gpio-controller@51c {
 218                         compatible = "brcm,bcm6345-gpio";
 219                         reg = <0x51c 0x4>,
 220                               <0x53c 0x4>;
 221                         gpio-controller;
 222                         #gpio-cells = <2>;
 223
 224                         status = "disabled";
 225                 };
 226
 227                 hsspi: spi-controller@1000 {
 228                         compatible = "brcm,bcm6328-hsspi";
 229                         #address-cells = <1>;
 230                         #size-cells = <0>;
 231                         reg = <0x1000 0x600>;
 232                         clocks = <&hsspi_pll>, <&hsspi_pll>;
 233                         clock-names = "hsspi", "pll";
 234                         spi-max-frequency = <100000000>;
 235                         num-cs = <8>;
 236
 237                         status = "disabled";
 238                 };
 239
 240                 nand: nand-controller@1800 {
 241                         compatible = "brcm,nand-bcm68360",
 242                                      "brcm,brcmnand-v5.0",
 243                                      "brcm,brcmnand";
 244                         reg-names = "nand", "nand-int-base", "nand-cache";
 245                         reg = <0x1800 0x180>,
 246                               <0x2000 0x10>,
 247                               <0x1c00 0x200>;
 248                         parameter-page-big-endian = <0>;
 249
 250                         status = "disabled";
 251                 };
 252         };
 253 };