arch/arm/dts/bcm6855.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (C) 2022 Philippe Reynes <[email protected]>
   4  * Copyright 2022 Broadcom Ltd.
   5  */
   6
   7 #include <dt-bindings/interrupt-controller/arm-gic.h>
   8 #include <dt-bindings/interrupt-controller/irq.h>
   9
  10 / {
  11         compatible = "brcm,bcm6855", "brcm,bcmbca";
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14
  15         interrupt-parent = <&gic>;
  16
  17         cpus {
  18                 #address-cells = <1>;
  19                 #size-cells = <0>;
  20
  21                 CA7_0: cpu@0 {
  22                         device_type = "cpu";
  23                         compatible = "arm,cortex-a7";
  24                         reg = <0x0>;
  25                         next-level-cache = <&L2_0>;
  26                         enable-method = "psci";
  27                 };
  28
  29                 CA7_1: cpu@1 {
  30                         device_type = "cpu";
  31                         compatible = "arm,cortex-a7";
  32                         reg = <0x1>;
  33                         next-level-cache = <&L2_0>;
  34                         enable-method = "psci";
  35                 };
  36
  37                 CA7_2: cpu@2 {
  38                         device_type = "cpu";
  39                         compatible = "arm,cortex-a7";
  40                         reg = <0x2>;
  41                         next-level-cache = <&L2_0>;
  42                         enable-method = "psci";
  43                 };
  44
  45                 L2_0: l2-cache0 {
  46                         compatible = "cache";
  47                 };
  48         };
  49
  50         timer {
  51                 compatible = "arm,armv7-timer";
  52                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
  53                         <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
  54                         <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
  55                         <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>;
  56                 arm,cpu-registers-not-fw-configured;
  57         };
  58
  59         pmu: pmu {
  60                 compatible = "arm,cortex-a7-pmu";
  61                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
  62                         <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
  63                         <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
  64                 interrupt-affinity = <&CA7_0>, <&CA7_1>, <&CA7_2>;
  65         };
  66
  67         clocks: clocks {
  68                 bootph-all;
  69
  70                 periph_clk: periph-clk {
  71                         compatible = "fixed-clock";
  72                         #clock-cells = <0>;
  73                         clock-frequency = <200000000>;
  74                 };
  75
  76                 uart_clk: uart-clk {
  77                         compatible = "fixed-factor-clock";
  78                         #clock-cells = <0>;
  79                         clocks = <&periph_clk>;
  80                         clock-div = <4>;
  81                         clock-mult = <1>;
  82                 };
  83
  84                 hsspi_pll: hsspi-pll {
  85                         compatible = "fixed-factor-clock";
  86                         #clock-cells = <0>;
  87                         clocks = <&periph_clk>;
  88                         clock-mult = <2>;
  89                         clock-div = <1>;
  90                 };
  91
  92                 wdt_clk: wdt-clk {
  93                         compatible = "fixed-factor-clock";
  94                         #clock-cells = <0>;
  95                         clocks = <&periph_clk>;
  96                         clock-div = <4>;
  97                         clock-mult = <1>;
  98                 };
  99         };
 100
 101         psci {
 102                 compatible = "arm,psci-0.2";
 103                 method = "smc";
 104         };
 105
 106         axi@81000000 {
 107                 compatible = "simple-bus";
 108                 #address-cells = <1>;
 109                 #size-cells = <1>;
 110                 ranges = <0 0x81000000 0x8000>;
 111
 112                 gic: interrupt-controller@1000 {
 113                         compatible = "arm,cortex-a7-gic";
 114                         #interrupt-cells = <3>;
 115                         interrupt-controller;
 116                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_HIGH)>;
 117                         reg = <0x1000 0x1000>,
 118                                 <0x2000 0x2000>,
 119                                 <0x4000 0x2000>,
 120                                 <0x6000 0x2000>;
 121                 };
 122         };
 123
 124         bus@ff800000 {
 125                 compatible = "simple-bus";
 126                 #address-cells = <1>;
 127                 #size-cells = <1>;
 128                 ranges = <0 0xff800000 0x800000>;
 129                 bootph-all;
 130
 131                 uart0: serial@12000 {
 132                         compatible = "arm,pl011", "arm,primecell";
 133                         reg = <0x12000 0x1000>;
 134                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 135                         clocks = <&uart_clk>, <&uart_clk>;
 136                         clock-names = "uartclk", "apb_pclk";
 137                         status = "disabled";
 138                 };
 139
 140                 wdt1: watchdog@480 {
 141                         compatible = "brcm,bcm6345-wdt";
 142                         reg = <0x480 0x14>;
 143                         clocks = <&wdt_clk>;
 144                 };
 145
 146                 wdt2: watchdog@4c0 {
 147                         compatible = "brcm,bcm6345-wdt";
 148                         reg = <0x4c0 0x14>;
 149                         clocks = <&wdt_clk>;
 150                 };
 151
 152                 wdt-reboot {
 153                         compatible = "wdt-reboot";
 154                         wdt = <&wdt1>;
 155                 };
 156
 157                 gpio0: gpio-controller@500 {
 158                         compatible = "brcm,bcm6345-gpio";
 159                         reg = <0x500 0x4>,
 160                               <0x520 0x4>;
 161                         gpio-controller;
 162                         #gpio-cells = <2>;
 163
 164                         status = "disabled";
 165                 };
 166
 167                 gpio1: gpio-controller@504 {
 168                         compatible = "brcm,bcm6345-gpio";
 169                         reg = <0x504 0x4>,
 170                               <0x524 0x4>;
 171                         gpio-controller;
 172                         #gpio-cells = <2>;
 173
 174                         status = "disabled";
 175                 };
 176
 177                 gpio2: gpio-controller@508 {
 178                         compatible = "brcm,bcm6345-gpio";
 179                         reg = <0x508 0x4>,
 180                               <0x528 0x4>;
 181                         gpio-controller;
 182                         #gpio-cells = <2>;
 183
 184                         status = "disabled";
 185                 };
 186
 187                 gpio3: gpio-controller@50c {
 188                         compatible = "brcm,bcm6345-gpio";
 189                         reg = <0x50c 0x4>,
 190                               <0x52c 0x4>;
 191                         gpio-controller;
 192                         #gpio-cells = <2>;
 193
 194                         status = "disabled";
 195                 };
 196
 197                 gpio4: gpio-controller@510 {
 198                         compatible = "brcm,bcm6345-gpio";
 199                         reg = <0x510 0x4>,
 200                               <0x530 0x4>;
 201                         gpio-controller;
 202                         #gpio-cells = <2>;
 203
 204                         status = "disabled";
 205                 };
 206
 207                 gpio5: gpio-controller@514 {
 208                         compatible = "brcm,bcm6345-gpio";
 209                         reg = <0x514 0x4>,
 210                               <0x534 0x4>;
 211                         gpio-controller;
 212                         #gpio-cells = <2>;
 213
 214                         status = "disabled";
 215                 };
 216
 217                 gpio6: gpio-controller@518 {
 218                         compatible = "brcm,bcm6345-gpio";
 219                         reg = <0x518 0x4>,
 220                               <0x538 0x4>;
 221                         gpio-controller;
 222                         #gpio-cells = <2>;
 223
 224                         status = "disabled";
 225                 };
 226
 227                 gpio7: gpio-controller@51c {
 228                         compatible = "brcm,bcm6345-gpio";
 229                         reg = <0x51c 0x4>,
 230                               <0x53c 0x4>;
 231                         gpio-controller;
 232                         #gpio-cells = <2>;
 233
 234                         status = "disabled";
 235                 };
 236
 237                 nand: nand-controller@1800 {
 238                         compatible = "brcm,nand-bcm6753",
 239                                      "brcm,brcmnand-v5.0",
 240                                      "brcm,brcmnand";
 241                         reg-names = "nand", "nand-int-base", "nand-cache";
 242                         reg = <0x1800 0x180>,
 243                               <0x2000 0x10>,
 244                               <0x1c00 0x200>;
 245                         parameter-page-big-endian = <0>;
 246
 247                         status = "disabled";
 248                 };
 249
 250                 leds: led-controller@3000 {
 251                         compatible = "brcm,bcm6753-leds";
 252                         reg = <0x3000 0x3480>;
 253
 254                         status = "disabled";
 255                 };
 256         };
 257 };