drivers/mtd/nand/raw/atmel/nand-controller.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright 2022 ATMEL
   4  * Copyright 2017 Free Electrons
   5  *
   6  * Author: Boris Brezillon <[email protected]>
   7  *
   8  * Derived from the atmel_nand.c driver which contained the following
   9  * copyrights:
  10  *
  11  *   Copyright 2003 Rick Bronson
  12  *
  13  *   Derived from drivers/mtd/nand/autcpu12.c (removed in v3.8)
  14  *      Copyright 2001 Thomas Gleixner ([email protected])
  15  *
  16  *   Derived from drivers/mtd/spia.c (removed in v3.8)
  17  *      Copyright 2000 Steven J. Hill ([email protected])
  18  *
  19  *
  20  *   Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
  21  *      Richard Genoud ([email protected]), Adeneo Copyright 2007
  22  *
  23  *   Derived from Das U-Boot source code
  24  *      (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
  25  *      Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
  26  *
  27  *   Add Programmable Multibit ECC support for various AT91 SoC
  28  *      Copyright 2012 ATMEL, Hong Xu
  29  *
  30  *   Add Nand Flash Controller support for SAMA5 SoC
  31  *      Copyright 2013 ATMEL, Josh Wu ([email protected])
  32  *
  33  *   Port from Linux
  34  *      Balamanikandan Gunasundar([email protected])
  35  *      Copyright (C) 2022 Microchip Technology Inc.
  36  *
  37  * A few words about the naming convention in this file. This convention
  38  * applies to structure and function names.
  39  *
  40  * Prefixes:
  41  *
  42  * - atmel_nand_: all generic structures/functions
  43  * - atmel_smc_nand_: all structures/functions specific to the SMC interface
  44  *                    (at91sam9 and avr32 SoCs)
  45  * - atmel_hsmc_nand_: all structures/functions specific to the HSMC interface
  46  *                     (sama5 SoCs and later)
  47  * - atmel_nfc_: all structures/functions used to manipulate the NFC sub-block
  48  *               that is available in the HSMC block
  49  * - <soc>_nand_: all SoC specific structures/functions
  50  */
  51
  52 #include <asm-generic/gpio.h>
  53 #include <clk.h>
  54 #include <dm/device_compat.h>
  55 #include <dm/devres.h>
  56 #include <dm/of_addr.h>
  57 #include <dm/of_access.h>
  58 #include <dm/uclass.h>
  59 #include <linux/completion.h>
  60 #include <linux/io.h>
  61 #include <linux/iopoll.h>
  62 #include <linux/ioport.h>
  63 #include <linux/mfd/syscon/atmel-matrix.h>
  64 #include <linux/mfd/syscon/atmel-smc.h>
  65 #include <linux/mtd/rawnand.h>
  66 #include <linux/mtd/mtd.h>
  67 #include <linux/time.h>
  68 #include <mach/at91_sfr.h>
  69 #include <nand.h>
  70 #include <regmap.h>
  71 #include <syscon.h>
  72
  73 #include "pmecc.h"
  74
  75 #define ATMEL_HSMC_NFC_CFG                      0x0
  76 #define ATMEL_HSMC_NFC_CFG_SPARESIZE(x)         (((x) / 4) << 24)
  77 #define ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK       GENMASK(30, 24)
  78 #define ATMEL_HSMC_NFC_CFG_DTO(cyc, mul)        (((cyc) << 16) | ((mul) << 20))
  79 #define ATMEL_HSMC_NFC_CFG_DTO_MAX              GENMASK(22, 16)
  80 #define ATMEL_HSMC_NFC_CFG_RBEDGE               BIT(13)
  81 #define ATMEL_HSMC_NFC_CFG_FALLING_EDGE         BIT(12)
  82 #define ATMEL_HSMC_NFC_CFG_RSPARE               BIT(9)
  83 #define ATMEL_HSMC_NFC_CFG_WSPARE               BIT(8)
  84 #define ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK        GENMASK(2, 0)
  85 #define ATMEL_HSMC_NFC_CFG_PAGESIZE(x)          (fls((x) / 512) - 1)
  86
  87 #define ATMEL_HSMC_NFC_CTRL                     0x4
  88 #define ATMEL_HSMC_NFC_CTRL_EN                  BIT(0)
  89 #define ATMEL_HSMC_NFC_CTRL_DIS                 BIT(1)
  90
  91 #define ATMEL_HSMC_NFC_SR                       0x8
  92 #define ATMEL_HSMC_NFC_IER                      0xc
  93 #define ATMEL_HSMC_NFC_IDR                      0x10
  94 #define ATMEL_HSMC_NFC_IMR                      0x14
  95 #define ATMEL_HSMC_NFC_SR_ENABLED               BIT(1)
  96 #define ATMEL_HSMC_NFC_SR_RB_RISE               BIT(4)
  97 #define ATMEL_HSMC_NFC_SR_RB_FALL               BIT(5)
  98 #define ATMEL_HSMC_NFC_SR_BUSY                  BIT(8)
  99 #define ATMEL_HSMC_NFC_SR_WR                    BIT(11)
 100 #define ATMEL_HSMC_NFC_SR_CSID                  GENMASK(14, 12)
 101 #define ATMEL_HSMC_NFC_SR_XFRDONE               BIT(16)
 102 #define ATMEL_HSMC_NFC_SR_CMDDONE               BIT(17)
 103 #define ATMEL_HSMC_NFC_SR_DTOE                  BIT(20)
 104 #define ATMEL_HSMC_NFC_SR_UNDEF                 BIT(21)
 105 #define ATMEL_HSMC_NFC_SR_AWB                   BIT(22)
 106 #define ATMEL_HSMC_NFC_SR_NFCASE                BIT(23)
 107 #define ATMEL_HSMC_NFC_SR_ERRORS                (ATMEL_HSMC_NFC_SR_DTOE | \
 108                                                  ATMEL_HSMC_NFC_SR_UNDEF | \
 109                                                  ATMEL_HSMC_NFC_SR_AWB | \
 110                                                  ATMEL_HSMC_NFC_SR_NFCASE)
 111 #define ATMEL_HSMC_NFC_SR_RBEDGE(x)             BIT((x) + 24)
 112
 113 #define ATMEL_HSMC_NFC_ADDR                     0x18
 114 #define ATMEL_HSMC_NFC_BANK                     0x1c
 115
 116 #define ATMEL_NFC_MAX_RB_ID                     7
 117
 118 #define ATMEL_NFC_SRAM_SIZE                     0x2400
 119
 120 #define ATMEL_NFC_CMD(pos, cmd)                 ((cmd) << (((pos) * 8) + 2))
 121 #define ATMEL_NFC_VCMD2                         BIT(18)
 122 #define ATMEL_NFC_ACYCLE(naddrs)                ((naddrs) << 19)
 123 #define ATMEL_NFC_CSID(cs)                      ((cs) << 22)
 124 #define ATMEL_NFC_DATAEN                        BIT(25)
 125 #define ATMEL_NFC_NFCWR                         BIT(26)
 126
 127 #define ATMEL_NFC_MAX_ADDR_CYCLES               5
 128
 129 #define ATMEL_NAND_ALE_OFFSET                   BIT(21)
 130 #define ATMEL_NAND_CLE_OFFSET                   BIT(22)
 131
 132 #define DEFAULT_TIMEOUT_MS                      1000
 133 #define MIN_DMA_LEN                             128
 134
 135 static struct nand_ecclayout atmel_pmecc_oobinfo;
 136
 137 struct nand_controller_ops {
 138         int (*attach_chip)(struct nand_chip *chip);
 139         int (*setup_data_interface)(struct mtd_info *mtd, int chipnr,
 140                                     const struct nand_data_interface *conf);
 141 };
 142
 143 struct nand_controller {
 144         const struct nand_controller_ops *ops;
 145 };
 146
 147 enum atmel_nand_rb_type {
 148         ATMEL_NAND_NO_RB,
 149         ATMEL_NAND_NATIVE_RB,
 150         ATMEL_NAND_GPIO_RB,
 151 };
 152
 153 struct atmel_nand_rb {
 154         enum atmel_nand_rb_type type;
 155         union {
 156                 struct gpio_desc gpio;
 157                 int id;
 158         };
 159 };
 160
 161 struct atmel_nand_cs {
 162         int id;
 163         struct atmel_nand_rb rb;
 164         struct gpio_desc csgpio;
 165         struct {
 166                 void __iomem *virt;
 167                 dma_addr_t dma;
 168         } io;
 169
 170         struct atmel_smc_cs_conf smcconf;
 171 };
 172
 173 struct atmel_nand {
 174         struct list_head node;
 175         struct udevice *dev;
 176         struct nand_chip base;
 177         struct atmel_nand_cs *activecs;
 178         struct atmel_pmecc_user *pmecc;
 179         struct gpio_desc cdgpio;
 180         int numcs;
 181         struct nand_controller *controller;
 182         struct atmel_nand_cs cs[];
 183 };
 184
 185 static inline struct atmel_nand *to_atmel_nand(struct nand_chip *chip)
 186 {
 187         return container_of(chip, struct atmel_nand, base);
 188 }
 189
 190 enum atmel_nfc_data_xfer {
 191         ATMEL_NFC_NO_DATA,
 192         ATMEL_NFC_READ_DATA,
 193         ATMEL_NFC_WRITE_DATA,
 194 };
 195
 196 struct atmel_nfc_op {
 197         u8 cs;
 198         u8 ncmds;
 199         u8 cmds[2];
 200         u8 naddrs;
 201         u8 addrs[5];
 202         enum atmel_nfc_data_xfer data;
 203         u32 wait;
 204         u32 errors;
 205 };
 206
 207 struct atmel_nand_controller;
 208 struct atmel_nand_controller_caps;
 209
 210 struct atmel_nand_controller_ops {
 211         int (*probe)(struct udevice *udev,
 212                      const struct atmel_nand_controller_caps *caps);
 213         int (*remove)(struct atmel_nand_controller *nc);
 214         void (*nand_init)(struct atmel_nand_controller *nc,
 215                           struct atmel_nand *nand);
 216         int (*ecc_init)(struct nand_chip *chip);
 217         int (*setup_data_interface)(struct atmel_nand *nand, int csline,
 218                                     const struct nand_data_interface *conf);
 219 };
 220
 221 struct atmel_nand_controller_caps {
 222         bool has_dma;
 223         bool legacy_of_bindings;
 224         u32 ale_offs;
 225         u32 cle_offs;
 226         const char *ebi_csa_regmap_name;
 227         const struct atmel_nand_controller_ops *ops;
 228 };
 229
 230 struct atmel_nand_controller {
 231         struct nand_controller base;
 232         const struct atmel_nand_controller_caps *caps;
 233         struct udevice *dev;
 234         struct regmap *smc;
 235         struct dma_chan *dmac;
 236         struct atmel_pmecc *pmecc;
 237         struct list_head chips;
 238         struct clk *mck;
 239 };
 240
 241 static inline struct atmel_nand_controller *
 242 to_nand_controller(struct nand_controller *ctl)
 243 {
 244         return container_of(ctl, struct atmel_nand_controller, base);
 245 }
 246
 247 struct atmel_smc_nand_ebi_csa_cfg {
 248         u32 offs;
 249         u32 nfd0_on_d16;
 250 };
 251
 252 struct atmel_smc_nand_controller {
 253         struct atmel_nand_controller base;
 254         struct regmap *ebi_csa_regmap;
 255         struct atmel_smc_nand_ebi_csa_cfg *ebi_csa;
 256 };
 257
 258 static inline struct atmel_smc_nand_controller *
 259 to_smc_nand_controller(struct nand_controller *ctl)
 260 {
 261         return container_of(to_nand_controller(ctl),
 262                             struct atmel_smc_nand_controller, base);
 263 }
 264
 265 struct atmel_hsmc_nand_controller {
 266         struct atmel_nand_controller base;
 267         struct {
 268                 struct gen_pool *pool;
 269                 void __iomem *virt;
 270                 dma_addr_t dma;
 271         } sram;
 272         const struct atmel_hsmc_reg_layout *hsmc_layout;
 273         struct regmap *io;
 274         struct atmel_nfc_op op;
 275         struct completion complete;
 276         int irq;
 277
 278         /* Only used when instantiating from legacy DT bindings. */
 279         struct clk *clk;
 280 };
 281
 282 static inline struct atmel_hsmc_nand_controller *
 283 to_hsmc_nand_controller(struct nand_controller *ctl)
 284 {
 285         return container_of(to_nand_controller(ctl),
 286                             struct atmel_hsmc_nand_controller, base);
 287 }
 288
 289 static void pmecc_config_ecc_layout(struct nand_ecclayout *layout,
 290                                     int oobsize, int ecc_len)
 291 {
 292         int i;
 293
 294         layout->eccbytes = ecc_len;
 295
 296         /* ECC will occupy the last ecc_len bytes continuously */
 297         for (i = 0; i < ecc_len; i++)
 298                 layout->eccpos[i] = oobsize - ecc_len + i;
 299
 300         layout->oobfree[0].offset = 2;
 301         layout->oobfree[0].length =
 302                 oobsize - ecc_len - layout->oobfree[0].offset;
 303 }
 304
 305 static bool atmel_nfc_op_done(struct atmel_nfc_op *op, u32 status)
 306 {
 307         op->errors |= status & ATMEL_HSMC_NFC_SR_ERRORS;
 308         op->wait ^= status & op->wait;
 309
 310         return !op->wait || op->errors;
 311 }
 312
 313 static int atmel_nfc_wait(struct atmel_hsmc_nand_controller *nc, bool poll,
 314                           unsigned int timeout_ms)
 315 {
 316         int ret;
 317         u32 status;
 318
 319         if (!timeout_ms)
 320                 timeout_ms = DEFAULT_TIMEOUT_MS;
 321
 322         if (poll)
 323                 ret = regmap_read_poll_timeout(nc->base.smc,
 324                                                ATMEL_HSMC_NFC_SR, status,
 325                                                atmel_nfc_op_done(&nc->op,
 326                                                                  status),
 327                                                0, timeout_ms);
 328         else
 329                 return -EOPNOTSUPP;
 330
 331         if (nc->op.errors & ATMEL_HSMC_NFC_SR_DTOE) {
 332                 dev_err(nc->base.dev, "Waiting NAND R/B Timeout\n");
 333                 ret = -ETIMEDOUT;
 334         }
 335
 336         if (nc->op.errors & ATMEL_HSMC_NFC_SR_UNDEF) {
 337                 dev_err(nc->base.dev, "Access to an undefined area\n");
 338                 ret = -EIO;
 339         }
 340
 341         if (nc->op.errors & ATMEL_HSMC_NFC_SR_AWB) {
 342                 dev_err(nc->base.dev, "Access while busy\n");
 343                 ret = -EIO;
 344         }
 345
 346         if (nc->op.errors & ATMEL_HSMC_NFC_SR_NFCASE) {
 347                 dev_err(nc->base.dev, "Wrong access size\n");
 348                 ret = -EIO;
 349         }
 350
 351         return ret;
 352 }
 353
 354 static u8 atmel_nand_read_byte(struct mtd_info *mtd)
 355 {
 356         struct nand_chip *chip = mtd_to_nand(mtd);
 357         struct atmel_nand *nand = to_atmel_nand(chip);
 358
 359         return ioread8(nand->activecs->io.virt);
 360 }
 361
 362 static void atmel_nand_write_byte(struct mtd_info *mtd, u8 byte)
 363 {
 364         struct nand_chip *chip = mtd_to_nand(mtd);
 365         struct atmel_nand *nand = to_atmel_nand(chip);
 366
 367         if (chip->options & NAND_BUSWIDTH_16)
 368                 iowrite16(byte | (byte << 8), nand->activecs->io.virt);
 369         else
 370                 iowrite8(byte, nand->activecs->io.virt);
 371 }
 372
 373 static void atmel_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 374 {
 375         struct nand_chip *chip = mtd_to_nand(mtd);
 376         struct atmel_nand *nand = to_atmel_nand(chip);
 377
 378         if (chip->options & NAND_BUSWIDTH_16)
 379                 ioread16_rep(nand->activecs->io.virt, buf, len / 2);
 380         else
 381                 ioread8_rep(nand->activecs->io.virt, buf, len);
 382 }
 383
 384 static void atmel_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 385 {
 386         struct nand_chip *chip = mtd_to_nand(mtd);
 387         struct atmel_nand *nand = to_atmel_nand(chip);
 388
 389         if (chip->options & NAND_BUSWIDTH_16)
 390                 iowrite16_rep(nand->activecs->io.virt, buf, len / 2);
 391         else
 392                 iowrite8_rep(nand->activecs->io.virt, buf, len);
 393 }
 394
 395 static int atmel_nand_dev_ready(struct mtd_info *mtd)
 396 {
 397         struct nand_chip  *chip = mtd_to_nand(mtd);
 398         struct atmel_nand *nand = to_atmel_nand(chip);
 399
 400         return dm_gpio_get_value(&nand->activecs->rb.gpio);
 401 }
 402
 403 static void atmel_nand_select_chip(struct mtd_info *mtd, int cs)
 404 {
 405         struct nand_chip *chip =  mtd_to_nand(mtd);
 406         struct atmel_nand *nand = to_atmel_nand(chip);
 407
 408         if (cs < 0 || cs >= nand->numcs) {
 409                 nand->activecs = NULL;
 410                 chip->dev_ready = NULL;
 411                 return;
 412         }
 413
 414         nand->activecs = &nand->cs[cs];
 415
 416         if (nand->activecs->rb.type == ATMEL_NAND_GPIO_RB)
 417                 chip->dev_ready = atmel_nand_dev_ready;
 418 }
 419
 420 static int atmel_hsmc_nand_dev_ready(struct mtd_info *mtd)
 421 {
 422         struct nand_chip *chip = mtd_to_nand(mtd);
 423         struct atmel_nand *nand = to_atmel_nand(chip);
 424         struct atmel_hsmc_nand_controller *nc;
 425         u32 status;
 426
 427         nc = to_hsmc_nand_controller(nand->controller);
 428
 429         regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &status);
 430
 431         return status & ATMEL_HSMC_NFC_SR_RBEDGE(nand->activecs->rb.id);
 432 }
 433
 434 static void atmel_hsmc_nand_select_chip(struct mtd_info *mtd, int cs)
 435 {
 436         struct nand_chip *chip = mtd_to_nand(mtd);
 437         struct atmel_nand *nand = to_atmel_nand(chip);
 438         struct atmel_hsmc_nand_controller *nc;
 439
 440         nc = to_hsmc_nand_controller(nand->controller);
 441
 442         atmel_nand_select_chip(mtd, cs);
 443
 444         if (!nand->activecs) {
 445                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL,
 446                              ATMEL_HSMC_NFC_CTRL_DIS);
 447                 return;
 448         }
 449
 450         if (nand->activecs->rb.type == ATMEL_NAND_NATIVE_RB)
 451                 chip->dev_ready = atmel_hsmc_nand_dev_ready;
 452
 453         regmap_update_bits(nc->base.smc, ATMEL_HSMC_NFC_CFG,
 454                            ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK |
 455                            ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK |
 456                            ATMEL_HSMC_NFC_CFG_RSPARE |
 457                            ATMEL_HSMC_NFC_CFG_WSPARE,
 458                            ATMEL_HSMC_NFC_CFG_PAGESIZE(mtd->writesize) |
 459                            ATMEL_HSMC_NFC_CFG_SPARESIZE(mtd->oobsize) |
 460                            ATMEL_HSMC_NFC_CFG_RSPARE);
 461         regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL,
 462                      ATMEL_HSMC_NFC_CTRL_EN);
 463 }
 464
 465 static int atmel_nfc_exec_op(struct atmel_hsmc_nand_controller *nc, bool poll)
 466 {
 467         u8 *addrs = nc->op.addrs;
 468         unsigned int op = 0;
 469         u32 addr, val;
 470         int i, ret;
 471
 472         nc->op.wait = ATMEL_HSMC_NFC_SR_CMDDONE;
 473
 474         for (i = 0; i < nc->op.ncmds; i++)
 475                 op |= ATMEL_NFC_CMD(i, nc->op.cmds[i]);
 476
 477         if (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES)
 478                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_ADDR, *addrs++);
 479
 480         op |= ATMEL_NFC_CSID(nc->op.cs) |
 481               ATMEL_NFC_ACYCLE(nc->op.naddrs);
 482
 483         if (nc->op.ncmds > 1)
 484                 op |= ATMEL_NFC_VCMD2;
 485
 486         addr = addrs[0] | (addrs[1] << 8) | (addrs[2] << 16) |
 487                (addrs[3] << 24);
 488
 489         if (nc->op.data != ATMEL_NFC_NO_DATA) {
 490                 op |= ATMEL_NFC_DATAEN;
 491                 nc->op.wait |= ATMEL_HSMC_NFC_SR_XFRDONE;
 492
 493                 if (nc->op.data == ATMEL_NFC_WRITE_DATA)
 494                         op |= ATMEL_NFC_NFCWR;
 495         }
 496
 497         /* Clear all flags. */
 498         regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &val);
 499
 500         /* Send the command. */
 501         regmap_write(nc->io, op, addr);
 502
 503         ret = atmel_nfc_wait(nc, poll, 0);
 504         if (ret)
 505                 dev_err(nc->base.dev,
 506                         "Failed to send NAND command (err = %d)!",
 507                         ret);
 508
 509         /* Reset the op state. */
 510         memset(&nc->op, 0, sizeof(nc->op));
 511
 512         return ret;
 513 }
 514
 515 static void atmel_hsmc_nand_cmd_ctrl(struct mtd_info *mtd, int dat,
 516                                      unsigned int ctrl)
 517 {
 518         struct nand_chip *chip = mtd_to_nand(mtd);
 519         struct atmel_nand *nand = to_atmel_nand(chip);
 520         struct atmel_hsmc_nand_controller *nc;
 521
 522         nc = to_hsmc_nand_controller(nand->controller);
 523
 524         if (ctrl & NAND_ALE) {
 525                 if (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES)
 526                         return;
 527
 528                 nc->op.addrs[nc->op.naddrs++] = dat;
 529         } else if (ctrl & NAND_CLE) {
 530                 if (nc->op.ncmds > 1)
 531                         return;
 532
 533                 nc->op.cmds[nc->op.ncmds++] = dat;
 534         }
 535
 536         if (dat == NAND_CMD_NONE) {
 537                 nc->op.cs = nand->activecs->id;
 538                 atmel_nfc_exec_op(nc, true);
 539         }
 540 }
 541
 542 static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
 543                                 unsigned int ctrl)
 544 {
 545         struct nand_chip *chip = mtd_to_nand(mtd);
 546         struct atmel_nand *nand = to_atmel_nand(chip);
 547         struct atmel_nand_controller *nc;
 548
 549         nc = to_nand_controller(nand->controller);
 550
 551         if ((ctrl & NAND_CTRL_CHANGE) &&
 552             dm_gpio_is_valid(&nand->activecs->csgpio)) {
 553                 if (ctrl & NAND_NCE)
 554                         dm_gpio_set_value(&nand->activecs->csgpio, 0);
 555                 else
 556                         dm_gpio_set_value(&nand->activecs->csgpio, 1);
 557         }
 558
 559         if (ctrl & NAND_ALE)
 560                 writeb(cmd, nand->activecs->io.virt + nc->caps->ale_offs);
 561         else if (ctrl & NAND_CLE)
 562                 writeb(cmd, nand->activecs->io.virt + nc->caps->cle_offs);
 563 }
 564
 565 static void atmel_nfc_copy_to_sram(struct nand_chip *chip, const u8 *buf,
 566                                    bool oob_required)
 567 {
 568         struct mtd_info *mtd = nand_to_mtd(chip);
 569         struct atmel_nand *nand = to_atmel_nand(chip);
 570         struct atmel_hsmc_nand_controller *nc;
 571         int ret = -EIO;
 572
 573         nc = to_hsmc_nand_controller(nand->controller);
 574
 575         if (ret)
 576                 memcpy_toio(nc->sram.virt, buf, mtd->writesize);
 577
 578         if (oob_required)
 579                 memcpy_toio(nc->sram.virt + mtd->writesize, chip->oob_poi,
 580                             mtd->oobsize);
 581 }
 582
 583 static void atmel_nfc_copy_from_sram(struct nand_chip *chip, u8 *buf,
 584                                      bool oob_required)
 585 {
 586         struct mtd_info *mtd = nand_to_mtd(chip);
 587         struct atmel_nand *nand = to_atmel_nand(chip);
 588         struct atmel_hsmc_nand_controller *nc;
 589         int ret = -EIO;
 590
 591         nc = to_hsmc_nand_controller(nand->controller);
 592
 593         if (ret)
 594                 memcpy_fromio(buf, nc->sram.virt, mtd->writesize);
 595
 596         if (oob_required)
 597                 memcpy_fromio(chip->oob_poi, nc->sram.virt + mtd->writesize,
 598                               mtd->oobsize);
 599 }
 600
 601 static void atmel_nfc_set_op_addr(struct nand_chip *chip, int page, int column)
 602 {
 603         struct mtd_info *mtd = nand_to_mtd(chip);
 604         struct atmel_nand *nand = to_atmel_nand(chip);
 605         struct atmel_hsmc_nand_controller *nc;
 606
 607         nc = to_hsmc_nand_controller(nand->controller);
 608
 609         if (column >= 0) {
 610                 nc->op.addrs[nc->op.naddrs++] = column;
 611
 612                 /*
 613                  * 2 address cycles for the column offset on large page NANDs.
 614                  */
 615                 if (mtd->writesize > 512)
 616                         nc->op.addrs[nc->op.naddrs++] = column >> 8;
 617         }
 618
 619         if (page >= 0) {
 620                 nc->op.addrs[nc->op.naddrs++] = page;
 621                 nc->op.addrs[nc->op.naddrs++] = page >> 8;
 622
 623                 if (chip->options & NAND_ROW_ADDR_3)
 624                         nc->op.addrs[nc->op.naddrs++] = page >> 16;
 625         }
 626 }
 627
 628 static int atmel_nand_pmecc_enable(struct nand_chip *chip, int op, bool raw)
 629 {
 630         struct atmel_nand *nand = to_atmel_nand(chip);
 631         struct atmel_nand_controller *nc;
 632         int ret;
 633
 634         nc = to_nand_controller(nand->controller);
 635
 636         if (raw)
 637                 return 0;
 638
 639         ret = atmel_pmecc_enable(nand->pmecc, op);
 640         if (ret)
 641                 dev_err(nc->dev,
 642                         "Failed to enable ECC engine (err = %d)\n", ret);
 643
 644         return ret;
 645 }
 646
 647 static void atmel_nand_pmecc_disable(struct nand_chip *chip, bool raw)
 648 {
 649         struct atmel_nand *nand = to_atmel_nand(chip);
 650
 651         if (!raw)
 652                 atmel_pmecc_disable(nand->pmecc);
 653 }
 654
 655 static int atmel_nand_pmecc_generate_eccbytes(struct nand_chip *chip, bool raw)
 656 {
 657         struct atmel_nand *nand = to_atmel_nand(chip);
 658         struct mtd_info *mtd = nand_to_mtd(chip);
 659         struct atmel_nand_controller *nc;
 660         struct mtd_oob_region oobregion;
 661         void *eccbuf;
 662         int ret, i;
 663
 664         nc = to_nand_controller(nand->controller);
 665
 666         if (raw)
 667                 return 0;
 668
 669         ret = atmel_pmecc_wait_rdy(nand->pmecc);
 670         if (ret) {
 671                 dev_err(nc->dev,
 672                         "Failed to transfer NAND page data (err = %d)\n",
 673                         ret);
 674                 return ret;
 675         }
 676
 677         mtd_ooblayout_ecc(mtd, 0, &oobregion);
 678         eccbuf = chip->oob_poi + oobregion.offset;
 679
 680         for (i = 0; i < chip->ecc.steps; i++) {
 681                 atmel_pmecc_get_generated_eccbytes(nand->pmecc, i,
 682                                                    eccbuf);
 683                 eccbuf += chip->ecc.bytes;
 684         }
 685
 686         return 0;
 687 }
 688
 689 static int atmel_nand_pmecc_correct_data(struct nand_chip *chip, void *buf,
 690                                          bool raw)
 691 {
 692         struct atmel_nand *nand = to_atmel_nand(chip);
 693         struct mtd_info *mtd = nand_to_mtd(chip);
 694         struct atmel_nand_controller *nc;
 695         struct mtd_oob_region oobregion;
 696         int ret, i, max_bitflips = 0;
 697         void *databuf, *eccbuf;
 698
 699         nc = to_nand_controller(nand->controller);
 700
 701         if (raw)
 702                 return 0;
 703
 704         ret = atmel_pmecc_wait_rdy(nand->pmecc);
 705         if (ret) {
 706                 dev_err(nc->dev,
 707                         "Failed to read NAND page data (err = %d)\n", ret);
 708                 return ret;
 709         }
 710
 711         mtd_ooblayout_ecc(mtd, 0, &oobregion);
 712         eccbuf = chip->oob_poi + oobregion.offset;
 713         databuf = buf;
 714
 715         for (i = 0; i < chip->ecc.steps; i++) {
 716                 ret = atmel_pmecc_correct_sector(nand->pmecc, i, databuf,
 717                                                  eccbuf);
 718                 if (ret < 0 && !atmel_pmecc_correct_erased_chunks(nand->pmecc))
 719                         ret = nand_check_erased_ecc_chunk(databuf,
 720                                                           chip->ecc.size,
 721                                                           eccbuf,
 722                                                           chip->ecc.bytes,
 723                                                           NULL, 0,
 724                                                           chip->ecc.strength);
 725
 726                 if (ret >= 0)
 727                         max_bitflips = max(ret, max_bitflips);
 728                 else
 729                         mtd->ecc_stats.failed++;
 730
 731                 databuf += chip->ecc.size;
 732                 eccbuf += chip->ecc.bytes;
 733         }
 734
 735         return max_bitflips;
 736 }
 737
 738 static int atmel_nand_pmecc_write_pg(struct nand_chip *chip, const u8 *buf,
 739                                      bool oob_required, int page, bool raw)
 740 {
 741         struct mtd_info *mtd = nand_to_mtd(chip);
 742         struct atmel_nand *nand = to_atmel_nand(chip);
 743         int ret;
 744
 745         nand_prog_page_begin_op(chip, page, 0, NULL, 0);
 746
 747         ret = atmel_nand_pmecc_enable(chip, NAND_ECC_WRITE, raw);
 748         if (ret)
 749                 return ret;
 750
 751         atmel_nand_write_buf(mtd, buf, mtd->writesize);
 752
 753         ret = atmel_nand_pmecc_generate_eccbytes(chip, raw);
 754         if (ret) {
 755                 atmel_pmecc_disable(nand->pmecc);
 756                 return ret;
 757         }
 758
 759         atmel_nand_pmecc_disable(chip, raw);
 760
 761         atmel_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize);
 762
 763         return nand_prog_page_end_op(chip);
 764 }
 765
 766 static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
 767                                        struct nand_chip *chip, const u8 *buf,
 768                                        int oob_required, int page)
 769 {
 770         return atmel_nand_pmecc_write_pg(chip, buf, oob_required, page, false);
 771 }
 772
 773 static int atmel_nand_pmecc_write_page_raw(struct mtd_info *mtd,
 774                                            struct nand_chip *chip,
 775                                            const u8 *buf, int oob_required,
 776                                            int page)
 777 {
 778         return atmel_nand_pmecc_write_pg(chip, buf, oob_required, page, true);
 779 }
 780
 781 static int atmel_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf,
 782                                     bool oob_required, int page, bool raw)
 783 {
 784         struct mtd_info *mtd = nand_to_mtd(chip);
 785         int ret;
 786
 787         nand_read_page_op(chip, page, 0, NULL, 0);
 788
 789         ret = atmel_nand_pmecc_enable(chip, NAND_ECC_READ, raw);
 790         if (ret)
 791                 return ret;
 792
 793         atmel_nand_read_buf(mtd, buf, mtd->writesize);
 794         atmel_nand_read_buf(mtd, chip->oob_poi, mtd->oobsize);
 795
 796         ret = atmel_nand_pmecc_correct_data(chip, buf, raw);
 797
 798         atmel_nand_pmecc_disable(chip, raw);
 799
 800         return ret;
 801 }
 802
 803 static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
 804                                       struct nand_chip *chip, u8 *buf,
 805                                       int oob_required, int page)
 806 {
 807         return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, false);
 808 }
 809
 810 static int atmel_nand_pmecc_read_page_raw(struct mtd_info *mtd,
 811                                           struct nand_chip *chip, u8 *buf,
 812                                           int oob_required, int page)
 813 {
 814         return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, true);
 815 }
 816
 817 static int atmel_hsmc_nand_pmecc_write_pg(struct nand_chip *chip,
 818                                           const u8 *buf, bool oob_required,
 819                                           int page, bool raw)
 820 {
 821         struct mtd_info *mtd = nand_to_mtd(chip);
 822         struct atmel_nand *nand = to_atmel_nand(chip);
 823         struct atmel_hsmc_nand_controller *nc;
 824         int ret, status;
 825
 826         nc = to_hsmc_nand_controller(nand->controller);
 827
 828         atmel_nfc_copy_to_sram(chip, buf, false);
 829
 830         nc->op.cmds[0] = NAND_CMD_SEQIN;
 831         nc->op.ncmds = 1;
 832         atmel_nfc_set_op_addr(chip, page, 0x0);
 833         nc->op.cs = nand->activecs->id;
 834         nc->op.data = ATMEL_NFC_WRITE_DATA;
 835
 836         ret = atmel_nand_pmecc_enable(chip, NAND_ECC_WRITE, raw);
 837         if (ret)
 838                 return ret;
 839
 840         ret = atmel_nfc_exec_op(nc, true);
 841         if (ret) {
 842                 atmel_nand_pmecc_disable(chip, raw);
 843                 dev_err(nc->base.dev,
 844                         "Failed to transfer NAND page data (err = %d)\n",
 845                         ret);
 846                 return ret;
 847         }
 848
 849         ret = atmel_nand_pmecc_generate_eccbytes(chip, raw);
 850
 851         atmel_nand_pmecc_disable(chip, raw);
 852
 853         if (ret)
 854                 return ret;
 855
 856         atmel_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize);
 857
 858         nc->op.cmds[0] = NAND_CMD_PAGEPROG;
 859         nc->op.ncmds = 1;
 860         nc->op.cs = nand->activecs->id;
 861         ret = atmel_nfc_exec_op(nc, true);
 862         if (ret)
 863                 dev_err(nc->base.dev, "Failed to program NAND page (err = %d)\n",
 864                         ret);
 865
 866         status = chip->waitfunc(mtd, chip);
 867         if (status & NAND_STATUS_FAIL)
 868                 return -EIO;
 869
 870         return ret;
 871 }
 872
 873 static int
 874 atmel_hsmc_nand_pmecc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
 875                                  const u8 *buf, int oob_required,
 876                                  int page)
 877 {
 878         return atmel_hsmc_nand_pmecc_write_pg(chip, buf, oob_required, page,
 879                                               false);
 880 }
 881
 882 static int
 883 atmel_hsmc_nand_pmecc_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
 884                                      const u8 *buf,
 885                                      int oob_required, int page)
 886 {
 887         return atmel_hsmc_nand_pmecc_write_pg(chip, buf, oob_required, page,
 888                                               true);
 889 }
 890
 891 static int atmel_hsmc_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf,
 892                                          bool oob_required, int page,
 893                                          bool raw)
 894 {
 895         struct mtd_info *mtd = nand_to_mtd(chip);
 896         struct atmel_nand *nand = to_atmel_nand(chip);
 897         struct atmel_hsmc_nand_controller *nc;
 898         int ret;
 899
 900         nc = to_hsmc_nand_controller(nand->controller);
 901
 902         /*
 903          * Optimized read page accessors only work when the NAND R/B pin is
 904          * connected to a native SoC R/B pin. If that's not the case, fallback
 905          * to the non-optimized one.
 906          */
 907         if (nand->activecs->rb.type != ATMEL_NAND_NATIVE_RB) {
 908                 nand_read_page_op(chip, page, 0, NULL, 0);
 909
 910                 return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page,
 911                                                 raw);
 912         }
 913
 914         nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READ0;
 915
 916         if (mtd->writesize > 512)
 917                 nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READSTART;
 918
 919         atmel_nfc_set_op_addr(chip, page, 0x0);
 920         nc->op.cs = nand->activecs->id;
 921         nc->op.data = ATMEL_NFC_READ_DATA;
 922
 923         ret = atmel_nand_pmecc_enable(chip, NAND_ECC_READ, raw);
 924         if (ret)
 925                 return ret;
 926
 927         ret = atmel_nfc_exec_op(nc, true);
 928         if (ret) {
 929                 atmel_nand_pmecc_disable(chip, raw);
 930                 dev_err(nc->base.dev,
 931                         "Failed to load NAND page data (err = %d)\n",
 932                         ret);
 933                 return ret;
 934         }
 935
 936         atmel_nfc_copy_from_sram(chip, buf, true);
 937
 938         ret = atmel_nand_pmecc_correct_data(chip, buf, raw);
 939
 940         atmel_nand_pmecc_disable(chip, raw);
 941
 942         return ret;
 943 }
 944
 945 static int atmel_hsmc_nand_pmecc_read_page(struct mtd_info *mtd,
 946                                            struct nand_chip *chip, u8 *buf,
 947                                            int oob_required, int page)
 948 {
 949         return atmel_hsmc_nand_pmecc_read_pg(chip, buf, oob_required, page,
 950                                              false);
 951 }
 952
 953 static int atmel_hsmc_nand_pmecc_read_page_raw(struct mtd_info *mtd,
 954                                                struct nand_chip *chip,
 955                                                u8 *buf, int oob_required,
 956                                                int page)
 957 {
 958         return atmel_hsmc_nand_pmecc_read_pg(chip, buf, oob_required, page,
 959                                              true);
 960 }
 961
 962 static int nand_ooblayout_ecc_lp(struct mtd_info *mtd, int section,
 963                                  struct mtd_oob_region *oobregion)
 964 {
 965         struct nand_chip *chip = mtd_to_nand(mtd);
 966         struct nand_ecc_ctrl *ecc = &chip->ecc;
 967
 968         if (section || !ecc->total)
 969                 return -ERANGE;
 970
 971         oobregion->length = ecc->total;
 972         oobregion->offset = mtd->oobsize - oobregion->length;
 973
 974         return 0;
 975 }
 976
 977 static int nand_ooblayout_free_lp(struct mtd_info *mtd, int section,
 978                                   struct mtd_oob_region *oobregion)
 979 {
 980         struct nand_chip *chip = mtd_to_nand(mtd);
 981         struct nand_ecc_ctrl *ecc = &chip->ecc;
 982
 983         if (section)
 984                 return -ERANGE;
 985
 986         oobregion->length = mtd->oobsize - ecc->total - 2;
 987         oobregion->offset = 2;
 988
 989         return 0;
 990 }
 991
 992 static const struct mtd_ooblayout_ops nand_ooblayout_lp_ops = {
 993         .ecc = nand_ooblayout_ecc_lp,
 994         .rfree = nand_ooblayout_free_lp,
 995 };
 996
 997 const struct mtd_ooblayout_ops *nand_get_large_page_ooblayout(void)
 998 {
 999         return &nand_ooblayout_lp_ops;
1000 }
1001
1002 static int atmel_nand_pmecc_init(struct nand_chip *chip)
1003 {
1004         struct mtd_info *mtd = nand_to_mtd(chip);
1005         struct atmel_nand *nand = to_atmel_nand(chip);
1006         struct atmel_nand_controller *nc;
1007         struct atmel_pmecc_user_req req;
1008
1009         nc = to_nand_controller(nand->controller);
1010
1011         if (!nc->pmecc) {
1012                 dev_err(nc->dev, "HW ECC not supported\n");
1013                 return -EOPNOTSUPP;
1014         }
1015
1016         if (nc->caps->legacy_of_bindings) {
1017                 u32 val;
1018
1019                 if (!ofnode_read_u32(nc->dev->node_, "atmel,pmecc-cap", &val))
1020                         chip->ecc.strength = val;
1021
1022                 if (!ofnode_read_u32(nc->dev->node_,
1023                                      "atmel,pmecc-sector-size",
1024                                      &val))
1025                         chip->ecc.size = val;
1026         }
1027
1028         if (chip->ecc.options & NAND_ECC_MAXIMIZE)
1029                 req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH;
1030         else if (chip->ecc.strength)
1031                 req.ecc.strength = chip->ecc.strength;
1032         else
1033                 req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH;
1034
1035         if (chip->ecc.size)
1036                 req.ecc.sectorsize = chip->ecc.size;
1037         else
1038                 req.ecc.sectorsize = ATMEL_PMECC_SECTOR_SIZE_AUTO;
1039
1040         req.pagesize = mtd->writesize;
1041         req.oobsize = mtd->oobsize;
1042
1043         if (mtd->writesize <= 512) {
1044                 req.ecc.bytes = 4;
1045                 req.ecc.ooboffset = 0;
1046         } else {
1047                 req.ecc.bytes = mtd->oobsize - 2;
1048                 req.ecc.ooboffset = ATMEL_PMECC_OOBOFFSET_AUTO;
1049         }
1050
1051         nand->pmecc = atmel_pmecc_create_user(nc->pmecc, &req);
1052         if (IS_ERR(nand->pmecc))
1053                 return PTR_ERR(nand->pmecc);
1054
1055         chip->ecc.algo = NAND_ECC_BCH;
1056         chip->ecc.size = req.ecc.sectorsize;
1057         chip->ecc.bytes = req.ecc.bytes / req.ecc.nsectors;
1058         chip->ecc.strength = req.ecc.strength;
1059
1060         chip->options |= NAND_NO_SUBPAGE_WRITE;
1061
1062         mtd_set_ooblayout(mtd, nand_get_large_page_ooblayout());
1063         pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
1064                                 mtd->oobsize,
1065                                 chip->ecc.bytes);
1066         chip->ecc.layout = &atmel_pmecc_oobinfo;
1067
1068         return 0;
1069 }
1070
1071 static int atmel_nand_ecc_init(struct nand_chip *chip)
1072 {
1073         struct atmel_nand_controller *nc;
1074         struct atmel_nand *nand = to_atmel_nand(chip);
1075         int ret;
1076
1077         nc = to_nand_controller(nand->controller);
1078
1079         switch (chip->ecc.mode) {
1080         case NAND_ECC_NONE:
1081         case NAND_ECC_SOFT:
1082                 /*
1083                  * Nothing to do, the core will initialize everything for us.
1084                  */
1085                 break;
1086
1087         case NAND_ECC_HW:
1088                 ret = atmel_nand_pmecc_init(chip);
1089                 if (ret)
1090                         return ret;
1091
1092                 chip->ecc.read_page = atmel_nand_pmecc_read_page;
1093                 chip->ecc.write_page = atmel_nand_pmecc_write_page;
1094                 chip->ecc.read_page_raw = atmel_nand_pmecc_read_page_raw;
1095                 chip->ecc.write_page_raw = atmel_nand_pmecc_write_page_raw;
1096                 break;
1097
1098         default:
1099                 /* Other modes are not supported. */
1100                 dev_err(nc->dev, "Unsupported ECC mode: %d\n",
1101                         chip->ecc.mode);
1102                 return -EOPNOTSUPP;
1103         }
1104
1105         return 0;
1106 }
1107
1108 static int atmel_hsmc_nand_ecc_init(struct nand_chip *chip)
1109 {
1110         int ret;
1111
1112         ret = atmel_nand_ecc_init(chip);
1113         if (ret)
1114                 return ret;
1115
1116         if (chip->ecc.mode != NAND_ECC_HW)
1117                 return 0;
1118
1119         /* Adjust the ECC operations for the HSMC IP. */
1120         chip->ecc.read_page = atmel_hsmc_nand_pmecc_read_page;
1121         chip->ecc.write_page = atmel_hsmc_nand_pmecc_write_page;
1122         chip->ecc.read_page_raw = atmel_hsmc_nand_pmecc_read_page_raw;
1123         chip->ecc.write_page_raw = atmel_hsmc_nand_pmecc_write_page_raw;
1124
1125         return 0;
1126 }
1127
1128 static int atmel_smc_nand_prepare_smcconf(struct atmel_nand *nand,
1129                                           const struct nand_data_interface *conf,
1130                                           struct atmel_smc_cs_conf *smcconf)
1131 {
1132         u32 ncycles, totalcycles, timeps, mckperiodps;
1133         struct atmel_nand_controller *nc;
1134         int ret;
1135
1136         nc = to_nand_controller(nand->controller);
1137
1138         /* DDR interface not supported. */
1139         if (conf->type != NAND_SDR_IFACE)
1140                 return -EOPNOTSUPP;
1141
1142         /*
1143          * tRC < 30ns implies EDO mode. This controller does not support this
1144          * mode.
1145          */
1146         if (conf->timings.sdr.tRC_min < 30000)
1147                 return -EOPNOTSUPP;
1148
1149         atmel_smc_cs_conf_init(smcconf);
1150
1151         mckperiodps = NSEC_PER_SEC / clk_get_rate(nc->mck);
1152         mckperiodps *= 1000;
1153
1154         /*
1155          * Set write pulse timing. This one is easy to extract:
1156          *
1157          * NWE_PULSE = tWP
1158          */
1159         ncycles = DIV_ROUND_UP(conf->timings.sdr.tWP_min, mckperiodps);
1160         totalcycles = ncycles;
1161         ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NWE_SHIFT,
1162                                           ncycles);
1163         if (ret)
1164                 return ret;
1165
1166         /*
1167          * The write setup timing depends on the operation done on the NAND.
1168          * All operations goes through the same data bus, but the operation
1169          * type depends on the address we are writing to (ALE/CLE address
1170          * lines).
1171          * Since we have no way to differentiate the different operations at
1172          * the SMC level, we must consider the worst case (the biggest setup
1173          * time among all operation types):
1174          *
1175          * NWE_SETUP = max(tCLS, tCS, tALS, tDS) - NWE_PULSE
1176          */
1177         timeps = max3(conf->timings.sdr.tCLS_min, conf->timings.sdr.tCS_min,
1178                       conf->timings.sdr.tALS_min);
1179         timeps = max(timeps, conf->timings.sdr.tDS_min);
1180         ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1181         ncycles = ncycles > totalcycles ? ncycles - totalcycles : 0;
1182         totalcycles += ncycles;
1183         ret = atmel_smc_cs_conf_set_setup(smcconf, ATMEL_SMC_NWE_SHIFT,
1184                                           ncycles);
1185         if (ret)
1186                 return ret;
1187
1188         /*
1189          * As for the write setup timing, the write hold timing depends on the
1190          * operation done on the NAND:
1191          *
1192          * NWE_HOLD = max(tCLH, tCH, tALH, tDH, tWH)
1193          */
1194         timeps = max3(conf->timings.sdr.tCLH_min, conf->timings.sdr.tCH_min,
1195                       conf->timings.sdr.tALH_min);
1196         timeps = max3(timeps, conf->timings.sdr.tDH_min,
1197                       conf->timings.sdr.tWH_min);
1198         ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1199         totalcycles += ncycles;
1200
1201         /*
1202          * The write cycle timing is directly matching tWC, but is also
1203          * dependent on the other timings on the setup and hold timings we
1204          * calculated earlier, which gives:
1205          *
1206          * NWE_CYCLE = max(tWC, NWE_SETUP + NWE_PULSE + NWE_HOLD)
1207          */
1208         ncycles = DIV_ROUND_UP(conf->timings.sdr.tWC_min, mckperiodps);
1209         ncycles = max(totalcycles, ncycles);
1210         ret = atmel_smc_cs_conf_set_cycle(smcconf, ATMEL_SMC_NWE_SHIFT,
1211                                           ncycles);
1212         if (ret)
1213                 return ret;
1214
1215         /*
1216          * We don't want the CS line to be toggled between each byte/word
1217          * transfer to the NAND. The only way to guarantee that is to have the
1218          * NCS_{WR,RD}_{SETUP,HOLD} timings set to 0, which in turn means:
1219          *
1220          * NCS_WR_PULSE = NWE_CYCLE
1221          */
1222         ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NCS_WR_SHIFT,
1223                                           ncycles);
1224         if (ret)
1225                 return ret;
1226
1227         /*
1228          * As for the write setup timing, the read hold timing depends on the
1229          * operation done on the NAND:
1230          *
1231          * NRD_HOLD = max(tREH, tRHOH)
1232          */
1233         timeps = max(conf->timings.sdr.tREH_min, conf->timings.sdr.tRHOH_min);
1234         ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1235         totalcycles = ncycles;
1236
1237         /*
1238          * TDF = tRHZ - NRD_HOLD
1239          */
1240         ncycles = DIV_ROUND_UP(conf->timings.sdr.tRHZ_max, mckperiodps);
1241         ncycles -= totalcycles;
1242
1243         /*
1244          * In ONFI 4.0 specs, tRHZ has been increased to support EDO NANDs and
1245          * we might end up with a config that does not fit in the TDF field.
1246          * Just take the max value in this case and hope that the NAND is more
1247          * tolerant than advertised.
1248          */
1249         if (ncycles > ATMEL_SMC_MODE_TDF_MAX)
1250                 ncycles = ATMEL_SMC_MODE_TDF_MAX;
1251         else if (ncycles < ATMEL_SMC_MODE_TDF_MIN)
1252                 ncycles = ATMEL_SMC_MODE_TDF_MIN;
1253
1254         smcconf->mode |= ATMEL_SMC_MODE_TDF(ncycles) |
1255                          ATMEL_SMC_MODE_TDFMODE_OPTIMIZED;
1256
1257         /*
1258          * Read pulse timing directly matches tRP:
1259          *
1260          * NRD_PULSE = tRP
1261          */
1262         ncycles = DIV_ROUND_UP(conf->timings.sdr.tRP_min, mckperiodps);
1263         totalcycles += ncycles;
1264         ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NRD_SHIFT,
1265                                           ncycles);
1266         if (ret)
1267                 return ret;
1268
1269         /*
1270          * The write cycle timing is directly matching tWC, but is also
1271          * dependent on the setup and hold timings we calculated earlier,
1272          * which gives:
1273          *
1274          * NRD_CYCLE = max(tRC, NRD_PULSE + NRD_HOLD)
1275          *
1276          * NRD_SETUP is always 0.
1277          */
1278         ncycles = DIV_ROUND_UP(conf->timings.sdr.tRC_min, mckperiodps);
1279         ncycles = max(totalcycles, ncycles);
1280         ret = atmel_smc_cs_conf_set_cycle(smcconf, ATMEL_SMC_NRD_SHIFT,
1281                                           ncycles);
1282         if (ret)
1283                 return ret;
1284
1285         /*
1286          * We don't want the CS line to be toggled between each byte/word
1287          * transfer from the NAND. The only way to guarantee that is to have
1288          * the NCS_{WR,RD}_{SETUP,HOLD} timings set to 0, which in turn means:
1289          *
1290          * NCS_RD_PULSE = NRD_CYCLE
1291          */
1292         ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NCS_RD_SHIFT,
1293                                           ncycles);
1294         if (ret)
1295                 return ret;
1296
1297         /* Txxx timings are directly matching tXXX ones. */
1298         ncycles = DIV_ROUND_UP(conf->timings.sdr.tCLR_min, mckperiodps);
1299         ret = atmel_smc_cs_conf_set_timing(smcconf,
1300                                            ATMEL_HSMC_TIMINGS_TCLR_SHIFT,
1301                                            ncycles);
1302         if (ret)
1303                 return ret;
1304
1305         ncycles = DIV_ROUND_UP(conf->timings.sdr.tADL_min, mckperiodps);
1306         ret = atmel_smc_cs_conf_set_timing(smcconf,
1307                                            ATMEL_HSMC_TIMINGS_TADL_SHIFT,
1308                                            ncycles);
1309         /*
1310          * Version 4 of the ONFI spec mandates that tADL be at least 400
1311          * nanoseconds, but, depending on the master clock rate, 400 ns may not
1312          * fit in the tADL field of the SMC reg. We need to relax the check and
1313          * accept the -ERANGE return code.
1314          *
1315          * Note that previous versions of the ONFI spec had a lower tADL_min
1316          * (100 or 200 ns). It's not clear why this timing constraint got
1317          * increased but it seems most NANDs are fine with values lower than
1318          * 400ns, so we should be safe.
1319          */
1320         if (ret && ret != -ERANGE)
1321                 return ret;
1322
1323         ncycles = DIV_ROUND_UP(conf->timings.sdr.tAR_min, mckperiodps);
1324         ret = atmel_smc_cs_conf_set_timing(smcconf,
1325                                            ATMEL_HSMC_TIMINGS_TAR_SHIFT,
1326                                            ncycles);
1327         if (ret)
1328                 return ret;
1329
1330         ncycles = DIV_ROUND_UP(conf->timings.sdr.tRR_min, mckperiodps);
1331         ret = atmel_smc_cs_conf_set_timing(smcconf,
1332                                            ATMEL_HSMC_TIMINGS_TRR_SHIFT,
1333                                            ncycles);
1334         if (ret)
1335                 return ret;
1336
1337         ncycles = DIV_ROUND_UP(conf->timings.sdr.tWB_max, mckperiodps);
1338         ret = atmel_smc_cs_conf_set_timing(smcconf,
1339                                            ATMEL_HSMC_TIMINGS_TWB_SHIFT,
1340                                            ncycles);
1341         if (ret)
1342                 return ret;
1343
1344         /* Attach the CS line to the NFC logic. */
1345         smcconf->timings |= ATMEL_HSMC_TIMINGS_NFSEL;
1346
1347         /* Set the appropriate data bus width. */
1348         if (nand->base.options & NAND_BUSWIDTH_16)
1349                 smcconf->mode |= ATMEL_SMC_MODE_DBW_16;
1350
1351         /* Operate in NRD/NWE READ/WRITEMODE. */
1352         smcconf->mode |= ATMEL_SMC_MODE_READMODE_NRD |
1353                          ATMEL_SMC_MODE_WRITEMODE_NWE;
1354
1355         return 0;
1356 }
1357
1358 static int
1359 atmel_smc_nand_setup_data_interface(struct atmel_nand *nand,
1360                                     int csline,
1361                                     const struct nand_data_interface *conf)
1362 {
1363         struct atmel_nand_controller *nc;
1364         struct atmel_smc_cs_conf smcconf;
1365         struct atmel_nand_cs *cs;
1366         int ret;
1367
1368         nc = to_nand_controller(nand->controller);
1369
1370         ret = atmel_smc_nand_prepare_smcconf(nand, conf, &smcconf);
1371         if (ret)
1372                 return ret;
1373
1374         if (csline == NAND_DATA_IFACE_CHECK_ONLY)
1375                 return 0;
1376
1377         cs = &nand->cs[csline];
1378         cs->smcconf = smcconf;
1379
1380         atmel_smc_cs_conf_apply(nc->smc, cs->id, &cs->smcconf);
1381
1382         return 0;
1383 }
1384
1385 static int
1386 atmel_hsmc_nand_setup_data_interface(struct atmel_nand *nand,
1387                                      int csline,
1388                                      const struct nand_data_interface *conf)
1389 {
1390         struct atmel_hsmc_nand_controller *nc;
1391         struct atmel_smc_cs_conf smcconf;
1392         struct atmel_nand_cs *cs;
1393         int ret;
1394
1395         nc = to_hsmc_nand_controller(nand->controller);
1396
1397         ret = atmel_smc_nand_prepare_smcconf(nand, conf, &smcconf);
1398         if (ret)
1399                 return ret;
1400
1401         if (csline == NAND_DATA_IFACE_CHECK_ONLY)
1402                 return 0;
1403
1404         cs = &nand->cs[csline];
1405         cs->smcconf = smcconf;
1406
1407         if (cs->rb.type == ATMEL_NAND_NATIVE_RB)
1408                 cs->smcconf.timings |= ATMEL_HSMC_TIMINGS_RBNSEL(cs->rb.id);
1409
1410         atmel_hsmc_cs_conf_apply(nc->base.smc, nc->hsmc_layout, cs->id,
1411                                  &cs->smcconf);
1412
1413         return 0;
1414 }
1415
1416 static int atmel_nand_setup_data_interface(struct mtd_info *mtd, int csline,
1417                                            const struct nand_data_interface *conf)
1418 {
1419         struct nand_chip *chip = mtd_to_nand(mtd);
1420         struct atmel_nand *nand = to_atmel_nand(chip);
1421         struct atmel_nand_controller *nc;
1422
1423         nc = to_nand_controller(nand->controller);
1424
1425         if (csline >= nand->numcs ||
1426             (csline < 0 && csline != NAND_DATA_IFACE_CHECK_ONLY))
1427                 return -EINVAL;
1428
1429         return nc->caps->ops->setup_data_interface(nand, csline, conf);
1430 }
1431
1432 #define NAND_KEEP_TIMINGS       0x00800000
1433
1434 static void atmel_nand_init(struct atmel_nand_controller *nc,
1435                             struct atmel_nand *nand)
1436 {
1437         struct nand_chip *chip = &nand->base;
1438         struct mtd_info *mtd = nand_to_mtd(chip);
1439
1440         mtd->dev->parent = nc->dev;
1441         nand->controller = &nc->base;
1442
1443         chip->cmd_ctrl = atmel_nand_cmd_ctrl;
1444         chip->read_byte = atmel_nand_read_byte;
1445         chip->write_byte = atmel_nand_write_byte;
1446         chip->read_buf = atmel_nand_read_buf;
1447         chip->write_buf = atmel_nand_write_buf;
1448         chip->select_chip = atmel_nand_select_chip;
1449         chip->setup_data_interface = atmel_nand_setup_data_interface;
1450
1451         if (!nc->mck || !nc->caps->ops->setup_data_interface)
1452                 chip->options |= NAND_KEEP_TIMINGS;
1453
1454         /* Some NANDs require a longer delay than the default one (20us). */
1455         chip->chip_delay = 40;
1456
1457         /* Default to HW ECC if pmecc is available. */
1458         if (nc->pmecc)
1459                 chip->ecc.mode = NAND_ECC_HW;
1460 }
1461
1462 static void atmel_smc_nand_init(struct atmel_nand_controller *nc,
1463                                 struct atmel_nand *nand)
1464 {
1465         struct atmel_smc_nand_controller *smc_nc;
1466         int i;
1467
1468         atmel_nand_init(nc, nand);
1469
1470         smc_nc = to_smc_nand_controller(nand->controller);
1471         if (!smc_nc->ebi_csa_regmap)
1472                 return;
1473
1474         /* Attach the CS to the NAND Flash logic. */
1475         for (i = 0; i < nand->numcs; i++)
1476                 regmap_update_bits(smc_nc->ebi_csa_regmap,
1477                                    smc_nc->ebi_csa->offs,
1478                                    BIT(nand->cs[i].id), BIT(nand->cs[i].id));
1479
1480         if (smc_nc->ebi_csa->nfd0_on_d16)
1481                 regmap_update_bits(smc_nc->ebi_csa_regmap,
1482                                    smc_nc->ebi_csa->offs,
1483                                    smc_nc->ebi_csa->nfd0_on_d16,
1484                                    smc_nc->ebi_csa->nfd0_on_d16);
1485 }
1486
1487 static void atmel_hsmc_nand_init(struct atmel_nand_controller *nc,
1488                                  struct atmel_nand *nand)
1489 {
1490         struct nand_chip *chip = &nand->base;
1491
1492         atmel_nand_init(nc, nand);
1493
1494         /* Overload some methods for the HSMC controller. */
1495         chip->cmd_ctrl = atmel_hsmc_nand_cmd_ctrl;
1496         chip->select_chip = atmel_hsmc_nand_select_chip;
1497 }
1498
1499 static int atmel_nand_controller_remove_nand(struct atmel_nand *nand)
1500 {
1501         list_del(&nand->node);
1502
1503         return 0;
1504 }
1505
1506 static struct atmel_nand *atmel_nand_create(struct atmel_nand_controller *nc,
1507                                             ofnode np,
1508                                             int reg_cells)
1509 {
1510         struct atmel_nand *nand;
1511         ofnode n;
1512         int numcs = 0;
1513         int ret, i;
1514         u32 val;
1515         fdt32_t faddr;
1516         phys_addr_t base;
1517
1518         /* Count num of nand nodes */
1519         ofnode_for_each_subnode(n, ofnode_get_parent(np))
1520                 numcs++;
1521         if (numcs < 1) {
1522                 dev_err(nc->dev, "Missing or invalid reg property\n");
1523                 return ERR_PTR(-EINVAL);
1524         }
1525
1526         nand = devm_kzalloc(nc->dev,
1527                             sizeof(struct atmel_nand) +
1528                             (numcs * sizeof(struct atmel_nand_cs)),
1529                             GFP_KERNEL);
1530         if (!nand) {
1531                 dev_err(nc->dev, "Failed to allocate NAND object\n");
1532                 return ERR_PTR(-ENOMEM);
1533         }
1534
1535         nand->numcs = numcs;
1536
1537         gpio_request_by_name_nodev(np, "det-gpios", 0, &nand->cdgpio,
1538                                    GPIOD_IS_IN);
1539
1540         for (i = 0; i < numcs; i++) {
1541                 ret = ofnode_read_u32(np, "reg", &val);
1542                 if (ret) {
1543                         dev_err(nc->dev, "Invalid reg property (err = %d)\n",
1544                                 ret);
1545                         return ERR_PTR(ret);
1546                 }
1547                 nand->cs[i].id = val;
1548
1549                 /* Read base address */
1550                 struct resource res;
1551
1552                 if (ofnode_read_resource(np, 0, &res)) {
1553                         dev_err(nc->dev, "Unable to read resource\n");
1554                         return ERR_PTR(-ENOMEM);
1555                 }
1556
1557                 faddr = cpu_to_fdt32(val);
1558                 base = ofnode_translate_address(np, &faddr);
1559                 nand->cs[i].io.virt = (void *)base;
1560
1561                 if (!ofnode_read_u32(np, "atmel,rb", &val)) {
1562                         if (val > ATMEL_NFC_MAX_RB_ID)
1563                                 return ERR_PTR(-EINVAL);
1564
1565                         nand->cs[i].rb.type = ATMEL_NAND_NATIVE_RB;
1566                         nand->cs[i].rb.id = val;
1567                 } else {
1568                         ret = gpio_request_by_name_nodev(np, "rb-gpios", 0,
1569                                                          &nand->cs[i].rb.gpio,
1570                                                          GPIOD_IS_IN);
1571                         if (ret && ret != -ENOENT)
1572                                 dev_err(nc->dev, "Failed to get R/B gpio (err = %d)\n", ret);
1573                         if (!ret)
1574                                 nand->cs[i].rb.type = ATMEL_NAND_GPIO_RB;
1575                 }
1576
1577                 gpio_request_by_name_nodev(np, "cs-gpios", 0,
1578                                            &nand->cs[i].csgpio,
1579                                            GPIOD_IS_OUT);
1580         }
1581
1582         nand_set_flash_node(&nand->base, np);
1583
1584         return nand;
1585 }
1586
1587 static int nand_attach(struct nand_chip *chip)
1588 {
1589         struct atmel_nand *nand = to_atmel_nand(chip);
1590
1591         if (nand->controller->ops && nand->controller->ops->attach_chip)
1592                 return nand->controller->ops->attach_chip(chip);
1593
1594         return 0;
1595 }
1596
1597 int atmel_nand_scan(struct mtd_info *mtd, int maxchips)
1598 {
1599         int ret;
1600
1601         ret = nand_scan_ident(mtd, maxchips, NULL);
1602         if (ret)
1603                 return ret;
1604
1605         ret = nand_attach(mtd_to_nand(mtd));
1606         if (ret)
1607                 return ret;
1608
1609         ret = nand_scan_tail(mtd);
1610         return ret;
1611 }
1612
1613 static int
1614 atmel_nand_controller_add_nand(struct atmel_nand_controller *nc,
1615                                struct atmel_nand *nand)
1616 {
1617         struct nand_chip *chip = &nand->base;
1618         struct mtd_info *mtd = nand_to_mtd(chip);
1619         int ret;
1620
1621         /* No card inserted, skip this NAND. */
1622         if (dm_gpio_is_valid(&nand->cdgpio) &&
1623             dm_gpio_get_value(&nand->cdgpio)) {
1624                 dev_info(nc->dev, "No SmartMedia card inserted.\n");
1625                 return 0;
1626         }
1627
1628         nc->caps->ops->nand_init(nc, nand);
1629
1630         ret = atmel_nand_scan(mtd, nand->numcs);
1631         if (ret) {
1632                 dev_err(nc->dev, "NAND scan failed: %d\n", ret);
1633                 return ret;
1634         }
1635
1636         ret = nand_register(0, mtd);
1637         if (ret) {
1638                 dev_err(nc->dev, "nand register failed: %d\n", ret);
1639                 return ret;
1640         }
1641
1642         list_add_tail(&nand->node, &nc->chips);
1643
1644         return 0;
1645 }
1646
1647 static int
1648 atmel_nand_controller_remove_nands(struct atmel_nand_controller *nc)
1649 {
1650         struct atmel_nand *nand, *tmp;
1651         int ret;
1652
1653         list_for_each_entry_safe(nand, tmp, &nc->chips, node) {
1654                 ret = atmel_nand_controller_remove_nand(nand);
1655                 if (ret)
1656                         return ret;
1657         }
1658
1659         return 0;
1660 }
1661
1662 static int atmel_nand_controller_add_nands(struct atmel_nand_controller *nc)
1663 {
1664         ofnode np;
1665         ofnode nand_np;
1666         int ret, reg_cells;
1667         u32 val;
1668
1669         /* TODO:
1670          * Add support for legacy nands
1671          */
1672
1673         np = nc->dev->node_;
1674
1675         ret = ofnode_read_u32(np, "#address-cells", &val);
1676         if (ret) {
1677                 dev_err(nc->dev, "missing #address-cells property\n");
1678                 return ret;
1679         }
1680
1681         reg_cells = val;
1682
1683         ret = ofnode_read_u32(np, "#size-cells", &val);
1684         if (ret) {
1685                 dev_err(nc->dev, "missing #size-cells property\n");
1686                 return ret;
1687         }
1688
1689         reg_cells += val;
1690
1691         ofnode_for_each_subnode(nand_np, np) {
1692                 struct atmel_nand *nand;
1693
1694                 nand = atmel_nand_create(nc, nand_np, reg_cells);
1695                 if (IS_ERR(nand)) {
1696                         ret = PTR_ERR(nand);
1697                         goto err;
1698                 }
1699
1700                 ret = atmel_nand_controller_add_nand(nc, nand);
1701                 if (ret)
1702                         goto err;
1703         }
1704
1705         return 0;
1706
1707 err:
1708         atmel_nand_controller_remove_nands(nc);
1709
1710         return ret;
1711 }
1712
1713 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9260_ebi_csa = {
1714         .offs = AT91SAM9260_MATRIX_EBICSA,
1715 };
1716
1717 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9261_ebi_csa = {
1718         .offs = AT91SAM9261_MATRIX_EBICSA,
1719 };
1720
1721 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9263_ebi_csa = {
1722         .offs = AT91SAM9263_MATRIX_EBI0CSA,
1723 };
1724
1725 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9rl_ebi_csa = {
1726         .offs = AT91SAM9RL_MATRIX_EBICSA,
1727 };
1728
1729 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9g45_ebi_csa = {
1730         .offs = AT91SAM9G45_MATRIX_EBICSA,
1731 };
1732
1733 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9n12_ebi_csa = {
1734         .offs = AT91SAM9N12_MATRIX_EBICSA,
1735 };
1736
1737 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9x5_ebi_csa = {
1738         .offs = AT91SAM9X5_MATRIX_EBICSA,
1739 };
1740
1741 static const struct atmel_smc_nand_ebi_csa_cfg sam9x60_ebi_csa = {
1742         .offs = AT91_SFR_CCFG_EBICSA,
1743         .nfd0_on_d16 = AT91_SFR_CCFG_NFD0_ON_D16,
1744 };
1745
1746 static const struct udevice_id atmel_ebi_csa_regmap_of_ids[] = {
1747         {
1748                 .compatible = "atmel,at91sam9260-matrix",
1749                 .data = (ulong)&at91sam9260_ebi_csa,
1750         },
1751         {
1752                 .compatible = "atmel,at91sam9261-matrix",
1753                 .data = (ulong)&at91sam9261_ebi_csa,
1754         },
1755         {
1756                 .compatible = "atmel,at91sam9263-matrix",
1757                 .data = (ulong)&at91sam9263_ebi_csa,
1758         },
1759         {
1760                 .compatible = "atmel,at91sam9rl-matrix",
1761                 .data = (ulong)&at91sam9rl_ebi_csa,
1762         },
1763         {
1764                 .compatible = "atmel,at91sam9g45-matrix",
1765                 .data = (ulong)&at91sam9g45_ebi_csa,
1766         },
1767         {
1768                 .compatible = "atmel,at91sam9n12-matrix",
1769                 .data = (ulong)&at91sam9n12_ebi_csa,
1770         },
1771         {
1772                 .compatible = "atmel,at91sam9x5-matrix",
1773                 .data = (ulong)&at91sam9x5_ebi_csa,
1774         },
1775         {
1776                 .compatible = "microchip,sam9x60-sfr",
1777                 .data = (ulong)&sam9x60_ebi_csa,
1778         },
1779         { /* sentinel */ },
1780 };
1781
1782 static int atmel_nand_attach_chip(struct nand_chip *chip)
1783 {
1784         struct atmel_nand *nand = to_atmel_nand(chip);
1785         struct atmel_nand_controller *nc = to_nand_controller(nand->controller);
1786         struct mtd_info *mtd = nand_to_mtd(chip);
1787         int ret;
1788
1789         ret = nc->caps->ops->ecc_init(chip);
1790         if (ret)
1791                 return ret;
1792
1793         if (nc->caps->legacy_of_bindings || !ofnode_valid(nc->dev->node_)) {
1794                 /*
1795                  * We keep the MTD name unchanged to avoid breaking platforms
1796                  * where the MTD cmdline parser is used and the bootloader
1797                  * has not been updated to use the new naming scheme.
1798                  */
1799                 mtd->name = "atmel_nand";
1800         } else if (!mtd->name) {
1801                 /*
1802                  * If the new bindings are used and the bootloader has not been
1803                  * updated to pass a new mtdparts parameter on the cmdline, you
1804                  * should define the following property in your nand node:
1805                  *
1806                  *      label = "atmel_nand";
1807                  *
1808                  * This way, mtd->name will be set by the core when
1809                  * nand_set_flash_node() is called.
1810                  */
1811                 sprintf(mtd->name, "%s:nand.%d", nc->dev->name, nand->cs[0].id);
1812         }
1813
1814         return 0;
1815 }
1816
1817 static const struct nand_controller_ops atmel_nand_controller_ops = {
1818         .attach_chip = atmel_nand_attach_chip,
1819 };
1820
1821 static int
1822 atmel_nand_controller_init(struct atmel_nand_controller *nc,
1823                            struct udevice *dev,
1824                            const struct atmel_nand_controller_caps *caps)
1825 {
1826         struct ofnode_phandle_args args;
1827         int ret;
1828
1829         nc->base.ops = &atmel_nand_controller_ops;
1830         INIT_LIST_HEAD(&nc->chips);
1831         nc->dev = dev;
1832         nc->caps = caps;
1833
1834         nc->pmecc = devm_atmel_pmecc_get(dev);
1835         if (IS_ERR(nc->pmecc)) {
1836                 ret = PTR_ERR(nc->pmecc);
1837                 if (ret != -EPROBE_DEFER)
1838                         dev_err(dev, "Could not get PMECC object (err = %d)\n",
1839                                 ret);
1840                 return ret;
1841         }
1842
1843         /* We do not retrieve the SMC syscon when parsing old DTs. */
1844         if (nc->caps->legacy_of_bindings)
1845                 return 0;
1846
1847         nc->mck = devm_kzalloc(dev, sizeof(nc->mck), GFP_KERNEL);
1848         if (!nc->mck)
1849                 return -ENOMEM;
1850
1851         clk_get_by_index(dev->parent, 0, nc->mck);
1852         if (IS_ERR(nc->mck)) {
1853                 dev_err(dev, "Failed to retrieve MCK clk\n");
1854                 return PTR_ERR(nc->mck);
1855         }
1856
1857         ret = ofnode_parse_phandle_with_args(dev->parent->node_,
1858                                              "atmel,smc", NULL, 0, 0, &args);
1859         if (ret) {
1860                 dev_err(dev, "Missing or invalid atmel,smc property\n");
1861                 return -EINVAL;
1862         }
1863
1864         nc->smc = syscon_node_to_regmap(args.node);
1865         if (IS_ERR(nc->smc)) {
1866                 ret = PTR_ERR(nc->smc);
1867                 dev_err(dev, "Could not get SMC regmap (err = %d)\n", ret);
1868                 return 0;
1869         }
1870
1871         return 0;
1872 }
1873
1874 static int
1875 atmel_smc_nand_controller_init(struct atmel_smc_nand_controller *nc)
1876 {
1877         struct udevice *dev = nc->base.dev;
1878         struct ofnode_phandle_args args;
1879         const struct udevice_id *match = NULL;
1880         const char *name;
1881         int ret;
1882         int len;
1883         int i;
1884
1885         /* We do not retrieve the EBICSA regmap when parsing old DTs. */
1886         if (nc->base.caps->legacy_of_bindings)
1887                 return 0;
1888
1889         ret = ofnode_parse_phandle_with_args(dev->parent->node_,
1890                                              nc->base.caps->ebi_csa_regmap_name,
1891                                              NULL, 0, 0, &args);
1892         if (ret) {
1893                 dev_err(dev, "Unable to read ebi csa regmap\n");
1894                 return -EINVAL;
1895         }
1896
1897         name = ofnode_get_property(args.node, "compatible", &len);
1898
1899         for (i = 0; i < ARRAY_SIZE(atmel_ebi_csa_regmap_of_ids); i++) {
1900                 if (!strcmp(name, atmel_ebi_csa_regmap_of_ids[i].compatible)) {
1901                         match = &atmel_ebi_csa_regmap_of_ids[i];
1902                         break;
1903                 }
1904         }
1905
1906         if (!match) {
1907                 dev_err(dev, "Unable to find ebi csa conf");
1908                 return -EINVAL;
1909         }
1910         nc->ebi_csa = (struct atmel_smc_nand_ebi_csa_cfg *)match->data;
1911
1912         nc->ebi_csa_regmap = syscon_node_to_regmap(args.node);
1913         if (IS_ERR(nc->ebi_csa_regmap)) {
1914                 ret = PTR_ERR(nc->ebi_csa_regmap);
1915                 dev_err(dev, "Could not get EBICSA regmap (err = %d)\n", ret);
1916                 return ret;
1917         }
1918
1919         /* TODO:
1920          * The at91sam9263 has 2 EBIs, if the NAND controller is under EBI1
1921          * add 4 to ->ebi_csa->offs.
1922          */
1923
1924         return 0;
1925 }
1926
1927 static int atmel_hsmc_nand_controller_init(struct atmel_hsmc_nand_controller *nc)
1928 {
1929         struct udevice *dev = nc->base.dev;
1930         struct ofnode_phandle_args args;
1931         struct clk smc_clk;
1932         int ret;
1933         u32 addr;
1934
1935         ret = ofnode_parse_phandle_with_args(dev->parent->node_,
1936                                              "atmel,smc", NULL, 0, 0, &args);
1937         if (ret) {
1938                 dev_err(dev, "Missing or invalid atmel,smc property\n");
1939                 return -EINVAL;
1940         }
1941
1942         nc->hsmc_layout = atmel_hsmc_get_reg_layout(args.node);
1943         if (IS_ERR(nc->hsmc_layout)) {
1944                 dev_err(dev, "Could not get hsmc layout\n");
1945                 return -EINVAL;
1946         }
1947
1948         /* Enable smc clock */
1949         ret = clk_get_by_index_nodev(args.node, 0, &smc_clk);
1950         if (ret) {
1951                 dev_err(dev, "Unable to get smc clock (err = %d)", ret);
1952                 return ret;
1953         }
1954
1955         ret = clk_prepare_enable(&smc_clk);
1956         if (ret)
1957                 return ret;
1958
1959         ret = ofnode_parse_phandle_with_args(dev->node_,
1960                                              "atmel,nfc-io", NULL, 0, 0, &args);
1961         if (ret) {
1962                 dev_err(dev, "Missing or invalid atmel,nfc-io property\n");
1963                 return -EINVAL;
1964         }
1965
1966         nc->io = syscon_node_to_regmap(args.node);
1967         if (IS_ERR(nc->io)) {
1968                 ret = PTR_ERR(nc->io);
1969                 dev_err(dev, "Could not get NFC IO regmap\n");
1970                 return ret;
1971         }
1972
1973         ret = ofnode_parse_phandle_with_args(dev->node_,
1974                                              "atmel,nfc-sram", NULL, 0, 0, &args);
1975         if (ret) {
1976                 dev_err(dev, "Missing or invalid atmel,nfc-sram property\n");
1977                 return ret;
1978         }
1979
1980         ret = ofnode_read_u32(args.node, "reg", &addr);
1981         if (ret) {
1982                 dev_err(dev, "Could not read reg addr of nfc sram");
1983                 return ret;
1984         }
1985         nc->sram.virt = (void *)addr;
1986
1987         return 0;
1988 }
1989
1990 static int
1991 atmel_hsmc_nand_controller_remove(struct atmel_nand_controller *nc)
1992 {
1993         struct atmel_hsmc_nand_controller *hsmc_nc;
1994         int ret;
1995
1996         ret = atmel_nand_controller_remove_nands(nc);
1997         if (ret)
1998                 return ret;
1999
2000         hsmc_nc = container_of(nc, struct atmel_hsmc_nand_controller, base);
2001
2002         if (hsmc_nc->clk) {
2003                 clk_disable_unprepare(hsmc_nc->clk);
2004                 devm_clk_put(nc->dev, hsmc_nc->clk);
2005         }
2006
2007         return 0;
2008 }
2009
2010 static int
2011 atmel_hsmc_nand_controller_probe(struct udevice *dev,
2012                                  const struct atmel_nand_controller_caps *caps)
2013 {
2014         struct atmel_hsmc_nand_controller *nc;
2015         int ret;
2016
2017         nc = devm_kzalloc(dev, sizeof(*nc), GFP_KERNEL);
2018         if (!nc)
2019                 return -ENOMEM;
2020
2021         ret = atmel_nand_controller_init(&nc->base, dev, caps);
2022         if (ret)
2023                 return ret;
2024
2025         ret = atmel_hsmc_nand_controller_init(nc);
2026         if (ret)
2027                 return ret;
2028
2029         /* Make sure all irqs are masked before registering our IRQ handler. */
2030         regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff);
2031
2032         /* Initial NFC configuration. */
2033         regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CFG,
2034                      ATMEL_HSMC_NFC_CFG_DTO_MAX);
2035
2036         ret = atmel_nand_controller_add_nands(&nc->base);
2037         if (ret)
2038                 goto err;
2039
2040         return 0;
2041
2042 err:
2043         atmel_hsmc_nand_controller_remove(&nc->base);
2044
2045         return ret;
2046 }
2047
2048 static const struct atmel_nand_controller_ops atmel_hsmc_nc_ops = {
2049         .probe = atmel_hsmc_nand_controller_probe,
2050         .remove = atmel_hsmc_nand_controller_remove,
2051         .ecc_init = atmel_hsmc_nand_ecc_init,
2052         .nand_init = atmel_hsmc_nand_init,
2053         .setup_data_interface = atmel_hsmc_nand_setup_data_interface,
2054 };
2055
2056 static const struct atmel_nand_controller_caps atmel_sama5_nc_caps = {
2057         .has_dma = true,
2058         .ale_offs = BIT(21),
2059         .cle_offs = BIT(22),
2060         .ops = &atmel_hsmc_nc_ops,
2061 };
2062
2063 static int
2064 atmel_smc_nand_controller_probe(struct udevice *dev,
2065                                 const struct atmel_nand_controller_caps *caps)
2066 {
2067         struct atmel_smc_nand_controller *nc;
2068         int ret;
2069
2070         nc = devm_kzalloc(dev, sizeof(*nc), GFP_KERNEL);
2071         if (!nc)
2072                 return -ENOMEM;
2073
2074         ret = atmel_nand_controller_init(&nc->base, dev, caps);
2075         if (ret)
2076                 return ret;
2077
2078         ret = atmel_smc_nand_controller_init(nc);
2079         if (ret)
2080                 return ret;
2081
2082         return atmel_nand_controller_add_nands(&nc->base);
2083 }
2084
2085 static int
2086 atmel_smc_nand_controller_remove(struct atmel_nand_controller *nc)
2087 {
2088         int ret;
2089
2090         ret = atmel_nand_controller_remove_nands(nc);
2091         if (ret)
2092                 return ret;
2093
2094         return 0;
2095 }
2096
2097 /*
2098  * The SMC reg layout of at91rm9200 is completely different which prevents us
2099  * from re-using atmel_smc_nand_setup_data_interface() for the
2100  * ->setup_data_interface() hook.
2101  * At this point, there's no support for the at91rm9200 SMC IP, so we leave
2102  * ->setup_data_interface() unassigned.
2103  */
2104 static const struct atmel_nand_controller_ops at91rm9200_nc_ops = {
2105         .probe = atmel_smc_nand_controller_probe,
2106         .remove = atmel_smc_nand_controller_remove,
2107         .ecc_init = atmel_nand_ecc_init,
2108         .nand_init = atmel_smc_nand_init,
2109 };
2110
2111 static const struct atmel_nand_controller_caps atmel_rm9200_nc_caps = {
2112         .ale_offs = BIT(21),
2113         .cle_offs = BIT(22),
2114         .ebi_csa_regmap_name = "atmel,matrix",
2115         .ops = &at91rm9200_nc_ops,
2116 };
2117
2118 static const struct atmel_nand_controller_ops atmel_smc_nc_ops = {
2119         .probe = atmel_smc_nand_controller_probe,
2120         .remove = atmel_smc_nand_controller_remove,
2121         .ecc_init = atmel_nand_ecc_init,
2122         .nand_init = atmel_smc_nand_init,
2123         .setup_data_interface = atmel_smc_nand_setup_data_interface,
2124 };
2125
2126 static const struct atmel_nand_controller_caps atmel_sam9260_nc_caps = {
2127         .ale_offs = BIT(21),
2128         .cle_offs = BIT(22),
2129         .ebi_csa_regmap_name = "atmel,matrix",
2130         .ops = &atmel_smc_nc_ops,
2131 };
2132
2133 static const struct atmel_nand_controller_caps atmel_sam9261_nc_caps = {
2134         .ale_offs = BIT(22),
2135         .cle_offs = BIT(21),
2136         .ebi_csa_regmap_name = "atmel,matrix",
2137         .ops = &atmel_smc_nc_ops,
2138 };
2139
2140 static const struct atmel_nand_controller_caps atmel_sam9g45_nc_caps = {
2141         .has_dma = true,
2142         .ale_offs = BIT(21),
2143         .cle_offs = BIT(22),
2144         .ebi_csa_regmap_name = "atmel,matrix",
2145         .ops = &atmel_smc_nc_ops,
2146 };
2147
2148 static const struct atmel_nand_controller_caps microchip_sam9x60_nc_caps = {
2149         .has_dma = true,
2150         .ale_offs = BIT(21),
2151         .cle_offs = BIT(22),
2152         .ebi_csa_regmap_name = "microchip,sfr",
2153         .ops = &atmel_smc_nc_ops,
2154 };
2155
2156 /* Only used to parse old bindings. */
2157 static const struct atmel_nand_controller_caps atmel_rm9200_nand_caps = {
2158         .ale_offs = BIT(21),
2159         .cle_offs = BIT(22),
2160         .ops = &atmel_smc_nc_ops,
2161         .legacy_of_bindings = true,
2162 };
2163
2164 static const struct udevice_id atmel_nand_controller_of_ids[] = {
2165         {
2166                 .compatible = "atmel,at91rm9200-nand-controller",
2167                 .data = (ulong)&atmel_rm9200_nc_caps,
2168         },
2169         {
2170                 .compatible = "atmel,at91sam9260-nand-controller",
2171                 .data = (ulong)&atmel_sam9260_nc_caps,
2172         },
2173         {
2174                 .compatible = "atmel,at91sam9261-nand-controller",
2175                 .data = (ulong)&atmel_sam9261_nc_caps,
2176         },
2177         {
2178                 .compatible = "atmel,at91sam9g45-nand-controller",
2179                 .data = (ulong)&atmel_sam9g45_nc_caps,
2180         },
2181         {
2182                 .compatible = "atmel,sama5d3-nand-controller",
2183                 .data = (ulong)&atmel_sama5_nc_caps,
2184         },
2185         {
2186                 .compatible = "microchip,sam9x60-nand-controller",
2187                 .data = (ulong)&microchip_sam9x60_nc_caps,
2188         },
2189         /* Support for old/deprecated bindings: */
2190         {
2191                 .compatible = "atmel,at91rm9200-nand",
2192                 .data = (ulong)&atmel_rm9200_nand_caps,
2193         },
2194         {
2195                 .compatible = "atmel,sama5d4-nand",
2196                 .data = (ulong)&atmel_rm9200_nand_caps,
2197         },
2198         {
2199                 .compatible = "atmel,sama5d2-nand",
2200                 .data = (ulong)&atmel_rm9200_nand_caps,
2201         },
2202         { /* sentinel */ },
2203 };
2204
2205 static int atmel_nand_controller_probe(struct udevice *dev)
2206 {
2207         const struct atmel_nand_controller_caps *caps;
2208         struct udevice *pmecc_dev;
2209
2210         caps = (struct atmel_nand_controller_caps *)dev_get_driver_data(dev);
2211         if (!caps) {
2212                 printf("Could not retrieve NFC caps\n");
2213                 return -EINVAL;
2214         }
2215
2216         /* Probe pmecc driver */
2217         if (uclass_get_device(UCLASS_MTD, 1, &pmecc_dev)) {
2218                 printf("%s: get device fail\n", __func__);
2219                 return -EINVAL;
2220         }
2221
2222         return caps->ops->probe(dev, caps);
2223 }
2224
2225 static int atmel_nand_controller_remove(struct udevice *dev)
2226 {
2227         struct atmel_nand_controller *nc;
2228
2229         nc = (struct atmel_nand_controller *)dev_get_driver_data(dev);
2230
2231         return nc->caps->ops->remove(nc);
2232 }
2233
2234 U_BOOT_DRIVER(atmel_nand_controller) = {
2235         .name = "atmel-nand-controller",
2236         .id = UCLASS_MTD,
2237         .of_match = atmel_nand_controller_of_ids,
2238         .probe = atmel_nand_controller_probe,
2239         .remove = atmel_nand_controller_remove,
2240 };
2241
2242 void board_nand_init(void)
2243 {
2244         struct udevice *dev;
2245         int ret;
2246
2247         ret = uclass_get_device_by_driver(UCLASS_MTD,
2248                                           DM_DRIVER_GET(atmel_nand_controller),
2249                                           &dev);
2250         if (ret && ret != -ENODEV)
2251                 printf("Failed to initialize NAND controller. (error %d)\n",
2252                        ret);
2253 }