arch/arm/mach-imx/imx8m/clock_imx8mm.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2018-2019 NXP
   4  *
   5  * Peng Fan <[email protected]>
   6  */
   7
   8 #include <common.h>
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/imx-regs.h>
  11 #include <asm/arch/sys_proto.h>
  12 #include <asm/global_data.h>
  13 #include <asm/io.h>
  14 #include <div64.h>
  15 #include <errno.h>
  16 #include <linux/bitops.h>
  17 #include <linux/delay.h>
  18
  19 DECLARE_GLOBAL_DATA_PTR;
  20
  21 static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
  22
  23 static u32 get_root_clk(enum clk_root_index clock_id);
  24
  25 #ifdef CONFIG_IMX_HAB
  26 void hab_caam_clock_enable(unsigned char enable)
  27 {
  28         /* The CAAM clock is always on for iMX8M */
  29 }
  30 #endif
  31
  32 void enable_ocotp_clk(unsigned char enable)
  33 {
  34         clock_enable(CCGR_OCOTP, !!enable);
  35 }
  36
  37 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
  38 {
  39         /* 0 - 3 is valid i2c num */
  40         if (i2c_num > 3)
  41                 return -EINVAL;
  42
  43         clock_enable(CCGR_I2C1 + i2c_num, !!enable);
  44
  45         return 0;
  46 }
  47
  48 #ifdef CONFIG_SPL_BUILD
  49 static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = {
  50         PLL_1443X_RATE(1000000000U, 250, 3, 1, 0),
  51         PLL_1443X_RATE(933000000U, 311, 4, 1, 0),
  52         PLL_1443X_RATE(800000000U, 300, 9, 0, 0),
  53         PLL_1443X_RATE(750000000U, 250, 8, 0, 0),
  54         PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
  55         PLL_1443X_RATE(600000000U, 300, 3, 2, 0),
  56         PLL_1443X_RATE(594000000U, 99, 1, 2, 0),
  57         PLL_1443X_RATE(400000000U, 300, 9, 1, 0),
  58         PLL_1443X_RATE(266000000U, 400, 9, 2, 0),
  59         PLL_1443X_RATE(167000000U, 334, 3, 4, 0),
  60         PLL_1443X_RATE(100000000U, 300, 9, 3, 0),
  61 };
  62
  63 static int fracpll_configure(enum pll_clocks pll, u32 freq)
  64 {
  65         int i;
  66         u32 tmp, div_val;
  67         void *pll_base;
  68         struct imx_int_pll_rate_table *rate;
  69
  70         for (i = 0; i < ARRAY_SIZE(imx8mm_fracpll_tbl); i++) {
  71                 if (freq == imx8mm_fracpll_tbl[i].rate)
  72                         break;
  73         }
  74
  75         if (i == ARRAY_SIZE(imx8mm_fracpll_tbl)) {
  76                 printf("%s: No matched freq table %u\n", __func__, freq);
  77                 return -EINVAL;
  78         }
  79
  80         rate = &imx8mm_fracpll_tbl[i];
  81
  82         switch (pll) {
  83         case ANATOP_DRAM_PLL:
  84                 setbits_le32(GPC_BASE_ADDR + 0xEC, 1 << 7);
  85                 setbits_le32(GPC_BASE_ADDR + 0xF8, 1 << 5);
  86                 writel(SRC_DDR1_ENABLE_MASK, SRC_BASE_ADDR + 0x1004);
  87
  88                 pll_base = &ana_pll->dram_pll_gnrl_ctl;
  89                 break;
  90         case ANATOP_VIDEO_PLL:
  91                 pll_base = &ana_pll->video_pll1_gnrl_ctl;
  92                 break;
  93         default:
  94                 return 0;
  95         }
  96         /* Bypass clock and set lock to pll output lock */
  97         tmp = readl(pll_base);
  98         tmp |= BYPASS_MASK;
  99         writel(tmp, pll_base);
 100
 101         /* Enable RST */
 102         tmp &= ~RST_MASK;
 103         writel(tmp, pll_base);
 104
 105         div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
 106                 (rate->sdiv << SDIV_SHIFT);
 107         writel(div_val, pll_base + 4);
 108         writel(rate->kdiv << KDIV_SHIFT, pll_base + 8);
 109
 110         __udelay(100);
 111
 112         /* Disable RST */
 113         tmp |= RST_MASK;
 114         writel(tmp, pll_base);
 115
 116         /* Wait Lock*/
 117         while (!(readl(pll_base) & LOCK_STATUS))
 118                 ;
 119
 120         /* Bypass */
 121         tmp &= ~BYPASS_MASK;
 122         writel(tmp, pll_base);
 123
 124         return 0;
 125 }
 126
 127 void dram_pll_init(ulong pll_val)
 128 {
 129         fracpll_configure(ANATOP_DRAM_PLL, pll_val);
 130 }
 131
 132 static struct dram_bypass_clk_setting imx8mm_dram_bypass_tbl[] = {
 133         DRAM_BYPASS_ROOT_CONFIG(MHZ(100), 2, CLK_ROOT_PRE_DIV1, 2,
 134                                 CLK_ROOT_PRE_DIV2),
 135         DRAM_BYPASS_ROOT_CONFIG(MHZ(250), 3, CLK_ROOT_PRE_DIV2, 2,
 136                                 CLK_ROOT_PRE_DIV2),
 137         DRAM_BYPASS_ROOT_CONFIG(MHZ(400), 1, CLK_ROOT_PRE_DIV2, 3,
 138                                 CLK_ROOT_PRE_DIV2),
 139 };
 140
 141 void dram_enable_bypass(ulong clk_val)
 142 {
 143         int i;
 144         struct dram_bypass_clk_setting *config;
 145
 146         for (i = 0; i < ARRAY_SIZE(imx8mm_dram_bypass_tbl); i++) {
 147                 if (clk_val == imx8mm_dram_bypass_tbl[i].clk)
 148                         break;
 149         }
 150
 151         if (i == ARRAY_SIZE(imx8mm_dram_bypass_tbl)) {
 152                 printf("%s: No matched freq table %lu\n", __func__, clk_val);
 153                 return;
 154         }
 155
 156         config = &imx8mm_dram_bypass_tbl[i];
 157
 158         clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
 159                              CLK_ROOT_SOURCE_SEL(config->alt_root_sel) |
 160                              CLK_ROOT_PRE_DIV(config->alt_pre_div));
 161         clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
 162                              CLK_ROOT_SOURCE_SEL(config->apb_root_sel) |
 163                              CLK_ROOT_PRE_DIV(config->apb_pre_div));
 164         clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
 165                              CLK_ROOT_SOURCE_SEL(1));
 166 }
 167
 168 void dram_disable_bypass(void)
 169 {
 170         clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
 171                              CLK_ROOT_SOURCE_SEL(0));
 172         clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
 173                              CLK_ROOT_SOURCE_SEL(4) |
 174                              CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV5));
 175 }
 176 #endif
 177
 178 int intpll_configure(enum pll_clocks pll, ulong freq)
 179 {
 180         void __iomem *pll_gnrl_ctl, __iomem *pll_div_ctl;
 181         u32 pll_div_ctl_val, pll_clke_masks;
 182
 183         switch (pll) {
 184         case ANATOP_SYSTEM_PLL1:
 185                 pll_gnrl_ctl = &ana_pll->sys_pll1_gnrl_ctl;
 186                 pll_div_ctl = &ana_pll->sys_pll1_div_ctl;
 187                 pll_clke_masks = INTPLL_DIV20_CLKE_MASK |
 188                         INTPLL_DIV10_CLKE_MASK | INTPLL_DIV8_CLKE_MASK |
 189                         INTPLL_DIV6_CLKE_MASK | INTPLL_DIV5_CLKE_MASK |
 190                         INTPLL_DIV4_CLKE_MASK | INTPLL_DIV3_CLKE_MASK |
 191                         INTPLL_DIV2_CLKE_MASK | INTPLL_CLKE_MASK;
 192                 break;
 193         case ANATOP_SYSTEM_PLL2:
 194                 pll_gnrl_ctl = &ana_pll->sys_pll2_gnrl_ctl;
 195                 pll_div_ctl = &ana_pll->sys_pll2_div_ctl;
 196                 pll_clke_masks = INTPLL_DIV20_CLKE_MASK |
 197                         INTPLL_DIV10_CLKE_MASK | INTPLL_DIV8_CLKE_MASK |
 198                         INTPLL_DIV6_CLKE_MASK | INTPLL_DIV5_CLKE_MASK |
 199                         INTPLL_DIV4_CLKE_MASK | INTPLL_DIV3_CLKE_MASK |
 200                         INTPLL_DIV2_CLKE_MASK | INTPLL_CLKE_MASK;
 201                 break;
 202         case ANATOP_SYSTEM_PLL3:
 203                 pll_gnrl_ctl = &ana_pll->sys_pll3_gnrl_ctl;
 204                 pll_div_ctl = &ana_pll->sys_pll3_div_ctl;
 205                 pll_clke_masks = INTPLL_CLKE_MASK;
 206                 break;
 207         case ANATOP_ARM_PLL:
 208                 pll_gnrl_ctl = &ana_pll->arm_pll_gnrl_ctl;
 209                 pll_div_ctl = &ana_pll->arm_pll_div_ctl;
 210                 pll_clke_masks = INTPLL_CLKE_MASK;
 211                 break;
 212         case ANATOP_GPU_PLL:
 213                 pll_gnrl_ctl = &ana_pll->gpu_pll_gnrl_ctl;
 214                 pll_div_ctl = &ana_pll->gpu_pll_div_ctl;
 215                 pll_clke_masks = INTPLL_CLKE_MASK;
 216                 break;
 217         case ANATOP_VPU_PLL:
 218                 pll_gnrl_ctl = &ana_pll->vpu_pll_gnrl_ctl;
 219                 pll_div_ctl = &ana_pll->vpu_pll_div_ctl;
 220                 pll_clke_masks = INTPLL_CLKE_MASK;
 221                 break;
 222         default:
 223                 return -EINVAL;
 224         };
 225
 226         switch (freq) {
 227         case MHZ(600):
 228                 /* 24 * 0x12c / 3 / 2 ^ 2 */
 229                 pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0x12c) |
 230                         INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(2);
 231                 break;
 232         case MHZ(750):
 233                 /* 24 * 0xfa / 2 / 2 ^ 2 */
 234                 pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xfa) |
 235                         INTPLL_PRE_DIV_VAL(2) | INTPLL_POST_DIV_VAL(2);
 236                 break;
 237         case MHZ(800):
 238                 /* 24 * 0x190 / 3 / 2 ^ 2 */
 239                 pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0x190) |
 240                         INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(2);
 241                 break;
 242         case MHZ(1000):
 243                 /* 24 * 0xfa / 3 / 2 ^ 1 */
 244                 pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xfa) |
 245                         INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(1);
 246                 break;
 247         case MHZ(1200):
 248                 /* 24 * 0x12c / 3 / 2 ^ 1 */
 249                 pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0x12c) |
 250                         INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(1);
 251                 break;
 252         case MHZ(1400):
 253                 /* 24 * 0x15e / 3 / 2 ^ 1 */
 254                 pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0x15e) |
 255                         INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(1);
 256                 break;
 257         case MHZ(1500):
 258                 /* 24 * 0x177 / 3 / 2 ^ 1 */
 259                 pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0x177) |
 260                         INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(1);
 261                 break;
 262         case MHZ(1600):
 263                 /* 24 * 0xc8 / 3 / 2 ^ 0 */
 264                 pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xc8) |
 265                         INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(0);
 266                 break;
 267         case MHZ(1800):
 268                 /* 24 * 0xe1 / 3 / 2 ^ 0 */
 269                 pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xe1) |
 270                         INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(0);
 271                 break;
 272         case MHZ(2000):
 273                 /* 24 * 0xfa / 3 / 2 ^ 0 */
 274                 pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xfa) |
 275                         INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(0);
 276                 break;
 277         default:
 278                 return -EINVAL;
 279         };
 280         /* Bypass clock and set lock to pll output lock */
 281         setbits_le32(pll_gnrl_ctl, INTPLL_BYPASS_MASK | INTPLL_LOCK_SEL_MASK);
 282         /* Enable reset */
 283         clrbits_le32(pll_gnrl_ctl, INTPLL_RST_MASK);
 284         /* Configure */
 285         writel(pll_div_ctl_val, pll_div_ctl);
 286
 287         __udelay(100);
 288
 289         /* Disable reset */
 290         setbits_le32(pll_gnrl_ctl, INTPLL_RST_MASK);
 291         /* Wait Lock */
 292         while (!(readl(pll_gnrl_ctl) & INTPLL_LOCK_MASK))
 293                 ;
 294         /* Clear bypass */
 295         clrbits_le32(pll_gnrl_ctl, INTPLL_BYPASS_MASK);
 296         setbits_le32(pll_gnrl_ctl, pll_clke_masks);
 297
 298         return 0;
 299 }
 300
 301 void init_uart_clk(u32 index)
 302 {
 303         /*
 304          * set uart clock root
 305          * 24M OSC
 306          */
 307         switch (index) {
 308         case 0:
 309                 clock_enable(CCGR_UART1, 0);
 310                 clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON |
 311                                      CLK_ROOT_SOURCE_SEL(0));
 312                 clock_enable(CCGR_UART1, 1);
 313                 return;
 314         case 1:
 315                 clock_enable(CCGR_UART2, 0);
 316                 clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON |
 317                                      CLK_ROOT_SOURCE_SEL(0));
 318                 clock_enable(CCGR_UART2, 1);
 319                 return;
 320         case 2:
 321                 clock_enable(CCGR_UART3, 0);
 322                 clock_set_target_val(UART3_CLK_ROOT, CLK_ROOT_ON |
 323                                      CLK_ROOT_SOURCE_SEL(0));
 324                 clock_enable(CCGR_UART3, 1);
 325                 return;
 326         case 3:
 327                 clock_enable(CCGR_UART4, 0);
 328                 clock_set_target_val(UART4_CLK_ROOT, CLK_ROOT_ON |
 329                                      CLK_ROOT_SOURCE_SEL(0));
 330                 clock_enable(CCGR_UART4, 1);
 331                 return;
 332         default:
 333                 printf("Invalid uart index\n");
 334                 return;
 335         }
 336 }
 337
 338 void init_wdog_clk(void)
 339 {
 340         clock_enable(CCGR_WDOG1, 0);
 341         clock_enable(CCGR_WDOG2, 0);
 342         clock_enable(CCGR_WDOG3, 0);
 343         clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
 344                              CLK_ROOT_SOURCE_SEL(0));
 345         clock_enable(CCGR_WDOG1, 1);
 346         clock_enable(CCGR_WDOG2, 1);
 347         clock_enable(CCGR_WDOG3, 1);
 348 }
 349
 350 void init_clk_usdhc(u32 index)
 351 {
 352         /*
 353          * set usdhc clock root
 354          * sys pll1 400M
 355          */
 356         switch (index) {
 357         case 0:
 358                 clock_enable(CCGR_USDHC1, 0);
 359                 clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON |
 360                                      CLK_ROOT_SOURCE_SEL(1));
 361                 clock_enable(CCGR_USDHC1, 1);
 362                 return;
 363         case 1:
 364                 clock_enable(CCGR_USDHC2, 0);
 365                 clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON |
 366                                      CLK_ROOT_SOURCE_SEL(1));
 367                 clock_enable(CCGR_USDHC2, 1);
 368                 return;
 369         case 2:
 370                 clock_enable(CCGR_USDHC3, 0);
 371                 clock_set_target_val(USDHC3_CLK_ROOT, CLK_ROOT_ON |
 372                                      CLK_ROOT_SOURCE_SEL(1));
 373                 clock_enable(CCGR_USDHC3, 1);
 374                 return;
 375         default:
 376                 printf("Invalid usdhc index\n");
 377                 return;
 378         }
 379 }
 380
 381 void init_clk_ecspi(u32 index)
 382 {
 383         switch (index) {
 384         case 0:
 385                 clock_enable(CCGR_ECSPI1, 0);
 386                 clock_set_target_val(ECSPI1_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0));
 387                 clock_enable(CCGR_ECSPI1, 1);
 388                 return;
 389         case 1:
 390                 clock_enable(CCGR_ECSPI2, 0);
 391                 clock_set_target_val(ECSPI2_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0));
 392                 clock_enable(CCGR_ECSPI2, 1);
 393                 return;
 394         case 2:
 395                 clock_enable(CCGR_ECSPI3, 0);
 396                 clock_set_target_val(ECSPI3_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0));
 397                 clock_enable(CCGR_ECSPI3, 1);
 398                 return;
 399         default:
 400                 printf("Invalid ecspi index\n");
 401                 return;
 402         }
 403 }
 404
 405 void init_nand_clk(void)
 406 {
 407         /*
 408          * set rawnand root
 409          * sys pll1 400M
 410          */
 411         clock_enable(CCGR_RAWNAND, 0);
 412         clock_set_target_val(NAND_CLK_ROOT, CLK_ROOT_ON |
 413                 CLK_ROOT_SOURCE_SEL(3) | CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4)); /* 100M */
 414         clock_enable(CCGR_RAWNAND, 1);
 415 }
 416
 417 int clock_init(void)
 418 {
 419         u32 val_cfg0;
 420
 421         /*
 422          * The gate is not exported to clk tree, so configure them here.
 423          * According to ANAMIX SPEC
 424          * sys pll1 fixed at 800MHz
 425          * sys pll2 fixed at 1GHz
 426          * Here we only enable the outputs.
 427          */
 428         val_cfg0 = readl(&ana_pll->sys_pll1_gnrl_ctl);
 429         val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK |
 430                 INTPLL_DIV3_CLKE_MASK | INTPLL_DIV4_CLKE_MASK |
 431                 INTPLL_DIV5_CLKE_MASK | INTPLL_DIV6_CLKE_MASK |
 432                 INTPLL_DIV8_CLKE_MASK | INTPLL_DIV10_CLKE_MASK |
 433                 INTPLL_DIV20_CLKE_MASK;
 434         writel(val_cfg0, &ana_pll->sys_pll1_gnrl_ctl);
 435
 436         val_cfg0 = readl(&ana_pll->sys_pll2_gnrl_ctl);
 437         val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK |
 438                 INTPLL_DIV3_CLKE_MASK | INTPLL_DIV4_CLKE_MASK |
 439                 INTPLL_DIV5_CLKE_MASK | INTPLL_DIV6_CLKE_MASK |
 440                 INTPLL_DIV8_CLKE_MASK | INTPLL_DIV10_CLKE_MASK |
 441                 INTPLL_DIV20_CLKE_MASK;
 442         writel(val_cfg0, &ana_pll->sys_pll2_gnrl_ctl);
 443
 444         /* Configure ARM at 1.2GHz */
 445         clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
 446                              CLK_ROOT_SOURCE_SEL(2));
 447
 448         intpll_configure(ANATOP_ARM_PLL, MHZ(1200));
 449
 450         /* Bypass CCM A53 ROOT, Switch to ARM PLL -> MUX-> CPU */
 451         clock_set_target_val(CORE_SEL_CFG, CLK_ROOT_SOURCE_SEL(1));
 452
 453         if (is_imx8mn() || is_imx8mp())
 454                 intpll_configure(ANATOP_SYSTEM_PLL3, MHZ(600));
 455         else
 456                 intpll_configure(ANATOP_SYSTEM_PLL3, MHZ(750));
 457
 458 #ifdef CONFIG_IMX8MP
 459         /* 8MP ROM already set NOC to 800Mhz, only need to configure NOC_IO clk to 600Mhz */
 460         /* 8MP ROM already set GIC to 400Mhz, system_pll1_800m with div = 2 */
 461         clock_set_target_val(NOC_IO_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(2));
 462 #else
 463         clock_set_target_val(NOC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(2));
 464
 465         /* config GIC to sys_pll2_100m */
 466         clock_enable(CCGR_GIC, 0);
 467         clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON |
 468                              CLK_ROOT_SOURCE_SEL(3));
 469         clock_enable(CCGR_GIC, 1);
 470 #endif
 471
 472         clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON |
 473                              CLK_ROOT_SOURCE_SEL(1));
 474
 475         clock_enable(CCGR_DDR1, 0);
 476         clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
 477                              CLK_ROOT_SOURCE_SEL(1));
 478         clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
 479                              CLK_ROOT_SOURCE_SEL(1));
 480         clock_enable(CCGR_DDR1, 1);
 481
 482         init_wdog_clk();
 483
 484         clock_enable(CCGR_TEMP_SENSOR, 1);
 485
 486         clock_enable(CCGR_SEC_DEBUG, 1);
 487
 488         return 0;
 489 };
 490
 491 u32 imx_get_uartclk(void)
 492 {
 493         return 24000000U;
 494 }
 495
 496 static u32 decode_intpll(enum clk_root_src intpll)
 497 {
 498         u32 pll_gnrl_ctl, pll_div_ctl, pll_clke_mask;
 499         u32 main_div, pre_div, post_div, div;
 500         u64 freq;
 501
 502         switch (intpll) {
 503         case ARM_PLL_CLK:
 504                 pll_gnrl_ctl = readl(&ana_pll->arm_pll_gnrl_ctl);
 505                 pll_div_ctl = readl(&ana_pll->arm_pll_div_ctl);
 506                 break;
 507         case GPU_PLL_CLK:
 508                 pll_gnrl_ctl = readl(&ana_pll->gpu_pll_gnrl_ctl);
 509                 pll_div_ctl = readl(&ana_pll->gpu_pll_div_ctl);
 510                 break;
 511         case VPU_PLL_CLK:
 512                 pll_gnrl_ctl = readl(&ana_pll->vpu_pll_gnrl_ctl);
 513                 pll_div_ctl = readl(&ana_pll->vpu_pll_div_ctl);
 514                 break;
 515         case SYSTEM_PLL1_800M_CLK:
 516         case SYSTEM_PLL1_400M_CLK:
 517         case SYSTEM_PLL1_266M_CLK:
 518         case SYSTEM_PLL1_200M_CLK:
 519         case SYSTEM_PLL1_160M_CLK:
 520         case SYSTEM_PLL1_133M_CLK:
 521         case SYSTEM_PLL1_100M_CLK:
 522         case SYSTEM_PLL1_80M_CLK:
 523         case SYSTEM_PLL1_40M_CLK:
 524                 pll_gnrl_ctl = readl(&ana_pll->sys_pll1_gnrl_ctl);
 525                 pll_div_ctl = readl(&ana_pll->sys_pll1_div_ctl);
 526                 break;
 527         case SYSTEM_PLL2_1000M_CLK:
 528         case SYSTEM_PLL2_500M_CLK:
 529         case SYSTEM_PLL2_333M_CLK:
 530         case SYSTEM_PLL2_250M_CLK:
 531         case SYSTEM_PLL2_200M_CLK:
 532         case SYSTEM_PLL2_166M_CLK:
 533         case SYSTEM_PLL2_125M_CLK:
 534         case SYSTEM_PLL2_100M_CLK:
 535         case SYSTEM_PLL2_50M_CLK:
 536                 pll_gnrl_ctl = readl(&ana_pll->sys_pll2_gnrl_ctl);
 537                 pll_div_ctl = readl(&ana_pll->sys_pll2_div_ctl);
 538                 break;
 539         case SYSTEM_PLL3_CLK:
 540                 pll_gnrl_ctl = readl(&ana_pll->sys_pll3_gnrl_ctl);
 541                 pll_div_ctl = readl(&ana_pll->sys_pll3_div_ctl);
 542                 break;
 543         default:
 544                 return -EINVAL;
 545         }
 546
 547         /* Only support SYS_XTAL 24M, PAD_CLK not take into consideration */
 548         if ((pll_gnrl_ctl & INTPLL_REF_CLK_SEL_MASK) != 0)
 549                 return 0;
 550
 551         if ((pll_gnrl_ctl & INTPLL_RST_MASK) == 0)
 552                 return 0;
 553
 554         /*
 555          * When BYPASS is equal to 1, PLL enters the bypass mode
 556          * regardless of the values of RESETB
 557          */
 558         if (pll_gnrl_ctl & INTPLL_BYPASS_MASK)
 559                 return 24000000u;
 560
 561         if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) {
 562                 puts("pll not locked\n");
 563                 return 0;
 564         }
 565
 566         switch (intpll) {
 567         case ARM_PLL_CLK:
 568         case GPU_PLL_CLK:
 569         case VPU_PLL_CLK:
 570         case SYSTEM_PLL3_CLK:
 571         case SYSTEM_PLL1_800M_CLK:
 572         case SYSTEM_PLL2_1000M_CLK:
 573                 pll_clke_mask = INTPLL_CLKE_MASK;
 574                 div = 1;
 575                 break;
 576
 577         case SYSTEM_PLL1_400M_CLK:
 578         case SYSTEM_PLL2_500M_CLK:
 579                 pll_clke_mask = INTPLL_DIV2_CLKE_MASK;
 580                 div = 2;
 581                 break;
 582
 583         case SYSTEM_PLL1_266M_CLK:
 584         case SYSTEM_PLL2_333M_CLK:
 585                 pll_clke_mask = INTPLL_DIV3_CLKE_MASK;
 586                 div = 3;
 587                 break;
 588
 589         case SYSTEM_PLL1_200M_CLK:
 590         case SYSTEM_PLL2_250M_CLK:
 591                 pll_clke_mask = INTPLL_DIV4_CLKE_MASK;
 592                 div = 4;
 593                 break;
 594
 595         case SYSTEM_PLL1_160M_CLK:
 596         case SYSTEM_PLL2_200M_CLK:
 597                 pll_clke_mask = INTPLL_DIV5_CLKE_MASK;
 598                 div = 5;
 599                 break;
 600
 601         case SYSTEM_PLL1_133M_CLK:
 602         case SYSTEM_PLL2_166M_CLK:
 603                 pll_clke_mask = INTPLL_DIV6_CLKE_MASK;
 604                 div = 6;
 605                 break;
 606
 607         case SYSTEM_PLL1_100M_CLK:
 608         case SYSTEM_PLL2_125M_CLK:
 609                 pll_clke_mask = INTPLL_DIV8_CLKE_MASK;
 610                 div = 8;
 611                 break;
 612
 613         case SYSTEM_PLL1_80M_CLK:
 614         case SYSTEM_PLL2_100M_CLK:
 615                 pll_clke_mask = INTPLL_DIV10_CLKE_MASK;
 616                 div = 10;
 617                 break;
 618
 619         case SYSTEM_PLL1_40M_CLK:
 620         case SYSTEM_PLL2_50M_CLK:
 621                 pll_clke_mask = INTPLL_DIV20_CLKE_MASK;
 622                 div = 20;
 623                 break;
 624         default:
 625                 return -EINVAL;
 626         }
 627
 628         if ((pll_gnrl_ctl & pll_clke_mask) == 0)
 629                 return 0;
 630
 631         main_div = (pll_div_ctl & INTPLL_MAIN_DIV_MASK) >>
 632                 INTPLL_MAIN_DIV_SHIFT;
 633         pre_div = (pll_div_ctl & INTPLL_PRE_DIV_MASK) >>
 634                 INTPLL_PRE_DIV_SHIFT;
 635         post_div = (pll_div_ctl & INTPLL_POST_DIV_MASK) >>
 636                 INTPLL_POST_DIV_SHIFT;
 637
 638         /* FFVCO = (m * FFIN) / p, FFOUT = (m * FFIN) / (p * 2^s) */
 639         freq = 24000000ULL * main_div;
 640         return lldiv(freq, pre_div * (1 << post_div) * div);
 641 }
 642
 643 static u32 decode_fracpll(enum clk_root_src frac_pll)
 644 {
 645         u32 pll_gnrl_ctl, pll_fdiv_ctl0, pll_fdiv_ctl1;
 646         u32 main_div, pre_div, post_div, k;
 647
 648         switch (frac_pll) {
 649         case DRAM_PLL1_CLK:
 650                 pll_gnrl_ctl = readl(&ana_pll->dram_pll_gnrl_ctl);
 651                 pll_fdiv_ctl0 = readl(&ana_pll->dram_pll_fdiv_ctl0);
 652                 pll_fdiv_ctl1 = readl(&ana_pll->dram_pll_fdiv_ctl1);
 653                 break;
 654         case AUDIO_PLL1_CLK:
 655                 pll_gnrl_ctl = readl(&ana_pll->audio_pll1_gnrl_ctl);
 656                 pll_fdiv_ctl0 = readl(&ana_pll->audio_pll1_fdiv_ctl0);
 657                 pll_fdiv_ctl1 = readl(&ana_pll->audio_pll1_fdiv_ctl1);
 658                 break;
 659         case AUDIO_PLL2_CLK:
 660                 pll_gnrl_ctl = readl(&ana_pll->audio_pll2_gnrl_ctl);
 661                 pll_fdiv_ctl0 = readl(&ana_pll->audio_pll2_fdiv_ctl0);
 662                 pll_fdiv_ctl1 = readl(&ana_pll->audio_pll2_fdiv_ctl1);
 663                 break;
 664         case VIDEO_PLL_CLK:
 665                 pll_gnrl_ctl = readl(&ana_pll->video_pll1_gnrl_ctl);
 666                 pll_fdiv_ctl0 = readl(&ana_pll->video_pll1_fdiv_ctl0);
 667                 pll_fdiv_ctl1 = readl(&ana_pll->video_pll1_fdiv_ctl1);
 668                 break;
 669         default:
 670                 printf("Unsupported clk_root_src %d\n", frac_pll);
 671                 return 0;
 672         }
 673
 674         /* Only support SYS_XTAL 24M, PAD_CLK not take into consideration */
 675         if ((pll_gnrl_ctl & GENMASK(1, 0)) != 0)
 676                 return 0;
 677
 678         if ((pll_gnrl_ctl & RST_MASK) == 0)
 679                 return 0;
 680         /*
 681          * When BYPASS is equal to 1, PLL enters the bypass mode
 682          * regardless of the values of RESETB
 683          */
 684         if (pll_gnrl_ctl & BYPASS_MASK)
 685                 return 24000000u;
 686
 687         if (!(pll_gnrl_ctl & LOCK_STATUS)) {
 688                 puts("pll not locked\n");
 689                 return 0;
 690         }
 691
 692         if (!(pll_gnrl_ctl & CLKE_MASK))
 693                 return 0;
 694
 695         main_div = (pll_fdiv_ctl0 & MDIV_MASK) >>
 696                 MDIV_SHIFT;
 697         pre_div = (pll_fdiv_ctl0 & PDIV_MASK) >>
 698                 PDIV_SHIFT;
 699         post_div = (pll_fdiv_ctl0 & SDIV_MASK) >>
 700                 SDIV_SHIFT;
 701
 702         k = pll_fdiv_ctl1 & KDIV_MASK;
 703
 704         return lldiv((main_div * 65536 + k) * 24000000ULL,
 705                      65536 * pre_div * (1 << post_div));
 706 }
 707
 708 static u32 get_root_src_clk(enum clk_root_src root_src)
 709 {
 710         switch (root_src) {
 711         case OSC_24M_CLK:
 712                 return 24000000u;
 713         case OSC_HDMI_CLK:
 714                 return 26000000u;
 715         case OSC_32K_CLK:
 716                 return 32000u;
 717         case ARM_PLL_CLK:
 718         case GPU_PLL_CLK:
 719         case VPU_PLL_CLK:
 720         case SYSTEM_PLL1_800M_CLK:
 721         case SYSTEM_PLL1_400M_CLK:
 722         case SYSTEM_PLL1_266M_CLK:
 723         case SYSTEM_PLL1_200M_CLK:
 724         case SYSTEM_PLL1_160M_CLK:
 725         case SYSTEM_PLL1_133M_CLK:
 726         case SYSTEM_PLL1_100M_CLK:
 727         case SYSTEM_PLL1_80M_CLK:
 728         case SYSTEM_PLL1_40M_CLK:
 729         case SYSTEM_PLL2_1000M_CLK:
 730         case SYSTEM_PLL2_500M_CLK:
 731         case SYSTEM_PLL2_333M_CLK:
 732         case SYSTEM_PLL2_250M_CLK:
 733         case SYSTEM_PLL2_200M_CLK:
 734         case SYSTEM_PLL2_166M_CLK:
 735         case SYSTEM_PLL2_125M_CLK:
 736         case SYSTEM_PLL2_100M_CLK:
 737         case SYSTEM_PLL2_50M_CLK:
 738         case SYSTEM_PLL3_CLK:
 739                 return decode_intpll(root_src);
 740         case DRAM_PLL1_CLK:
 741         case AUDIO_PLL1_CLK:
 742         case AUDIO_PLL2_CLK:
 743         case VIDEO_PLL_CLK:
 744                 return decode_fracpll(root_src);
 745         case ARM_A53_ALT_CLK:
 746                 return get_root_clk(ARM_A53_CLK_ROOT);
 747         default:
 748                 return 0;
 749         }
 750
 751         return 0;
 752 }
 753
 754 static u32 get_root_clk(enum clk_root_index clock_id)
 755 {
 756         enum clk_root_src root_src;
 757         u32 post_podf, pre_podf, root_src_clk;
 758
 759         if (clock_root_enabled(clock_id) <= 0)
 760                 return 0;
 761
 762         if (clock_get_prediv(clock_id, &pre_podf) < 0)
 763                 return 0;
 764
 765         if (clock_get_postdiv(clock_id, &post_podf) < 0)
 766                 return 0;
 767
 768         if (clock_get_src(clock_id, &root_src) < 0)
 769                 return 0;
 770
 771         root_src_clk = get_root_src_clk(root_src);
 772
 773         return root_src_clk / (post_podf + 1) / (pre_podf + 1);
 774 }
 775
 776 u32 get_arm_core_clk(void)
 777 {
 778         enum clk_root_src root_src;
 779         u32 root_src_clk;
 780
 781         if (clock_get_src(CORE_SEL_CFG, &root_src) < 0)
 782                 return 0;
 783
 784         root_src_clk = get_root_src_clk(root_src);
 785
 786         return root_src_clk;
 787 }
 788
 789 u32 mxc_get_clock(enum mxc_clock clk)
 790 {
 791         u32 val;
 792
 793         switch (clk) {
 794         case MXC_ARM_CLK:
 795                 return get_arm_core_clk();
 796         case MXC_IPG_CLK:
 797                 clock_get_target_val(IPG_CLK_ROOT, &val);
 798                 val = val & 0x3;
 799                 return get_root_clk(AHB_CLK_ROOT) / 2 / (val + 1);
 800         case MXC_CSPI_CLK:
 801                 return get_root_clk(ECSPI1_CLK_ROOT);
 802         case MXC_ESDHC_CLK:
 803                 return get_root_clk(USDHC1_CLK_ROOT);
 804         case MXC_ESDHC2_CLK:
 805                 return get_root_clk(USDHC2_CLK_ROOT);
 806         case MXC_ESDHC3_CLK:
 807                 return get_root_clk(USDHC3_CLK_ROOT);
 808         case MXC_I2C_CLK:
 809                 return get_root_clk(I2C1_CLK_ROOT);
 810         case MXC_UART_CLK:
 811                 return get_root_clk(UART1_CLK_ROOT);
 812         case MXC_QSPI_CLK:
 813                 return get_root_clk(QSPI_CLK_ROOT);
 814         default:
 815                 printf("Unsupported mxc_clock %d\n", clk);
 816                 break;
 817         }
 818
 819         return 0;
 820 }
 821
 822 #ifdef CONFIG_DWC_ETH_QOS
 823 int set_clk_eqos(enum enet_freq type)
 824 {
 825         u32 target;
 826         u32 enet1_ref;
 827
 828         switch (type) {
 829         case ENET_125MHZ:
 830                 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
 831                 break;
 832         case ENET_50MHZ:
 833                 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
 834                 break;
 835         case ENET_25MHZ:
 836                 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
 837                 break;
 838         default:
 839                 return -EINVAL;
 840         }
 841
 842         /* disable the clock first */
 843         clock_enable(CCGR_QOS_ETHENET, 0);
 844         clock_enable(CCGR_SDMA2, 0);
 845
 846         /* set enet axi clock 266Mhz */
 847         target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
 848                  CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
 849                  CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
 850         clock_set_target_val(ENET_AXI_CLK_ROOT, target);
 851
 852         target = CLK_ROOT_ON | enet1_ref |
 853                  CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
 854                  CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
 855         clock_set_target_val(ENET_QOS_CLK_ROOT, target);
 856
 857         target = CLK_ROOT_ON |
 858                 ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
 859                 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
 860                 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
 861         clock_set_target_val(ENET_QOS_TIMER_CLK_ROOT, target);
 862
 863         /* enable clock */
 864         clock_enable(CCGR_QOS_ETHENET, 1);
 865         clock_enable(CCGR_SDMA2, 1);
 866
 867         return 0;
 868 }
 869
 870 int imx_eqos_txclk_set_rate(ulong rate)
 871 {
 872         u32 val;
 873         u32 eqos_post_div;
 874
 875         /* disable the clock first */
 876         clock_enable(CCGR_QOS_ETHENET, 0);
 877         clock_enable(CCGR_SDMA2, 0);
 878
 879         switch (rate) {
 880         case 125000000:
 881                 eqos_post_div = 1;
 882                 break;
 883         case 25000000:
 884                 eqos_post_div = 125000000 / 25000000;
 885                 break;
 886         case 2500000:
 887                 eqos_post_div = 125000000 / 2500000;
 888                 break;
 889         default:
 890                 return -EINVAL;
 891         }
 892
 893         clock_get_target_val(ENET_QOS_CLK_ROOT, &val);
 894         val &= ~(CLK_ROOT_PRE_DIV_MASK | CLK_ROOT_POST_DIV_MASK);
 895         val |= CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
 896                CLK_ROOT_POST_DIV(eqos_post_div - 1);
 897         clock_set_target_val(ENET_QOS_CLK_ROOT, val);
 898
 899         /* enable clock */
 900         clock_enable(CCGR_QOS_ETHENET, 1);
 901         clock_enable(CCGR_SDMA2, 1);
 902
 903         return 0;
 904 }
 905
 906 u32 imx_get_eqos_csr_clk(void)
 907 {
 908         return get_root_clk(ENET_AXI_CLK_ROOT);
 909 }
 910 #endif
 911
 912 #ifdef CONFIG_FEC_MXC
 913 int set_clk_enet(enum enet_freq type)
 914 {
 915         u32 target;
 916         u32 enet1_ref;
 917
 918         switch (type) {
 919         case ENET_125MHZ:
 920                 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
 921                 break;
 922         case ENET_50MHZ:
 923                 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
 924                 break;
 925         case ENET_25MHZ:
 926                 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
 927                 break;
 928         default:
 929                 return -EINVAL;
 930         }
 931
 932         /* disable the clock first */
 933         clock_enable(CCGR_ENET1, 0);
 934         clock_enable(CCGR_SIM_ENET, 0);
 935
 936         /* set enet axi clock 266Mhz */
 937         target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
 938                  CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
 939                  CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
 940         clock_set_target_val(ENET_AXI_CLK_ROOT, target);
 941
 942         target = CLK_ROOT_ON | enet1_ref |
 943                  CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
 944                  CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
 945         clock_set_target_val(ENET_REF_CLK_ROOT, target);
 946
 947         target = CLK_ROOT_ON |
 948                 ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
 949                 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
 950                 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
 951         clock_set_target_val(ENET_TIMER_CLK_ROOT, target);
 952
 953         /* enable clock */
 954         clock_enable(CCGR_SIM_ENET, 1);
 955         clock_enable(CCGR_ENET1, 1);
 956
 957         return 0;
 958 }
 959 #endif