arch/arm/dts/ast2500-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <dt-bindings/clock/aspeed-clock.h>
   3 #include <dt-bindings/reset/ast2500-reset.h>
   4
   5 #include "ast2500.dtsi"
   6
   7 / {
   8         scu: clock-controller@1e6e2000 {
   9                 compatible = "aspeed,ast2500-scu";
  10                 reg = <0x1e6e2000 0x1000>;
  11                 bootph-all;
  12                 #clock-cells = <1>;
  13                 #reset-cells = <1>;
  14         };
  15
  16         rst: reset-controller {
  17                 bootph-all;
  18                 compatible = "aspeed,ast2500-reset";
  19                 #reset-cells = <1>;
  20         };
  21
  22         sdrammc: sdrammc@1e6e0000 {
  23                 bootph-all;
  24                 compatible = "aspeed,ast2500-sdrammc";
  25                 reg = <0x1e6e0000 0x174
  26                         0x1e6e0200 0x1d4 >;
  27                 #reset-cells = <1>;
  28                 clocks = <&scu ASPEED_CLK_MPLL>;
  29                 resets = <&rst ASPEED_RESET_SDRAM>;
  30         };
  31 };
  32
  33 &uart1 {
  34         clocks = <&scu ASPEED_CLK_GATE_UART1CLK>;
  35 };
  36
  37 &uart2 {
  38         clocks = <&scu ASPEED_CLK_GATE_UART2CLK>;
  39 };
  40
  41 &uart3 {
  42         clocks = <&scu ASPEED_CLK_GATE_UART3CLK>;
  43 };
  44
  45 &uart4 {
  46         clocks = <&scu ASPEED_CLK_GATE_UART4CLK>;
  47 };
  48
  49 &uart5 {
  50         clocks = <&scu ASPEED_CLK_GATE_UART5CLK>;
  51 };
  52
  53 &timer {
  54         bootph-all;
  55 };
  56
  57 &mac0 {
  58         clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>, <&scu ASPEED_CLK_D2PLL>;
  59 };
  60
  61 &mac1 {
  62         clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>, <&scu ASPEED_CLK_D2PLL>;
  63 };