1 // SPDX-License-Identifier: GPL-2.0+
3 * Image manipulator for Marvell SoCs
4 * supports Kirkwood, Dove, Armada 370, Armada XP, Armada 375, Armada 38x and
7 * (C) Copyright 2013 Thomas Petazzoni
13 #define OPENSSL_API_COMPAT 0x10101000L
15 #include "imagetool.h"
22 #include <openssl/bn.h>
23 #include <openssl/rsa.h>
24 #include <openssl/pem.h>
25 #include <openssl/err.h>
26 #include <openssl/evp.h>
28 #if OPENSSL_VERSION_NUMBER < 0x10100000L || \
29 (defined(LIBRESSL_VERSION_NUMBER) && LIBRESSL_VERSION_NUMBER < 0x2070000fL)
30 static void RSA_get0_key(const RSA *r,
31 const BIGNUM **n, const BIGNUM **e, const BIGNUM **d)
41 #elif !defined(LIBRESSL_VERSION_NUMBER)
42 void EVP_MD_CTX_cleanup(EVP_MD_CTX *ctx)
44 EVP_MD_CTX_reset(ctx);
48 /* fls - find last (most-significant) bit set in 4-bit integer */
49 static inline int fls4(int num)
63 static struct image_cfg_element *image_cfg;
65 static int verbose_mode;
79 struct boot_mode boot_modes[] = {
80 { IBR_HDR_I2C_ID, "i2c" },
81 { IBR_HDR_SPI_ID, "spi" },
82 { IBR_HDR_NAND_ID, "nand" },
83 { IBR_HDR_SATA_ID, "sata" },
84 { IBR_HDR_PEX_ID, "pex" },
85 { IBR_HDR_UART_ID, "uart" },
86 { IBR_HDR_SDIO_ID, "sdio" },
90 struct nand_ecc_mode {
95 struct nand_ecc_mode nand_ecc_modes[] = {
96 { IBR_HDR_ECC_DEFAULT, "default" },
97 { IBR_HDR_ECC_FORCED_HAMMING, "hamming" },
98 { IBR_HDR_ECC_FORCED_RS, "rs" },
99 { IBR_HDR_ECC_DISABLED, "disabled" },
103 /* Used to identify an undefined execution or destination address */
104 #define ADDR_INVALID ((uint32_t)-1)
106 #define BINARY_MAX_ARGS 255
108 /* In-memory representation of a line of the configuration file */
110 enum image_cfg_type {
111 IMAGE_CFG_VERSION = 0x1,
115 IMAGE_CFG_NAND_BLKSZ,
116 IMAGE_CFG_NAND_BADBLK_LOCATION,
117 IMAGE_CFG_NAND_ECC_MODE,
118 IMAGE_CFG_NAND_PAGESZ,
122 IMAGE_CFG_DATA_DELAY,
130 IMAGE_CFG_JTAG_DELAY,
133 IMAGE_CFG_SEC_COMMON_IMG,
134 IMAGE_CFG_SEC_SPECIALIZED_IMG,
135 IMAGE_CFG_SEC_BOOT_DEV,
136 IMAGE_CFG_SEC_FUSE_DUMP,
141 static const char * const id_strs[] = {
142 [IMAGE_CFG_VERSION] = "VERSION",
143 [IMAGE_CFG_BOOT_FROM] = "BOOT_FROM",
144 [IMAGE_CFG_DEST_ADDR] = "DEST_ADDR",
145 [IMAGE_CFG_EXEC_ADDR] = "EXEC_ADDR",
146 [IMAGE_CFG_NAND_BLKSZ] = "NAND_BLKSZ",
147 [IMAGE_CFG_NAND_BADBLK_LOCATION] = "NAND_BADBLK_LOCATION",
148 [IMAGE_CFG_NAND_ECC_MODE] = "NAND_ECC_MODE",
149 [IMAGE_CFG_NAND_PAGESZ] = "NAND_PAGE_SIZE",
150 [IMAGE_CFG_CPU] = "CPU",
151 [IMAGE_CFG_BINARY] = "BINARY",
152 [IMAGE_CFG_DATA] = "DATA",
153 [IMAGE_CFG_DATA_DELAY] = "DATA_DELAY",
154 [IMAGE_CFG_BAUDRATE] = "BAUDRATE",
155 [IMAGE_CFG_UART_PORT] = "UART_PORT",
156 [IMAGE_CFG_UART_MPP] = "UART_MPP",
157 [IMAGE_CFG_DEBUG] = "DEBUG",
158 [IMAGE_CFG_KAK] = "KAK",
159 [IMAGE_CFG_CSK] = "CSK",
160 [IMAGE_CFG_CSK_INDEX] = "CSK_INDEX",
161 [IMAGE_CFG_JTAG_DELAY] = "JTAG_DELAY",
162 [IMAGE_CFG_BOX_ID] = "BOX_ID",
163 [IMAGE_CFG_FLASH_ID] = "FLASH_ID",
164 [IMAGE_CFG_SEC_COMMON_IMG] = "SEC_COMMON_IMG",
165 [IMAGE_CFG_SEC_SPECIALIZED_IMG] = "SEC_SPECIALIZED_IMG",
166 [IMAGE_CFG_SEC_BOOT_DEV] = "SEC_BOOT_DEV",
167 [IMAGE_CFG_SEC_FUSE_DUMP] = "SEC_FUSE_DUMP"
170 struct image_cfg_element {
171 enum image_cfg_type type;
173 unsigned int version;
174 unsigned int cpu_sheeva;
175 unsigned int bootfrom;
178 unsigned int loadaddr;
179 unsigned int args[BINARY_MAX_ARGS];
182 unsigned int dstaddr;
183 unsigned int execaddr;
184 unsigned int nandblksz;
185 unsigned int nandbadblklocation;
186 unsigned int nandeccmode;
187 unsigned int nandpagesz;
188 struct ext_hdr_v0_reg regdata;
189 unsigned int regdata_delay;
190 unsigned int baudrate;
191 unsigned int uart_port;
192 unsigned int uart_mpp;
194 const char *key_name;
199 bool sec_specialized_img;
200 unsigned int sec_boot_dev;
205 #define IMAGE_CFG_ELEMENT_MAX 256
208 * Utility functions to manipulate boot mode and ecc modes (convert
209 * them back and forth between description strings and the
210 * corresponding numerical identifiers).
213 static const char *image_boot_mode_name(unsigned int id)
217 for (i = 0; boot_modes[i].name; i++)
218 if (boot_modes[i].id == id)
219 return boot_modes[i].name;
223 static int image_boot_mode_id(const char *boot_mode_name)
227 for (i = 0; boot_modes[i].name; i++)
228 if (!strcmp(boot_modes[i].name, boot_mode_name))
229 return boot_modes[i].id;
234 static const char *image_nand_ecc_mode_name(unsigned int id)
238 for (i = 0; nand_ecc_modes[i].name; i++)
239 if (nand_ecc_modes[i].id == id)
240 return nand_ecc_modes[i].name;
245 static int image_nand_ecc_mode_id(const char *nand_ecc_mode_name)
249 for (i = 0; nand_ecc_modes[i].name; i++)
250 if (!strcmp(nand_ecc_modes[i].name, nand_ecc_mode_name))
251 return nand_ecc_modes[i].id;
255 static struct image_cfg_element *
256 image_find_option(unsigned int optiontype)
260 for (i = 0; i < cfgn; i++) {
261 if (image_cfg[i].type == optiontype)
262 return &image_cfg[i];
269 image_count_options(unsigned int optiontype)
272 unsigned int count = 0;
274 for (i = 0; i < cfgn; i++)
275 if (image_cfg[i].type == optiontype)
281 static int image_get_csk_index(void)
283 struct image_cfg_element *e;
285 e = image_find_option(IMAGE_CFG_CSK_INDEX);
292 static bool image_get_spezialized_img(void)
294 struct image_cfg_element *e;
296 e = image_find_option(IMAGE_CFG_SEC_SPECIALIZED_IMG);
300 return e->sec_specialized_img;
303 static int image_get_bootfrom(void)
305 struct image_cfg_element *e;
307 e = image_find_option(IMAGE_CFG_BOOT_FROM);
309 /* fallback to SPI if no BOOT_FROM is not provided */
310 return IBR_HDR_SPI_ID;
315 static int image_is_cpu_sheeva(void)
317 struct image_cfg_element *e;
319 e = image_find_option(IMAGE_CFG_CPU);
323 return e->cpu_sheeva;
327 * Compute a 8-bit checksum of a memory area. This algorithm follows
328 * the requirements of the Marvell SoC BootROM specifications.
330 static uint8_t image_checksum8(void *start, uint32_t len)
335 /* check len and return zero checksum if invalid */
348 * Verify checksum over a complete header that includes the checksum field.
349 * Return 1 when OK, otherwise 0.
351 static int main_hdr_checksum_ok(void *hdr)
353 /* Offsets of checksum in v0 and v1 headers are the same */
354 struct main_hdr_v0 *main_hdr = (struct main_hdr_v0 *)hdr;
357 checksum = image_checksum8(hdr, kwbheader_size_for_csum(hdr));
358 /* Calculated checksum includes the header checksum field. Compensate
361 checksum -= main_hdr->checksum;
363 return checksum == main_hdr->checksum;
366 static uint32_t image_checksum32(void *start, uint32_t len)
371 /* check len and return zero checksum if invalid */
375 if (len % sizeof(uint32_t)) {
376 fprintf(stderr, "Length %d is not in multiple of %zu\n",
377 len, sizeof(uint32_t));
384 len -= sizeof(uint32_t);
390 static unsigned int options_to_baudrate(uint8_t options)
392 switch (options & 0x7) {
393 case MAIN_HDR_V1_OPT_BAUD_2400:
395 case MAIN_HDR_V1_OPT_BAUD_4800:
397 case MAIN_HDR_V1_OPT_BAUD_9600:
399 case MAIN_HDR_V1_OPT_BAUD_19200:
401 case MAIN_HDR_V1_OPT_BAUD_38400:
403 case MAIN_HDR_V1_OPT_BAUD_57600:
405 case MAIN_HDR_V1_OPT_BAUD_115200:
407 case MAIN_HDR_V1_OPT_BAUD_DEFAULT:
413 static uint8_t baudrate_to_option(unsigned int baudrate)
417 return MAIN_HDR_V1_OPT_BAUD_2400;
419 return MAIN_HDR_V1_OPT_BAUD_4800;
421 return MAIN_HDR_V1_OPT_BAUD_9600;
423 return MAIN_HDR_V1_OPT_BAUD_19200;
425 return MAIN_HDR_V1_OPT_BAUD_38400;
427 return MAIN_HDR_V1_OPT_BAUD_57600;
429 return MAIN_HDR_V1_OPT_BAUD_115200;
431 return MAIN_HDR_V1_OPT_BAUD_DEFAULT;
435 static void kwb_msg(const char *fmt, ...)
441 vfprintf(stdout, fmt, ap);
446 static int openssl_err(const char *msg)
448 unsigned long ssl_err = ERR_get_error();
450 fprintf(stderr, "%s", msg);
451 fprintf(stderr, ": %s\n",
452 ERR_error_string(ssl_err, 0));
457 static int kwb_load_rsa_key(const char *keydir, const char *name, RSA **p_rsa)
466 snprintf(path, sizeof(path), "%s/%s.key", keydir, name);
467 f = fopen(path, "r");
469 fprintf(stderr, "Couldn't open RSA private key: '%s': %s\n",
470 path, strerror(errno));
474 rsa = PEM_read_RSAPrivateKey(f, 0, NULL, "");
476 openssl_err("Failure reading private key");
486 static int kwb_load_cfg_key(struct image_tool_params *params,
487 unsigned int cfg_option, const char *key_name,
490 struct image_cfg_element *e_key;
496 e_key = image_find_option(cfg_option);
498 fprintf(stderr, "%s not configured\n", key_name);
502 res = kwb_load_rsa_key(params->keydir, e_key->key_name, &key);
504 fprintf(stderr, "Failed to load %s\n", key_name);
513 static int kwb_load_kak(struct image_tool_params *params, RSA **p_kak)
515 return kwb_load_cfg_key(params, IMAGE_CFG_KAK, "KAK", p_kak);
518 static int kwb_load_csk(struct image_tool_params *params, RSA **p_csk)
520 return kwb_load_cfg_key(params, IMAGE_CFG_CSK, "CSK", p_csk);
523 static int kwb_compute_pubkey_hash(struct pubkey_der_v1 *pk,
524 struct hash_v1 *hash)
527 unsigned int key_size;
528 unsigned int hash_size;
531 if (!pk || !hash || pk->key[0] != 0x30 || pk->key[1] != 0x82)
534 key_size = (pk->key[2] << 8) + pk->key[3] + 4;
536 ctx = EVP_MD_CTX_create();
538 return openssl_err("EVP context creation failed");
540 EVP_MD_CTX_init(ctx);
541 if (!EVP_DigestInit(ctx, EVP_sha256())) {
542 ret = openssl_err("Digest setup failed");
546 if (!EVP_DigestUpdate(ctx, pk->key, key_size)) {
547 ret = openssl_err("Hashing data failed");
551 if (!EVP_DigestFinal(ctx, hash->hash, &hash_size)) {
552 ret = openssl_err("Could not obtain hash");
556 EVP_MD_CTX_cleanup(ctx);
559 EVP_MD_CTX_destroy(ctx);
563 static int kwb_import_pubkey(RSA **key, struct pubkey_der_v1 *src, char *keyname)
566 const unsigned char *ptr;
572 rsa = d2i_RSAPublicKey(key, &ptr, sizeof(src->key));
574 openssl_err("error decoding public key");
580 fprintf(stderr, "Failed to decode %s pubkey\n", keyname);
584 static int kwb_export_pubkey(RSA *key, struct pubkey_der_v1 *dst, FILE *hashf,
587 int size_exp, size_mod, size_seq;
588 const BIGNUM *key_e, *key_n;
590 char *errmsg = "Failed to encode %s\n";
592 RSA_get0_key(key, NULL, &key_e, NULL);
593 RSA_get0_key(key, &key_n, NULL, NULL);
595 if (!key || !key_e || !key_n || !dst) {
596 fprintf(stderr, "export pk failed: (%p, %p, %p, %p)",
597 key, key_e, key_n, dst);
598 fprintf(stderr, errmsg, keyname);
603 * According to the specs, the key should be PKCS#1 DER encoded.
604 * But unfortunately the really required encoding seems to be different;
605 * it violates DER...! (But it still conformes to BER.)
606 * (Length always in long form w/ 2 byte length code; no leading zero
607 * when MSB of first byte is set...)
608 * So we cannot use the encoding func provided by OpenSSL and have to
609 * do the encoding manually.
612 size_exp = BN_num_bytes(key_e);
613 size_mod = BN_num_bytes(key_n);
614 size_seq = 4 + size_mod + 4 + size_exp;
616 if (size_mod > 256) {
617 fprintf(stderr, "export pk failed: wrong mod size: %d\n",
619 fprintf(stderr, errmsg, keyname);
623 if (4 + size_seq > sizeof(dst->key)) {
624 fprintf(stderr, "export pk failed: seq too large (%d, %zu)\n",
625 4 + size_seq, sizeof(dst->key));
626 fprintf(stderr, errmsg, keyname);
632 /* PKCS#1 (RFC3447) RSAPublicKey structure */
633 *cur++ = 0x30; /* SEQUENCE */
635 *cur++ = (size_seq >> 8) & 0xFF;
636 *cur++ = size_seq & 0xFF;
638 *cur++ = 0x02; /* INTEGER */
640 *cur++ = (size_mod >> 8) & 0xFF;
641 *cur++ = size_mod & 0xFF;
642 BN_bn2bin(key_n, cur);
645 *cur++ = 0x02; /* INTEGER */
647 *cur++ = (size_exp >> 8) & 0xFF;
648 *cur++ = size_exp & 0xFF;
649 BN_bn2bin(key_e, cur);
652 struct hash_v1 pk_hash;
656 ret = kwb_compute_pubkey_hash(dst, &pk_hash);
658 fprintf(stderr, errmsg, keyname);
662 fprintf(hashf, "SHA256 = ");
663 for (i = 0 ; i < sizeof(pk_hash.hash); ++i)
664 fprintf(hashf, "%02X", pk_hash.hash[i]);
665 fprintf(hashf, "\n");
671 static int kwb_sign(RSA *key, void *data, int datasz, struct sig_v1 *sig,
676 unsigned int sig_size;
680 evp_key = EVP_PKEY_new();
682 return openssl_err("EVP_PKEY object creation failed");
684 if (!EVP_PKEY_set1_RSA(evp_key, key)) {
685 ret = openssl_err("EVP key setup failed");
689 size = EVP_PKEY_size(evp_key);
690 if (size > sizeof(sig->sig)) {
691 fprintf(stderr, "Buffer to small for signature (%d bytes)\n",
697 ctx = EVP_MD_CTX_create();
699 ret = openssl_err("EVP context creation failed");
702 EVP_MD_CTX_init(ctx);
703 if (!EVP_SignInit(ctx, EVP_sha256())) {
704 ret = openssl_err("Signer setup failed");
708 if (!EVP_SignUpdate(ctx, data, datasz)) {
709 ret = openssl_err("Signing data failed");
713 if (!EVP_SignFinal(ctx, sig->sig, &sig_size, evp_key)) {
714 ret = openssl_err("Could not obtain signature");
718 EVP_MD_CTX_cleanup(ctx);
719 EVP_MD_CTX_destroy(ctx);
720 EVP_PKEY_free(evp_key);
725 EVP_MD_CTX_destroy(ctx);
727 EVP_PKEY_free(evp_key);
728 fprintf(stderr, "Failed to create %s signature\n", signame);
732 static int kwb_verify(RSA *key, void *data, int datasz, struct sig_v1 *sig,
740 evp_key = EVP_PKEY_new();
742 return openssl_err("EVP_PKEY object creation failed");
744 if (!EVP_PKEY_set1_RSA(evp_key, key)) {
745 ret = openssl_err("EVP key setup failed");
749 size = EVP_PKEY_size(evp_key);
750 if (size > sizeof(sig->sig)) {
751 fprintf(stderr, "Invalid signature size (%d bytes)\n",
757 ctx = EVP_MD_CTX_create();
759 ret = openssl_err("EVP context creation failed");
762 EVP_MD_CTX_init(ctx);
763 if (!EVP_VerifyInit(ctx, EVP_sha256())) {
764 ret = openssl_err("Verifier setup failed");
768 if (!EVP_VerifyUpdate(ctx, data, datasz)) {
769 ret = openssl_err("Hashing data failed");
773 if (EVP_VerifyFinal(ctx, sig->sig, sizeof(sig->sig), evp_key) != 1) {
774 ret = openssl_err("Could not verify signature");
778 EVP_MD_CTX_cleanup(ctx);
779 EVP_MD_CTX_destroy(ctx);
780 EVP_PKEY_free(evp_key);
785 EVP_MD_CTX_destroy(ctx);
787 EVP_PKEY_free(evp_key);
788 fprintf(stderr, "Failed to verify %s signature\n", signame);
792 static int kwb_sign_and_verify(RSA *key, void *data, int datasz,
793 struct sig_v1 *sig, char *signame)
795 if (kwb_sign(key, data, datasz, sig, signame) < 0)
798 if (kwb_verify(key, data, datasz, sig, signame) < 0)
805 static int kwb_dump_fuse_cmds_38x(FILE *out, struct secure_hdr_v1 *sec_hdr)
807 struct hash_v1 kak_pub_hash;
808 struct image_cfg_element *e;
809 unsigned int fuse_line;
815 if (!out || !sec_hdr)
818 ret = kwb_compute_pubkey_hash(&sec_hdr->kak, &kak_pub_hash);
822 fprintf(out, "# burn KAK pub key hash\n");
823 ptr = kak_pub_hash.hash;
824 for (fuse_line = 26; fuse_line <= 30; ++fuse_line) {
825 fprintf(out, "fuse prog -y %u 0 ", fuse_line);
827 for (i = 4; i-- > 0;)
828 fprintf(out, "%02hx", (ushort)ptr[i]);
832 if (fuse_line < 30) {
833 for (i = 3; i-- > 0;)
834 fprintf(out, "%02hx", (ushort)ptr[i]);
837 fprintf(out, "000000");
840 fprintf(out, " 1\n");
843 fprintf(out, "# burn CSK selection\n");
845 idx = image_get_csk_index();
846 if (idx < 0 || idx > 15) {
851 for (fuse_line = 31; fuse_line < 31 + idx; ++fuse_line)
852 fprintf(out, "fuse prog -y %u 0 00000001 00000000 1\n",
855 fprintf(out, "# CSK index is 0; no mods needed\n");
858 e = image_find_option(IMAGE_CFG_BOX_ID);
860 fprintf(out, "# set box ID\n");
861 fprintf(out, "fuse prog -y 48 0 %08x 00000000 1\n", e->boxid);
864 e = image_find_option(IMAGE_CFG_FLASH_ID);
866 fprintf(out, "# set flash ID\n");
867 fprintf(out, "fuse prog -y 47 0 %08x 00000000 1\n", e->flashid);
870 fprintf(out, "# enable secure mode ");
871 fprintf(out, "(must be the last fuse line written)\n");
874 e = image_find_option(IMAGE_CFG_SEC_BOOT_DEV);
876 fprintf(stderr, "ERROR: secured mode boot device not given\n");
881 if (e->sec_boot_dev > 0xff) {
882 fprintf(stderr, "ERROR: secured mode boot device invalid\n");
887 val |= (e->sec_boot_dev << 8);
889 fprintf(out, "fuse prog -y 24 0 %08x 0103e0a9 1\n", val);
891 fprintf(out, "# lock (unused) fuse lines (0-23)s\n");
892 for (fuse_line = 0; fuse_line < 24; ++fuse_line)
893 fprintf(out, "fuse prog -y %u 2 1\n", fuse_line);
895 fprintf(out, "# OK, that's all :-)\n");
901 static int kwb_dump_fuse_cmds(struct secure_hdr_v1 *sec_hdr)
904 struct image_cfg_element *e;
906 e = image_find_option(IMAGE_CFG_SEC_FUSE_DUMP);
910 if (!strcmp(e->name, "a38x")) {
911 FILE *out = fopen("kwb_fuses_a38x.txt", "w+");
914 fprintf(stderr, "Couldn't open eFuse settings: '%s': %s\n",
915 "kwb_fuses_a38x.txt", strerror(errno));
919 kwb_dump_fuse_cmds_38x(out, sec_hdr);
930 static int image_fill_xip_header(void *image, struct image_tool_params *params)
932 struct main_hdr_v1 *main_hdr = image; /* kwbimage v0 and v1 have same XIP members */
933 int version = kwbimage_version(image);
934 uint32_t srcaddr = le32_to_cpu(main_hdr->srcaddr);
935 uint32_t startaddr = 0;
937 if (main_hdr->blockid != IBR_HDR_SPI_ID) {
938 fprintf(stderr, "XIP is supported only for SPI images\n");
943 params->addr >= 0xE8000000 && params->addr < 0xEFFFFFFF &&
944 params->ep >= 0xE8000000 && params->ep < 0xEFFFFFFF) {
945 /* Load and Execute address is in SPI address space (kwbimage v0) */
946 startaddr = 0xE8000000;
947 } else if (version != 0 &&
948 params->addr >= 0xD4000000 && params->addr < 0xD7FFFFFF &&
949 params->ep >= 0xD4000000 && params->ep < 0xD7FFFFFF) {
950 /* Load and Execute address is in SPI address space (kwbimage v1) */
951 startaddr = 0xD4000000;
952 } else if (version != 0 &&
953 params->addr >= 0xD8000000 && params->addr < 0xDFFFFFFF &&
954 params->ep >= 0xD8000000 && params->ep < 0xDFFFFFFF) {
955 /* Load and Execute address is in Device bus space (kwbimage v1) */
956 startaddr = 0xD8000000;
957 } else if (params->addr != 0x0) {
958 /* Load address is non-zero */
960 fprintf(stderr, "XIP Load Address or XIP Entry Point is not in SPI address space\n");
962 fprintf(stderr, "XIP Load Address or XIP Entry Point is not in SPI nor in Device bus address space\n");
967 * For XIP destaddr must be set to 0xFFFFFFFF and
968 * execaddr relative to the start of XIP memory address space.
970 main_hdr->destaddr = cpu_to_le32(0xFFFFFFFF);
972 if (startaddr == 0) {
974 * mkimage's --load-address 0x0 means that binary is Position
975 * Independent and in this case mkimage's --entry-point address
976 * is relative offset from beginning of the data part of image.
978 main_hdr->execaddr = cpu_to_le32(srcaddr + params->ep);
980 /* The lowest possible load address is after the header at srcaddr. */
981 if (params->addr - startaddr < srcaddr) {
983 "Invalid XIP Load Address 0x%08x.\n"
984 "The lowest address for this configuration is 0x%08x.\n",
985 params->addr, (unsigned)(startaddr + srcaddr));
988 main_hdr->srcaddr = cpu_to_le32(params->addr - startaddr);
989 main_hdr->execaddr = cpu_to_le32(params->ep - startaddr);
995 static size_t image_headersz_align(size_t headersz, uint8_t blockid)
998 * Header needs to be 4-byte aligned, which is already ensured by code
999 * above. Moreover UART images must have header aligned to 128 bytes
1000 * (xmodem block size), NAND images to 256 bytes (ECC calculation),
1001 * and SATA and SDIO images to 512 bytes (storage block size).
1002 * Note that SPI images do not have to have header size aligned
1003 * to 256 bytes because it is possible to read from SPI storage from
1004 * any offset (read offset does not have to be aligned to block size).
1006 if (blockid == IBR_HDR_UART_ID)
1007 return ALIGN(headersz, 128);
1008 else if (blockid == IBR_HDR_NAND_ID)
1009 return ALIGN(headersz, 256);
1010 else if (blockid == IBR_HDR_SATA_ID || blockid == IBR_HDR_SDIO_ID)
1011 return ALIGN(headersz, 512);
1016 static size_t image_headersz_v0(int *hasext)
1020 headersz = sizeof(struct main_hdr_v0);
1021 if (image_count_options(IMAGE_CFG_DATA) > 0) {
1022 headersz += sizeof(struct ext_hdr_v0);
1030 static void *image_create_v0(size_t *dataoff, struct image_tool_params *params,
1033 struct image_cfg_element *e;
1035 struct main_hdr_v0 *main_hdr;
1040 * Calculate the size of the header and the offset of the
1043 headersz = image_headersz_v0(&has_ext);
1044 *dataoff = image_headersz_align(headersz, image_get_bootfrom());
1046 image = malloc(headersz);
1048 fprintf(stderr, "Cannot allocate memory for image\n");
1052 memset(image, 0, headersz);
1054 main_hdr = (struct main_hdr_v0 *)image;
1056 /* Fill in the main header */
1057 main_hdr->blocksize =
1058 cpu_to_le32(payloadsz);
1059 main_hdr->srcaddr = cpu_to_le32(*dataoff);
1060 main_hdr->ext = has_ext;
1061 main_hdr->version = 0;
1062 main_hdr->destaddr = cpu_to_le32(params->addr);
1063 main_hdr->execaddr = cpu_to_le32(params->ep);
1064 main_hdr->blockid = image_get_bootfrom();
1066 e = image_find_option(IMAGE_CFG_NAND_ECC_MODE);
1068 main_hdr->nandeccmode = e->nandeccmode;
1069 e = image_find_option(IMAGE_CFG_NAND_BLKSZ);
1071 main_hdr->nandblocksize = e->nandblksz / (64 * 1024);
1072 e = image_find_option(IMAGE_CFG_NAND_PAGESZ);
1074 main_hdr->nandpagesize = cpu_to_le16(e->nandpagesz);
1075 e = image_find_option(IMAGE_CFG_NAND_BADBLK_LOCATION);
1077 main_hdr->nandbadblklocation = e->nandbadblklocation;
1080 * For SATA srcaddr is specified in number of sectors.
1081 * This expects the sector size to be 512 bytes.
1083 if (main_hdr->blockid == IBR_HDR_SATA_ID)
1084 main_hdr->srcaddr = cpu_to_le32(le32_to_cpu(main_hdr->srcaddr) / 512);
1086 /* For PCIe srcaddr is not used and must be set to 0xFFFFFFFF. */
1087 if (main_hdr->blockid == IBR_HDR_PEX_ID)
1088 main_hdr->srcaddr = cpu_to_le32(0xFFFFFFFF);
1090 if (params->xflag) {
1091 if (!image_fill_xip_header(main_hdr, params)) {
1095 *dataoff = le32_to_cpu(main_hdr->srcaddr);
1098 /* Generate the ext header */
1100 struct ext_hdr_v0 *ext_hdr;
1103 ext_hdr = (struct ext_hdr_v0 *)
1104 (image + sizeof(struct main_hdr_v0));
1105 ext_hdr->offset = cpu_to_le32(0x40);
1107 for (cfgi = 0, datai = 0; cfgi < cfgn; cfgi++) {
1108 e = &image_cfg[cfgi];
1109 if (e->type != IMAGE_CFG_DATA)
1112 ext_hdr->rcfg[datai].raddr =
1113 cpu_to_le32(e->regdata.raddr);
1114 ext_hdr->rcfg[datai].rdata =
1115 cpu_to_le32(e->regdata.rdata);
1119 ext_hdr->checksum = image_checksum8(ext_hdr,
1120 sizeof(struct ext_hdr_v0));
1123 main_hdr->checksum = image_checksum8(image,
1124 sizeof(struct main_hdr_v0));
1129 static size_t image_headersz_v1(int *hasext)
1131 struct image_cfg_element *e;
1139 headersz = sizeof(struct main_hdr_v1);
1141 if (image_get_csk_index() >= 0) {
1142 headersz += sizeof(struct secure_hdr_v1);
1147 cpu_sheeva = image_is_cpu_sheeva();
1150 for (cfgi = 0; cfgi < cfgn; cfgi++) {
1151 e = &image_cfg[cfgi];
1153 if (e->type == IMAGE_CFG_DATA)
1156 if (e->type == IMAGE_CFG_DATA_DELAY ||
1157 (e->type == IMAGE_CFG_BINARY && count > 0)) {
1158 headersz += sizeof(struct register_set_hdr_v1) + 8 * count + 4;
1162 if (e->type != IMAGE_CFG_BINARY)
1165 ret = stat(e->binary.file, &s);
1170 memset(cwd, 0, sizeof(cwd));
1171 if (!getcwd(cwd, sizeof(cwd))) {
1172 dir = "current working directory";
1173 perror("getcwd() failed");
1177 "Didn't find the file '%s' in '%s' which is mandatory to generate the image\n"
1178 "This file generally contains the DDR3 training code, and should be extracted from an existing bootable\n"
1179 "image for your board. Use 'dumpimage -T kwbimage -p 1' to extract it from an existing image.\n",
1180 e->binary.file, dir);
1184 headersz += sizeof(struct opt_hdr_v1) + sizeof(uint32_t) +
1185 (e->binary.nargs) * sizeof(uint32_t);
1187 if (e->binary.loadaddr) {
1189 * BootROM loads kwbimage header (in which the
1190 * executable code is also stored) to address
1191 * 0x40004000 or 0x40000000. Thus there is
1192 * restriction for the load address of the N-th
1195 unsigned int base_addr, low_addr, high_addr;
1197 base_addr = cpu_sheeva ? 0x40004000 : 0x40000000;
1198 low_addr = base_addr + headersz;
1199 high_addr = low_addr +
1200 (BINARY_MAX_ARGS - e->binary.nargs) * sizeof(uint32_t);
1202 if (cpu_sheeva && e->binary.loadaddr % 16) {
1204 "Invalid LOAD_ADDRESS 0x%08x for BINARY %s with %d args.\n"
1205 "Address for CPU SHEEVA must be 16-byte aligned.\n",
1206 e->binary.loadaddr, e->binary.file, e->binary.nargs);
1210 if (e->binary.loadaddr % 4 || e->binary.loadaddr < low_addr ||
1211 e->binary.loadaddr > high_addr) {
1213 "Invalid LOAD_ADDRESS 0x%08x for BINARY %s with %d args.\n"
1214 "Address must be 4-byte aligned and in range 0x%08x-0x%08x.\n",
1215 e->binary.loadaddr, e->binary.file,
1216 e->binary.nargs, low_addr, high_addr);
1219 headersz = e->binary.loadaddr - base_addr;
1220 } else if (cpu_sheeva) {
1221 headersz = ALIGN(headersz, 16);
1223 headersz = ALIGN(headersz, 4);
1226 headersz += ALIGN(s.st_size, 4) + sizeof(uint32_t);
1232 headersz += sizeof(struct register_set_hdr_v1) + 8 * count + 4;
1235 * For all images except UART, headersz stored in header itself should
1236 * contains header size without padding. For UART image BootROM rounds
1237 * down headersz to multiply of 128 bytes. Therefore align UART headersz
1238 * to multiply of 128 bytes to ensure that remaining UART header bytes
1239 * are not ignored by BootROM.
1241 if (image_get_bootfrom() == IBR_HDR_UART_ID)
1242 headersz = ALIGN(headersz, 128);
1247 static int add_binary_header_v1(uint8_t **cur, uint8_t **next_ext,
1248 struct image_cfg_element *binarye,
1249 struct main_hdr_v1 *main_hdr)
1251 struct opt_hdr_v1 *hdr = (struct opt_hdr_v1 *)*cur;
1263 hdr->headertype = OPT_HDR_V1_BINARY_TYPE;
1265 bin = fopen(binarye->binary.file, "r");
1267 fprintf(stderr, "Cannot open binary file %s\n",
1268 binarye->binary.file);
1272 if (fstat(fileno(bin), &s)) {
1273 fprintf(stderr, "Cannot stat binary file %s\n",
1274 binarye->binary.file);
1278 *cur += sizeof(struct opt_hdr_v1);
1280 args = (uint32_t *)*cur;
1281 *args = cpu_to_le32(binarye->binary.nargs);
1283 for (argi = 0; argi < binarye->binary.nargs; argi++)
1284 args[argi] = cpu_to_le32(binarye->binary.args[argi]);
1286 *cur += (binarye->binary.nargs + 1) * sizeof(uint32_t);
1289 * ARM executable code inside the BIN header on platforms with Sheeva
1290 * CPU (A370 and AXP) must always be aligned with the 128-bit boundary.
1291 * In the case when this code is not position independent (e.g. ARM
1292 * SPL), it must be placed at fixed load and execute address.
1293 * This requirement can be met by inserting dummy arguments into
1294 * BIN header, if needed.
1296 cpu_sheeva = image_is_cpu_sheeva();
1297 base_addr = cpu_sheeva ? 0x40004000 : 0x40000000;
1298 offset = *cur - (uint8_t *)main_hdr;
1299 if (binarye->binary.loadaddr)
1300 add_args = (binarye->binary.loadaddr - base_addr - offset) / sizeof(uint32_t);
1301 else if (cpu_sheeva)
1302 add_args = ((16 - offset % 16) % 16) / sizeof(uint32_t);
1306 *(args - 1) = cpu_to_le32(binarye->binary.nargs + add_args);
1307 *cur += add_args * sizeof(uint32_t);
1310 ret = fread(*cur, s.st_size, 1, bin);
1313 "Could not read binary image %s\n",
1314 binarye->binary.file);
1320 *cur += ALIGN(s.st_size, 4);
1322 *((uint32_t *)*cur) = 0x00000000;
1326 *cur += sizeof(uint32_t);
1328 binhdrsz = sizeof(struct opt_hdr_v1) +
1329 (binarye->binary.nargs + add_args + 2) * sizeof(uint32_t) +
1330 ALIGN(s.st_size, 4);
1331 hdr->headersz_lsb = cpu_to_le16(binhdrsz & 0xFFFF);
1332 hdr->headersz_msb = (binhdrsz & 0xFFFF0000) >> 16;
1342 static int export_pub_kak_hash(RSA *kak, struct secure_hdr_v1 *secure_hdr)
1347 hashf = fopen("pub_kak_hash.txt", "w");
1349 fprintf(stderr, "Couldn't open hash file: '%s': %s\n",
1350 "pub_kak_hash.txt", strerror(errno));
1354 res = kwb_export_pubkey(kak, &secure_hdr->kak, hashf, "KAK");
1358 return res < 0 ? 1 : 0;
1361 static int kwb_sign_csk_with_kak(struct image_tool_params *params,
1362 struct secure_hdr_v1 *secure_hdr, RSA *csk)
1365 RSA *kak_pub = NULL;
1366 int csk_idx = image_get_csk_index();
1367 struct sig_v1 tmp_sig;
1369 if (csk_idx < 0 || csk_idx > 15) {
1370 fprintf(stderr, "Invalid CSK index %d\n", csk_idx);
1374 if (kwb_load_kak(params, &kak) < 0)
1377 if (export_pub_kak_hash(kak, secure_hdr))
1380 if (kwb_import_pubkey(&kak_pub, &secure_hdr->kak, "KAK") < 0)
1383 if (kwb_export_pubkey(csk, &secure_hdr->csk[csk_idx], NULL, "CSK") < 0)
1386 if (kwb_sign_and_verify(kak, &secure_hdr->csk,
1387 sizeof(secure_hdr->csk) +
1388 sizeof(secure_hdr->csksig),
1389 &tmp_sig, "CSK") < 0)
1392 if (kwb_verify(kak_pub, &secure_hdr->csk,
1393 sizeof(secure_hdr->csk) +
1394 sizeof(secure_hdr->csksig),
1395 &tmp_sig, "CSK (2)") < 0)
1398 secure_hdr->csksig = tmp_sig;
1403 static int add_secure_header_v1(struct image_tool_params *params, uint8_t *image_ptr,
1404 size_t image_size, uint8_t *header_ptr, size_t headersz,
1405 struct secure_hdr_v1 *secure_hdr)
1407 struct image_cfg_element *e_jtagdelay;
1408 struct image_cfg_element *e_boxid;
1409 struct image_cfg_element *e_flashid;
1411 struct sig_v1 tmp_sig;
1412 bool specialized_img = image_get_spezialized_img();
1414 kwb_msg("Create secure header content\n");
1416 e_jtagdelay = image_find_option(IMAGE_CFG_JTAG_DELAY);
1417 e_boxid = image_find_option(IMAGE_CFG_BOX_ID);
1418 e_flashid = image_find_option(IMAGE_CFG_FLASH_ID);
1420 if (kwb_load_csk(params, &csk) < 0)
1423 secure_hdr->headertype = OPT_HDR_V1_SECURE_TYPE;
1424 secure_hdr->headersz_msb = 0;
1425 secure_hdr->headersz_lsb = cpu_to_le16(sizeof(struct secure_hdr_v1));
1427 secure_hdr->jtag_delay = e_jtagdelay->jtag_delay;
1428 if (e_boxid && specialized_img)
1429 secure_hdr->boxid = cpu_to_le32(e_boxid->boxid);
1430 if (e_flashid && specialized_img)
1431 secure_hdr->flashid = cpu_to_le32(e_flashid->flashid);
1433 if (kwb_sign_csk_with_kak(params, secure_hdr, csk))
1436 if (kwb_sign_and_verify(csk, image_ptr, image_size - 4,
1437 &secure_hdr->imgsig, "image") < 0)
1440 if (kwb_sign_and_verify(csk, header_ptr, headersz, &tmp_sig, "header") < 0)
1443 secure_hdr->hdrsig = tmp_sig;
1445 kwb_dump_fuse_cmds(secure_hdr);
1450 static void finish_register_set_header_v1(uint8_t **cur, uint8_t **next_ext,
1451 struct register_set_hdr_v1 *register_set_hdr,
1452 int *datai, uint8_t delay)
1454 int size = sizeof(struct register_set_hdr_v1) + 8 * (*datai) + 4;
1456 register_set_hdr->headertype = OPT_HDR_V1_REGISTER_TYPE;
1457 register_set_hdr->headersz_lsb = cpu_to_le16(size & 0xFFFF);
1458 register_set_hdr->headersz_msb = size >> 16;
1459 register_set_hdr->data[*datai].last_entry.delay = delay;
1462 *next_ext = ®ister_set_hdr->data[*datai].last_entry.next;
1466 static void *image_create_v1(size_t *dataoff, struct image_tool_params *params,
1467 uint8_t *ptr, int payloadsz)
1469 struct image_cfg_element *e;
1470 struct main_hdr_v1 *main_hdr;
1471 struct register_set_hdr_v1 *register_set_hdr;
1472 struct secure_hdr_v1 *secure_hdr = NULL;
1474 uint8_t *image, *cur;
1476 uint8_t *next_ext = NULL;
1481 * Calculate the size of the header and the offset of the
1484 headersz = image_headersz_v1(&hasext);
1487 *dataoff = image_headersz_align(headersz, image_get_bootfrom());
1489 image = malloc(headersz);
1491 fprintf(stderr, "Cannot allocate memory for image\n");
1495 memset(image, 0, headersz);
1497 main_hdr = (struct main_hdr_v1 *)image;
1499 cur += sizeof(struct main_hdr_v1);
1500 next_ext = &main_hdr->ext;
1502 /* Fill the main header */
1503 main_hdr->blocksize =
1504 cpu_to_le32(payloadsz);
1505 main_hdr->headersz_lsb = cpu_to_le16(headersz & 0xFFFF);
1506 main_hdr->headersz_msb = (headersz & 0xFFFF0000) >> 16;
1507 main_hdr->destaddr = cpu_to_le32(params->addr);
1508 main_hdr->execaddr = cpu_to_le32(params->ep);
1509 main_hdr->srcaddr = cpu_to_le32(*dataoff);
1510 main_hdr->ext = hasext;
1511 main_hdr->version = 1;
1512 main_hdr->blockid = image_get_bootfrom();
1514 e = image_find_option(IMAGE_CFG_NAND_BLKSZ);
1516 main_hdr->nandblocksize = e->nandblksz / (64 * 1024);
1517 e = image_find_option(IMAGE_CFG_NAND_PAGESZ);
1519 main_hdr->nandpagesize = cpu_to_le16(e->nandpagesz);
1520 e = image_find_option(IMAGE_CFG_NAND_BADBLK_LOCATION);
1522 main_hdr->nandbadblklocation = e->nandbadblklocation;
1523 e = image_find_option(IMAGE_CFG_BAUDRATE);
1525 main_hdr->options |= baudrate_to_option(e->baudrate);
1526 e = image_find_option(IMAGE_CFG_UART_PORT);
1528 main_hdr->options |= (e->uart_port & 3) << 3;
1529 e = image_find_option(IMAGE_CFG_UART_MPP);
1531 main_hdr->options |= (e->uart_mpp & 7) << 5;
1532 e = image_find_option(IMAGE_CFG_DEBUG);
1534 main_hdr->flags = e->debug ? 0x1 : 0;
1537 * For SATA srcaddr is specified in number of sectors.
1538 * This expects the sector size to be 512 bytes.
1540 if (main_hdr->blockid == IBR_HDR_SATA_ID)
1541 main_hdr->srcaddr = cpu_to_le32(le32_to_cpu(main_hdr->srcaddr) / 512);
1543 /* For PCIe srcaddr is not used and must be set to 0xFFFFFFFF. */
1544 if (main_hdr->blockid == IBR_HDR_PEX_ID)
1545 main_hdr->srcaddr = cpu_to_le32(0xFFFFFFFF);
1547 if (params->xflag) {
1548 if (!image_fill_xip_header(main_hdr, params)) {
1552 *dataoff = le32_to_cpu(main_hdr->srcaddr);
1555 if (image_get_csk_index() >= 0) {
1557 * only reserve the space here; we fill the header later since
1558 * we need the header to be complete to compute the signatures
1560 secure_hdr = (struct secure_hdr_v1 *)cur;
1561 cur += sizeof(struct secure_hdr_v1);
1563 next_ext = &secure_hdr->next;
1567 for (cfgi = 0; cfgi < cfgn; cfgi++) {
1568 e = &image_cfg[cfgi];
1569 if (e->type != IMAGE_CFG_DATA &&
1570 e->type != IMAGE_CFG_DATA_DELAY &&
1571 e->type != IMAGE_CFG_BINARY)
1575 register_set_hdr = (struct register_set_hdr_v1 *)cur;
1577 /* If delay is not specified, use the smallest possible value. */
1578 if (e->type == IMAGE_CFG_DATA_DELAY)
1579 delay = e->regdata_delay;
1581 delay = REGISTER_SET_HDR_OPT_DELAY_MS(0);
1584 * DATA_DELAY command is the last entry in the register set
1585 * header and BINARY command inserts new binary header.
1586 * Therefore BINARY command requires to finish register set
1587 * header if some DATA command was specified. And DATA_DELAY
1588 * command automatically finish register set header even when
1589 * there was no DATA command.
1591 if (e->type == IMAGE_CFG_DATA_DELAY ||
1592 (e->type == IMAGE_CFG_BINARY && datai != 0))
1593 finish_register_set_header_v1(&cur, &next_ext, register_set_hdr,
1596 if (e->type == IMAGE_CFG_DATA) {
1597 register_set_hdr->data[datai].entry.address =
1598 cpu_to_le32(e->regdata.raddr);
1599 register_set_hdr->data[datai].entry.value =
1600 cpu_to_le32(e->regdata.rdata);
1604 if (e->type == IMAGE_CFG_BINARY) {
1605 if (add_binary_header_v1(&cur, &next_ext, e, main_hdr))
1610 /* Set delay to the smallest possible value. */
1611 delay = REGISTER_SET_HDR_OPT_DELAY_MS(0);
1612 finish_register_set_header_v1(&cur, &next_ext, register_set_hdr,
1616 if (secure_hdr && add_secure_header_v1(params, ptr + *dataoff, payloadsz,
1617 image, headersz, secure_hdr))
1620 /* Calculate and set the header checksum */
1621 main_hdr->checksum = image_checksum8(main_hdr, headersz);
1626 static int recognize_keyword(char *keyword)
1630 for (kw_id = 1; kw_id < IMAGE_CFG_COUNT; ++kw_id)
1631 if (!strcmp(keyword, id_strs[kw_id]))
1637 static int image_create_config_parse_oneline(char *line,
1638 struct image_cfg_element *el)
1640 char *keyword, *saveptr, *value1, *value2;
1641 char delimiters[] = " \t";
1642 int keyword_id, ret, argi;
1643 char *unknown_msg = "Ignoring unknown line '%s'\n";
1645 keyword = strtok_r(line, delimiters, &saveptr);
1646 keyword_id = recognize_keyword(keyword);
1649 fprintf(stderr, unknown_msg, line);
1653 el->type = keyword_id;
1655 value1 = strtok_r(NULL, delimiters, &saveptr);
1658 fprintf(stderr, "Parameter missing in line '%s'\n", line);
1662 switch (keyword_id) {
1663 case IMAGE_CFG_VERSION:
1664 el->version = atoi(value1);
1667 if (strcmp(value1, "FEROCEON") == 0)
1669 else if (strcmp(value1, "SHEEVA") == 0)
1671 else if (strcmp(value1, "A9") == 0)
1674 fprintf(stderr, "Invalid CPU %s\n", value1);
1678 case IMAGE_CFG_BOOT_FROM:
1679 ret = image_boot_mode_id(value1);
1682 fprintf(stderr, "Invalid boot media '%s'\n", value1);
1687 case IMAGE_CFG_NAND_BLKSZ:
1688 el->nandblksz = strtoul(value1, NULL, 16);
1690 case IMAGE_CFG_NAND_BADBLK_LOCATION:
1691 el->nandbadblklocation = strtoul(value1, NULL, 16);
1693 case IMAGE_CFG_NAND_ECC_MODE:
1694 ret = image_nand_ecc_mode_id(value1);
1697 fprintf(stderr, "Invalid NAND ECC mode '%s'\n", value1);
1700 el->nandeccmode = ret;
1702 case IMAGE_CFG_NAND_PAGESZ:
1703 el->nandpagesz = strtoul(value1, NULL, 16);
1705 case IMAGE_CFG_BINARY:
1708 el->binary.file = strdup(value1);
1710 char *value = strtok_r(NULL, delimiters, &saveptr);
1716 if (!strcmp(value, "LOAD_ADDRESS")) {
1717 value = strtok_r(NULL, delimiters, &saveptr);
1720 "Missing address argument for BINARY LOAD_ADDRESS\n");
1723 el->binary.loadaddr = strtoul(value, &endptr, 16);
1726 "Invalid argument '%s' for BINARY LOAD_ADDRESS\n",
1730 value = strtok_r(NULL, delimiters, &saveptr);
1733 "Unexpected argument '%s' after BINARY LOAD_ADDRESS\n",
1740 el->binary.args[argi] = strtoul(value, &endptr, 16);
1742 fprintf(stderr, "Invalid argument '%s' for BINARY\n", value);
1746 if (argi >= BINARY_MAX_ARGS) {
1748 "Too many arguments for BINARY\n");
1752 el->binary.nargs = argi;
1754 case IMAGE_CFG_DATA:
1755 value2 = strtok_r(NULL, delimiters, &saveptr);
1757 if (!value1 || !value2) {
1759 "Invalid number of arguments for DATA\n");
1763 el->regdata.raddr = strtoul(value1, NULL, 16);
1764 el->regdata.rdata = strtoul(value2, NULL, 16);
1766 case IMAGE_CFG_DATA_DELAY:
1767 if (!strcmp(value1, "SDRAM_SETUP"))
1768 el->regdata_delay = REGISTER_SET_HDR_OPT_DELAY_SDRAM_SETUP;
1770 el->regdata_delay = REGISTER_SET_HDR_OPT_DELAY_MS(strtoul(value1, NULL, 10));
1771 if (el->regdata_delay > 255) {
1772 fprintf(stderr, "Maximal DATA_DELAY is 255\n");
1776 case IMAGE_CFG_BAUDRATE:
1777 el->baudrate = strtoul(value1, NULL, 10);
1779 case IMAGE_CFG_UART_PORT:
1780 el->uart_port = strtoul(value1, NULL, 16);
1782 case IMAGE_CFG_UART_MPP:
1783 el->uart_mpp = strtoul(value1, NULL, 16);
1785 case IMAGE_CFG_DEBUG:
1786 el->debug = strtoul(value1, NULL, 10);
1789 el->key_name = strdup(value1);
1792 el->key_name = strdup(value1);
1794 case IMAGE_CFG_CSK_INDEX:
1795 el->csk_idx = strtol(value1, NULL, 0);
1797 case IMAGE_CFG_JTAG_DELAY:
1798 el->jtag_delay = strtoul(value1, NULL, 0);
1800 case IMAGE_CFG_BOX_ID:
1801 el->boxid = strtoul(value1, NULL, 0);
1803 case IMAGE_CFG_FLASH_ID:
1804 el->flashid = strtoul(value1, NULL, 0);
1806 case IMAGE_CFG_SEC_SPECIALIZED_IMG:
1807 el->sec_specialized_img = true;
1809 case IMAGE_CFG_SEC_COMMON_IMG:
1810 el->sec_specialized_img = false;
1812 case IMAGE_CFG_SEC_BOOT_DEV:
1813 el->sec_boot_dev = strtoul(value1, NULL, 0);
1815 case IMAGE_CFG_SEC_FUSE_DUMP:
1816 el->name = strdup(value1);
1819 fprintf(stderr, unknown_msg, line);
1826 * Parse the configuration file 'fcfg' into the array of configuration
1827 * elements 'image_cfg', and return the number of configuration
1828 * elements in 'cfgn'.
1830 static int image_create_config_parse(FILE *fcfg)
1835 /* Parse the configuration file */
1836 while (!feof(fcfg)) {
1840 /* Read the current line */
1841 memset(buf, 0, sizeof(buf));
1842 line = fgets(buf, sizeof(buf), fcfg);
1846 /* Ignore useless lines */
1847 if (line[0] == '\n' || line[0] == '#')
1850 /* Strip final newline */
1851 if (line[strlen(line) - 1] == '\n')
1852 line[strlen(line) - 1] = 0;
1854 /* Parse the current line */
1855 ret = image_create_config_parse_oneline(line,
1862 if (cfgi >= IMAGE_CFG_ELEMENT_MAX) {
1864 "Too many configuration elements in .cfg file\n");
1873 static int image_get_version(void)
1875 struct image_cfg_element *e;
1877 e = image_find_option(IMAGE_CFG_VERSION);
1884 static void kwbimage_set_header(void *ptr, struct stat *sbuf, int ifd,
1885 struct image_tool_params *params)
1897 * Do not use sbuf->st_size as it contains size with padding.
1898 * We need original image data size, so stat original file.
1900 if (params->skipcpy) {
1902 } else if (stat(params->datafile, &s)) {
1903 fprintf(stderr, "Could not stat data file %s: %s\n",
1904 params->datafile, strerror(errno));
1907 datasz = ALIGN(s.st_size, 4);
1909 fcfg = fopen(params->imagename, "r");
1911 fprintf(stderr, "Could not open input file %s\n",
1916 image_cfg = malloc(IMAGE_CFG_ELEMENT_MAX *
1917 sizeof(struct image_cfg_element));
1919 fprintf(stderr, "Cannot allocate memory\n");
1924 memset(image_cfg, 0,
1925 IMAGE_CFG_ELEMENT_MAX * sizeof(struct image_cfg_element));
1928 ret = image_create_config_parse(fcfg);
1935 version = image_get_version();
1938 * Fallback to version 0 if no version is provided in the
1943 image = image_create_v0(&dataoff, params, datasz + 4);
1947 image = image_create_v1(&dataoff, params, ptr, datasz + 4);
1951 fprintf(stderr, "Unsupported version %d\n", version);
1957 fprintf(stderr, "Could not create image\n");
1964 /* Build and add image data checksum */
1965 checksum = cpu_to_le32(image_checksum32((uint8_t *)ptr + dataoff,
1967 memcpy((uint8_t *)ptr + dataoff + datasz, &checksum, sizeof(uint32_t));
1969 /* Finally copy the header into the image area */
1970 memcpy(ptr, image, kwbheader_size(image));
1975 static void kwbimage_print_header(const void *ptr)
1977 struct main_hdr_v0 *mhdr = (struct main_hdr_v0 *)ptr;
1978 struct bin_hdr_v0 *bhdr;
1979 struct opt_hdr_v1 *ohdr;
1981 printf("Image Type: MVEBU Boot from %s Image\n",
1982 image_boot_mode_name(mhdr->blockid));
1983 printf("Image version:%d\n", kwbimage_version(ptr));
1985 for_each_opt_hdr_v1 (ohdr, mhdr) {
1986 if (ohdr->headertype == OPT_HDR_V1_BINARY_TYPE) {
1987 printf("BIN Img Size: ");
1988 genimg_print_size(opt_hdr_v1_size(ohdr) - 12 -
1990 printf("BIN Img Offs: ");
1991 genimg_print_size(((uint8_t *)ohdr - (uint8_t *)mhdr) +
1992 8 + 4 * ohdr->data[0]);
1996 for_each_bin_hdr_v0(bhdr, mhdr) {
1997 printf("BIN Img Size: ");
1998 genimg_print_size(le32_to_cpu(bhdr->size));
1999 printf("BIN Img Addr: %08x\n", le32_to_cpu(bhdr->destaddr));
2000 printf("BIN Img Entr: %08x\n", le32_to_cpu(bhdr->execaddr));
2003 printf("Data Size: ");
2004 genimg_print_size(le32_to_cpu(mhdr->blocksize) - sizeof(uint32_t));
2005 printf("Data Offset: ");
2006 if (mhdr->blockid == IBR_HDR_SATA_ID)
2007 printf("%u Sector%s (LBA)\n", le32_to_cpu(mhdr->srcaddr),
2008 le32_to_cpu(mhdr->srcaddr) != 1 ? "s" : "");
2010 genimg_print_size(le32_to_cpu(mhdr->srcaddr));
2011 if (mhdr->blockid == IBR_HDR_SPI_ID && le32_to_cpu(mhdr->destaddr) == 0xFFFFFFFF) {
2012 printf("Load Address: XIP\n");
2013 printf("Execute Offs: %08x\n", le32_to_cpu(mhdr->execaddr));
2015 printf("Load Address: %08x\n", le32_to_cpu(mhdr->destaddr));
2016 printf("Entry Point: %08x\n", le32_to_cpu(mhdr->execaddr));
2020 static int kwbimage_check_image_types(uint8_t type)
2022 if (type == IH_TYPE_KWBIMAGE)
2023 return EXIT_SUCCESS;
2025 return EXIT_FAILURE;
2028 static int kwbimage_verify_header(unsigned char *ptr, int image_size,
2029 struct image_tool_params *params)
2031 size_t header_size = kwbheader_size(ptr);
2037 if (header_size > 192*1024)
2038 return -FDT_ERR_BADSTRUCTURE;
2040 if (header_size > image_size)
2041 return -FDT_ERR_BADSTRUCTURE;
2043 if (!main_hdr_checksum_ok(ptr))
2044 return -FDT_ERR_BADSTRUCTURE;
2046 /* Only version 0 extended header has checksum */
2047 if (kwbimage_version(ptr) == 0) {
2048 struct main_hdr_v0 *mhdr = (struct main_hdr_v0 *)ptr;
2049 struct ext_hdr_v0 *ext_hdr;
2050 struct bin_hdr_v0 *bhdr;
2052 for_each_ext_hdr_v0(ext_hdr, ptr) {
2053 csum = image_checksum8(ext_hdr, sizeof(*ext_hdr) - 1);
2054 if (csum != ext_hdr->checksum)
2055 return -FDT_ERR_BADSTRUCTURE;
2058 for_each_bin_hdr_v0(bhdr, ptr) {
2059 csum = image_checksum8(bhdr, (uint8_t *)&bhdr->checksum - (uint8_t *)bhdr - 1);
2060 if (csum != bhdr->checksum)
2061 return -FDT_ERR_BADSTRUCTURE;
2063 if (bhdr->offset > sizeof(*bhdr) || bhdr->offset % 4 != 0)
2064 return -FDT_ERR_BADSTRUCTURE;
2066 if (bhdr->offset + bhdr->size + 4 > sizeof(*bhdr) || bhdr->size % 4 != 0)
2067 return -FDT_ERR_BADSTRUCTURE;
2069 if (image_checksum32((uint8_t *)bhdr + bhdr->offset, bhdr->size) !=
2070 *(uint32_t *)((uint8_t *)bhdr + bhdr->offset + bhdr->size))
2071 return -FDT_ERR_BADSTRUCTURE;
2074 blockid = mhdr->blockid;
2075 offset = le32_to_cpu(mhdr->srcaddr);
2076 size = le32_to_cpu(mhdr->blocksize);
2077 } else if (kwbimage_version(ptr) == 1) {
2078 struct main_hdr_v1 *mhdr = (struct main_hdr_v1 *)ptr;
2079 const uint8_t *mhdr_end;
2080 struct opt_hdr_v1 *ohdr;
2082 mhdr_end = (uint8_t *)mhdr + header_size;
2083 for_each_opt_hdr_v1 (ohdr, ptr)
2084 if (!opt_hdr_v1_valid_size(ohdr, mhdr_end))
2085 return -FDT_ERR_BADSTRUCTURE;
2087 blockid = mhdr->blockid;
2088 offset = le32_to_cpu(mhdr->srcaddr);
2089 size = le32_to_cpu(mhdr->blocksize);
2091 return -FDT_ERR_BADSTRUCTURE;
2095 * For SATA srcaddr is specified in number of sectors.
2096 * This expects that sector size is 512 bytes.
2098 if (blockid == IBR_HDR_SATA_ID)
2102 * For PCIe srcaddr is always set to 0xFFFFFFFF.
2103 * This expects that data starts after all headers.
2105 if (blockid == IBR_HDR_PEX_ID && offset == 0xFFFFFFFF)
2106 offset = header_size;
2108 if (offset > image_size || offset % 4 != 0)
2109 return -FDT_ERR_BADSTRUCTURE;
2111 if (size < 4 || offset + size > image_size || size % 4 != 0)
2112 return -FDT_ERR_BADSTRUCTURE;
2114 if (image_checksum32(ptr + offset, size - 4) !=
2115 *(uint32_t *)(ptr + offset + size - 4))
2116 return -FDT_ERR_BADSTRUCTURE;
2121 static int kwbimage_align_size(int bootfrom, int alloc_len, struct stat s);
2123 static int kwbimage_generate(struct image_tool_params *params,
2124 struct image_type_params *tparams)
2134 fcfg = fopen(params->imagename, "r");
2136 fprintf(stderr, "Could not open input file %s\n",
2141 if (params->skipcpy) {
2143 } else if (stat(params->datafile, &s)) {
2144 fprintf(stderr, "Could not stat data file %s: %s\n",
2145 params->datafile, strerror(errno));
2149 image_cfg = malloc(IMAGE_CFG_ELEMENT_MAX *
2150 sizeof(struct image_cfg_element));
2152 fprintf(stderr, "Cannot allocate memory\n");
2157 memset(image_cfg, 0,
2158 IMAGE_CFG_ELEMENT_MAX * sizeof(struct image_cfg_element));
2161 ret = image_create_config_parse(fcfg);
2168 bootfrom = image_get_bootfrom();
2169 version = image_get_version();
2172 * Fallback to version 0 if no version is provided in the
2177 alloc_len = image_headersz_v0(NULL);
2181 alloc_len = image_headersz_v1(NULL);
2186 if (alloc_len > 192*1024) {
2187 fprintf(stderr, "Header is too big (%u bytes), maximal kwbimage header size is %u bytes\n", alloc_len, 192*1024);
2194 fprintf(stderr, "Unsupported version %d\n", version);
2199 alloc_len = image_headersz_align(alloc_len, image_get_bootfrom());
2203 hdr = malloc(alloc_len);
2205 fprintf(stderr, "%s: malloc return failure: %s\n",
2206 params->cmdname, strerror(errno));
2210 memset(hdr, 0, alloc_len);
2211 tparams->header_size = alloc_len;
2215 * This function should return aligned size of the datafile.
2216 * When skipcpy is set (datafile is skipped) then return value of this
2217 * function is ignored, so we have to put required kwbimage aligning
2218 * into the preallocated header size.
2220 if (params->skipcpy) {
2221 tparams->header_size += kwbimage_align_size(bootfrom, alloc_len, s);
2224 return kwbimage_align_size(bootfrom, alloc_len, s);
2228 static int kwbimage_align_size(int bootfrom, int alloc_len, struct stat s)
2231 * The resulting image needs to be 4-byte aligned. At least
2232 * the Marvell hdrparser tool complains if its unaligned.
2233 * After the image data is stored 4-byte checksum.
2234 * Final UART image must be aligned to 128 bytes.
2235 * Final SPI and NAND images must be aligned to 256 bytes.
2236 * Final SATA and SDIO images must be aligned to 512 bytes.
2238 if (bootfrom == IBR_HDR_SPI_ID || bootfrom == IBR_HDR_NAND_ID)
2239 return 4 + (256 - (alloc_len + s.st_size + 4) % 256) % 256;
2240 else if (bootfrom == IBR_HDR_SATA_ID || bootfrom == IBR_HDR_SDIO_ID)
2241 return 4 + (512 - (alloc_len + s.st_size + 4) % 512) % 512;
2242 else if (bootfrom == IBR_HDR_UART_ID)
2243 return 4 + (128 - (alloc_len + s.st_size + 4) % 128) % 128;
2245 return 4 + (4 - s.st_size % 4) % 4;
2248 static int kwbimage_generate_config(void *ptr, struct image_tool_params *params)
2250 struct main_hdr_v0 *mhdr0 = (struct main_hdr_v0 *)ptr;
2251 struct main_hdr_v1 *mhdr = (struct main_hdr_v1 *)ptr;
2252 size_t header_size = kwbheader_size(ptr);
2253 struct register_set_hdr_v1 *regset_hdr;
2254 struct ext_hdr_v0_reg *regdata;
2255 struct ext_hdr_v0 *ehdr0;
2256 struct bin_hdr_v0 *bhdr0;
2257 struct opt_hdr_v1 *ohdr;
2267 f = fopen(params->outfile, "w");
2269 fprintf(stderr, "Can't open \"%s\": %s\n", params->outfile, strerror(errno));
2273 version = kwbimage_version(ptr);
2277 if (mhdr0->ext > 1 || mhdr0->bin ||
2278 ((ehdr0 = ext_hdr_v0_first(ptr)) &&
2279 (ehdr0->match_addr || ehdr0->match_mask || ehdr0->match_value)))
2284 fprintf(f, "VERSION %d\n", version);
2286 fprintf(f, "BOOT_FROM %s\n", image_boot_mode_name(mhdr->blockid) ?: "<unknown>");
2288 if (version == 0 && mhdr->blockid == IBR_HDR_NAND_ID)
2289 fprintf(f, "NAND_ECC_MODE %s\n", image_nand_ecc_mode_name(mhdr0->nandeccmode));
2291 if (mhdr->blockid == IBR_HDR_NAND_ID)
2292 fprintf(f, "NAND_PAGE_SIZE 0x%x\n", (unsigned)le16_to_cpu(mhdr->nandpagesize));
2294 if (mhdr->blockid == IBR_HDR_NAND_ID && (version != 0 || is_v0_ext || mhdr->nandblocksize != 0)) {
2295 if (mhdr->nandblocksize != 0) /* block size explicitly set in 64 kB unit */
2296 fprintf(f, "NAND_BLKSZ 0x%x\n", (unsigned)mhdr->nandblocksize * 64*1024);
2297 else if (le16_to_cpu(mhdr->nandpagesize) > 512)
2298 fprintf(f, "NAND_BLKSZ 0x10000\n"); /* large page NAND flash = 64 kB block size */
2300 fprintf(f, "NAND_BLKSZ 0x4000\n"); /* small page NAND flash = 16 kB block size */
2303 if (mhdr->blockid == IBR_HDR_NAND_ID && (version != 0 || is_v0_ext))
2304 fprintf(f, "NAND_BADBLK_LOCATION 0x%x\n", (unsigned)mhdr->nandbadblklocation);
2306 if (version == 0 && mhdr->blockid == IBR_HDR_SATA_ID)
2307 fprintf(f, "SATA_PIO_MODE %u\n", (unsigned)mhdr0->satapiomode);
2310 * Addresses and sizes which are specified by mkimage command line
2311 * arguments and not in kwbimage config file
2315 fprintf(f, "#HEADER_SIZE 0x%x\n",
2316 ((unsigned)mhdr->headersz_msb << 8) | le16_to_cpu(mhdr->headersz_lsb));
2318 fprintf(f, "#SRC_ADDRESS 0x%x\n", le32_to_cpu(mhdr->srcaddr));
2319 fprintf(f, "#BLOCK_SIZE 0x%x\n", le32_to_cpu(mhdr->blocksize));
2320 fprintf(f, "#DEST_ADDRESS 0x%08x\n", le32_to_cpu(mhdr->destaddr));
2321 fprintf(f, "#EXEC_ADDRESS 0x%08x\n", le32_to_cpu(mhdr->execaddr));
2324 if (options_to_baudrate(mhdr->options))
2325 fprintf(f, "BAUDRATE %u\n", options_to_baudrate(mhdr->options));
2326 if (options_to_baudrate(mhdr->options) ||
2327 ((mhdr->options >> 3) & 0x3) || ((mhdr->options >> 5) & 0x7)) {
2328 fprintf(f, "UART_PORT %u\n", (unsigned)((mhdr->options >> 3) & 0x3));
2329 fprintf(f, "UART_MPP 0x%x\n", (unsigned)((mhdr->options >> 5) & 0x7));
2331 if (mhdr->flags & 0x1)
2332 fprintf(f, "DEBUG 1\n");
2336 for_each_opt_hdr_v1(ohdr, ptr) {
2337 if (ohdr->headertype == OPT_HDR_V1_SECURE_TYPE) {
2338 fprintf(f, "#SECURE_HEADER\n");
2339 } else if (ohdr->headertype == OPT_HDR_V1_BINARY_TYPE) {
2340 fprintf(f, "BINARY binary%d.bin", cur_idx);
2341 for (i = 0; i < ohdr->data[0]; i++)
2342 fprintf(f, " 0x%x", le32_to_cpu(((uint32_t *)ohdr->data)[i + 1]));
2343 offset = (unsigned)((uint8_t *)ohdr - (uint8_t *)mhdr) + 8 + 4 * ohdr->data[0];
2344 fprintf(f, " LOAD_ADDRESS 0x%08x\n", 0x40000000 + offset);
2345 fprintf(f, " # for CPU SHEEVA: LOAD_ADDRESS 0x%08x\n", 0x40004000 + offset);
2347 } else if (ohdr->headertype == OPT_HDR_V1_REGISTER_TYPE) {
2348 regset_hdr = (struct register_set_hdr_v1 *)ohdr;
2349 if (opt_hdr_v1_size(ohdr) > sizeof(*ohdr))
2350 regset_count = (opt_hdr_v1_size(ohdr) - sizeof(*ohdr)) /
2351 sizeof(regset_hdr->data[0].entry);
2354 for (i = 0; i < regset_count; i++)
2355 fprintf(f, "DATA 0x%08x 0x%08x\n",
2356 le32_to_cpu(regset_hdr->data[i].entry.address),
2357 le32_to_cpu(regset_hdr->data[i].entry.value));
2358 if (regset_count > 0) {
2359 if (regset_hdr->data[regset_count-1].last_entry.delay !=
2360 REGISTER_SET_HDR_OPT_DELAY_SDRAM_SETUP)
2361 fprintf(f, "DATA_DELAY %u\n",
2362 (unsigned)regset_hdr->data[regset_count-1].last_entry.delay);
2364 fprintf(f, "DATA_DELAY SDRAM_SETUP\n");
2369 if (version == 0 && !is_v0_ext && le16_to_cpu(mhdr0->ddrinitdelay))
2370 fprintf(f, "DDR_INIT_DELAY %u\n", (unsigned)le16_to_cpu(mhdr0->ddrinitdelay));
2372 for_each_ext_hdr_v0(ehdr0, ptr) {
2374 fprintf(f, "\nMATCH ADDRESS 0x%08x MASK 0x%08x VALUE 0x%08x\n",
2375 le32_to_cpu(ehdr0->match_addr),
2376 le32_to_cpu(ehdr0->match_mask),
2377 le32_to_cpu(ehdr0->match_value));
2378 if (ehdr0->rsvd1[0] || ehdr0->rsvd1[1] || ehdr0->rsvd1[2] ||
2379 ehdr0->rsvd1[3] || ehdr0->rsvd1[4] || ehdr0->rsvd1[5] ||
2380 ehdr0->rsvd1[6] || ehdr0->rsvd1[7])
2381 fprintf(f, "#DDR_RSVD1 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
2382 ehdr0->rsvd1[0], ehdr0->rsvd1[1], ehdr0->rsvd1[2],
2383 ehdr0->rsvd1[3], ehdr0->rsvd1[4], ehdr0->rsvd1[5],
2384 ehdr0->rsvd1[6], ehdr0->rsvd1[7]);
2385 if (ehdr0->rsvd2[0] || ehdr0->rsvd2[1] || ehdr0->rsvd2[2] ||
2386 ehdr0->rsvd2[3] || ehdr0->rsvd2[4] || ehdr0->rsvd2[5] ||
2388 fprintf(f, "#DDR_RSVD2 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
2389 ehdr0->rsvd2[0], ehdr0->rsvd2[1], ehdr0->rsvd2[2],
2390 ehdr0->rsvd2[3], ehdr0->rsvd2[4], ehdr0->rsvd2[5],
2392 if (ehdr0->ddrwritetype)
2393 fprintf(f, "DDR_WRITE_TYPE %u\n", (unsigned)ehdr0->ddrwritetype);
2394 if (ehdr0->ddrresetmpp)
2395 fprintf(f, "DDR_RESET_MPP 0x%x\n", (unsigned)ehdr0->ddrresetmpp);
2396 if (ehdr0->ddrclkenmpp)
2397 fprintf(f, "DDR_CLKEN_MPP 0x%x\n", (unsigned)ehdr0->ddrclkenmpp);
2398 if (ehdr0->ddrinitdelay)
2399 fprintf(f, "DDR_INIT_DELAY %u\n", (unsigned)ehdr0->ddrinitdelay);
2402 if (ehdr0->offset) {
2403 for (regdata = (struct ext_hdr_v0_reg *)((uint8_t *)ptr + ehdr0->offset);
2404 (uint8_t *)regdata < (uint8_t *)ptr + header_size &&
2405 (regdata->raddr || regdata->rdata);
2407 fprintf(f, "DATA 0x%08x 0x%08x\n", le32_to_cpu(regdata->raddr),
2408 le32_to_cpu(regdata->rdata));
2409 if ((uint8_t *)regdata != (uint8_t *)ptr + ehdr0->offset)
2410 fprintf(f, "DATA 0x0 0x0\n");
2413 if (le32_to_cpu(ehdr0->enddelay))
2414 fprintf(f, "DATA_DELAY %u\n", le32_to_cpu(ehdr0->enddelay));
2416 fprintf(f, "DATA_DELAY SDRAM_SETUP\n");
2420 for_each_bin_hdr_v0(bhdr0, ptr) {
2421 fprintf(f, "\nMATCH ADDRESS 0x%08x MASK 0x%08x VALUE 0x%08x\n",
2422 le32_to_cpu(bhdr0->match_addr),
2423 le32_to_cpu(bhdr0->match_mask),
2424 le32_to_cpu(bhdr0->match_value));
2426 fprintf(f, "BINARY binary%d.bin", cur_idx);
2427 params_count = fls4(bhdr0->params_flags & 0xF);
2428 for (i = 0; i < params_count; i++)
2429 fprintf(f, " 0x%x", (bhdr0->params[i] & (1 << i)) ? bhdr0->params[i] : 0);
2430 fprintf(f, " LOAD_ADDRESS 0x%08x", le32_to_cpu(bhdr0->destaddr));
2431 fprintf(f, " EXEC_ADDRESS 0x%08x", le32_to_cpu(bhdr0->execaddr));
2434 fprintf(f, "#BINARY_OFFSET 0x%x\n", le32_to_cpu(bhdr0->offset));
2435 fprintf(f, "#BINARY_SIZE 0x%x\n", le32_to_cpu(bhdr0->size));
2438 fprintf(f, "#BINARY_RSVD1 0x%x\n", (unsigned)bhdr0->rsvd1);
2440 fprintf(f, "#BINARY_RSVD2 0x%x\n", (unsigned)bhdr0->rsvd2);
2445 /* Undocumented reserved fields */
2447 if (version == 0 && (mhdr0->rsvd1[0] || mhdr0->rsvd1[1] || mhdr0->rsvd1[2]))
2448 fprintf(f, "#RSVD1 0x%x 0x%x 0x%x\n", (unsigned)mhdr0->rsvd1[0],
2449 (unsigned)mhdr0->rsvd1[1], (unsigned)mhdr0->rsvd1[2]);
2451 if (version == 0 && le16_to_cpu(mhdr0->rsvd2))
2452 fprintf(f, "#RSVD2 0x%x\n", (unsigned)le16_to_cpu(mhdr0->rsvd2));
2454 if (version != 0 && mhdr->reserved4)
2455 fprintf(f, "#RESERVED4 0x%x\n", (unsigned)mhdr->reserved4);
2457 if (version != 0 && mhdr->reserved5)
2458 fprintf(f, "#RESERVED5 0x%x\n", (unsigned)le16_to_cpu(mhdr->reserved5));
2465 static int kwbimage_extract_subimage(void *ptr, struct image_tool_params *params)
2467 struct main_hdr_v1 *mhdr = (struct main_hdr_v1 *)ptr;
2468 size_t header_size = kwbheader_size(ptr);
2469 struct bin_hdr_v0 *bhdr;
2470 struct opt_hdr_v1 *ohdr;
2471 int idx = params->pflag;
2477 /* Generate kwbimage config file when '-p -1' is specified */
2479 return kwbimage_generate_config(ptr, params);
2485 /* Extract data image when -p is not specified or when '-p 0' is specified */
2486 offset = le32_to_cpu(mhdr->srcaddr);
2488 if (mhdr->blockid == IBR_HDR_SATA_ID)
2491 if (mhdr->blockid == IBR_HDR_PEX_ID && offset == 0xFFFFFFFF)
2492 offset = header_size;
2494 image = (ulong)((uint8_t *)ptr + offset);
2495 size = le32_to_cpu(mhdr->blocksize) - 4;
2497 /* Extract N-th binary header executabe image when other '-p N' is specified */
2499 for_each_opt_hdr_v1(ohdr, ptr) {
2500 if (ohdr->headertype != OPT_HDR_V1_BINARY_TYPE)
2503 if (idx == cur_idx) {
2504 image = (ulong)&ohdr->data[4 + 4 * ohdr->data[0]];
2505 size = opt_hdr_v1_size(ohdr) - 12 - 4 * ohdr->data[0];
2511 for_each_bin_hdr_v0(bhdr, ptr) {
2512 if (idx == cur_idx) {
2513 image = (ulong)bhdr + bhdr->offset;
2521 fprintf(stderr, "Argument -p %d is invalid\n", idx);
2522 fprintf(stderr, "Available subimages:\n");
2523 fprintf(stderr, " -p -1 - kwbimage config file\n");
2524 fprintf(stderr, " -p 0 - data image\n");
2525 if (cur_idx - 1 > 0)
2526 fprintf(stderr, " -p N - Nth binary header image (totally: %d)\n",
2532 return imagetool_save_subimage(params->outfile, image, size);
2535 static int kwbimage_check_params(struct image_tool_params *params)
2537 if (!params->lflag && !params->iflag && !params->pflag &&
2538 (!params->imagename || !strlen(params->imagename))) {
2539 char *msg = "Configuration file for kwbimage creation omitted";
2541 fprintf(stderr, "Error:%s - %s\n", params->cmdname, msg);
2545 return (params->dflag && (params->fflag || params->lflag || params->skipcpy)) ||
2547 (params->lflag && (params->dflag || params->fflag));
2551 * kwbimage type parameters definition
2555 "Marvell MVEBU Boot Image support",
2558 kwbimage_check_params,
2559 kwbimage_verify_header,
2560 kwbimage_print_header,
2561 kwbimage_set_header,
2562 kwbimage_extract_subimage,
2563 kwbimage_check_image_types,