2 * Copyright 2015 Freescale Semiconductor, Inc.
4 * FSL USB HOST xHCI Controller
8 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm-generic/errno.h>
14 #include <linux/compat.h>
15 #include <linux/usb/xhci-fsl.h>
16 #include <linux/usb/dwc3.h>
19 /* Declare global data pointer */
20 DECLARE_GLOBAL_DATA_PTR;
22 static struct fsl_xhci fsl_xhci;
23 unsigned long ctr_addr[] = FSL_USB_XHCI_ADDR;
25 __weak int __board_usb_init(int index, enum usb_init_type init)
30 static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci)
34 ret = dwc3_core_init(fsl_xhci->dwc3_reg);
36 debug("%s:failed to initialize core\n", __func__);
40 /* We are hard-coding DWC3 core to Host Mode */
41 dwc3_set_mode(fsl_xhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
43 /* Set GFLADJ_30MHZ as 20h as per XHCI spec default value */
44 dwc3_set_fladj(fsl_xhci->dwc3_reg, GFLADJ_30MHZ_DEFAULT);
49 static int fsl_xhci_core_exit(struct fsl_xhci *fsl_xhci)
52 * Currently fsl socs do not support PHY shutdown from
53 * sw. But this support may be added in future socs.
58 int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
60 struct fsl_xhci *ctx = &fsl_xhci;
63 ctx->hcd = (struct xhci_hccr *)ctr_addr[index];
64 ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET);
66 ret = board_usb_init(index, USB_INIT_HOST);
68 puts("Failed to initialize board for USB\n");
72 ret = fsl_xhci_core_init(ctx);
74 puts("Failed to initialize xhci\n");
78 *hccr = (struct xhci_hccr *)ctx->hcd;
79 *hcor = (struct xhci_hcor *)((uintptr_t) *hccr
80 + HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
82 debug("fsl-xhci: init hccr %lx and hcor %lx hc_length %lx\n",
83 (uintptr_t)*hccr, (uintptr_t)*hcor,
84 (uintptr_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
89 void xhci_hcd_stop(int index)
91 struct fsl_xhci *ctx = &fsl_xhci;
93 fsl_xhci_core_exit(ctx);