drivers/net/fm/p5040.c

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #include <common.h>
   7 #include <phy.h>
   8 #include <fm_eth.h>
   9 #include <asm/io.h>
  10 #include <asm/immap_85xx.h>
  11 #include <asm/fsl_serdes.h>
  12
  13 u32 port_to_devdisr[] = {
  14         [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
  15         [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
  16         [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
  17         [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
  18         [FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5,
  19         [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1,
  20         [FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1,
  21         [FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2,
  22         [FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3,
  23         [FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4,
  24         [FM2_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC2_5,
  25         [FM2_10GEC1] = FSL_CORENET_DEVDISR2_10GEC2,
  26 };
  27
  28 static int is_device_disabled(enum fm_port port)
  29 {
  30         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  31         u32 devdisr2 = in_be32(&gur->devdisr2);
  32
  33         return port_to_devdisr[port] & devdisr2;
  34 }
  35
  36 void fman_disable_port(enum fm_port port)
  37 {
  38         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  39
  40         /* don't allow disabling of DTSEC1 as its needed for MDIO */
  41         if (port == FM1_DTSEC1)
  42                 return;
  43
  44         setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
  45 }
  46
  47 phy_interface_t fman_port_enet_if(enum fm_port port)
  48 {
  49         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  50         u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
  51
  52         if (is_device_disabled(port))
  53                 return PHY_INTERFACE_MODE_NONE;
  54
  55         if ((port == FM1_10GEC1) && (is_serdes_configured(XAUI_FM1)))
  56                 return PHY_INTERFACE_MODE_XGMII;
  57
  58         if ((port == FM2_10GEC1) && (is_serdes_configured(XAUI_FM2)))
  59                 return PHY_INTERFACE_MODE_XGMII;
  60
  61         /* handle RGMII first */
  62         if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) ==
  63                 FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII))
  64                 return PHY_INTERFACE_MODE_RGMII;
  65
  66         if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) ==
  67                 FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII))
  68                 return PHY_INTERFACE_MODE_MII;
  69
  70         if ((port == FM2_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
  71                 FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_RGMII))
  72                 return PHY_INTERFACE_MODE_RGMII;
  73
  74         if ((port == FM2_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
  75                 FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII))
  76                 return PHY_INTERFACE_MODE_MII;
  77
  78         switch (port) {
  79         case FM1_DTSEC1:
  80         case FM1_DTSEC2:
  81         case FM1_DTSEC3:
  82         case FM1_DTSEC4:
  83         case FM1_DTSEC5:
  84                 if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
  85                         return PHY_INTERFACE_MODE_SGMII;
  86                 break;
  87         case FM2_DTSEC1:
  88         case FM2_DTSEC2:
  89         case FM2_DTSEC3:
  90         case FM2_DTSEC4:
  91         case FM2_DTSEC5:
  92                 if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1))
  93                         return PHY_INTERFACE_MODE_SGMII;
  94                 break;
  95         default:
  96                 return PHY_INTERFACE_MODE_NONE;
  97         }
  98
  99         return PHY_INTERFACE_MODE_NONE;
 100 }