dts/upstream/src/arm64/renesas/condor-common.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for the Condor board with R-Car V3H
   4  *
   5  * Copyright (C) 2018 Renesas Electronics Corp.
   6  * Copyright (C) 2018 Cogent Embedded, Inc.
   7  */
   8 #include <dt-bindings/gpio/gpio.h>
   9
  10 / {
  11         aliases {
  12                 i2c0 = &i2c0;
  13                 i2c1 = &i2c1;
  14                 i2c2 = &i2c2;
  15                 i2c3 = &i2c3;
  16                 i2c4 = &i2c4;
  17                 i2c5 = &i2c5;
  18                 serial0 = &scif0;
  19                 ethernet0 = &gether;
  20         };
  21
  22         chosen {
  23                 stdout-path = "serial0:115200n8";
  24                 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
  25         };
  26
  27         d1_8v: regulator-2 {
  28                 compatible = "regulator-fixed";
  29                 regulator-name = "D1.8V";
  30                 regulator-min-microvolt = <1800000>;
  31                 regulator-max-microvolt = <1800000>;
  32                 regulator-boot-on;
  33                 regulator-always-on;
  34         };
  35
  36         d3_3v: regulator-0 {
  37                 compatible = "regulator-fixed";
  38                 regulator-name = "D3.3V";
  39                 regulator-min-microvolt = <3300000>;
  40                 regulator-max-microvolt = <3300000>;
  41                 regulator-boot-on;
  42                 regulator-always-on;
  43         };
  44
  45         hdmi-out {
  46                 compatible = "hdmi-connector";
  47                 type = "a";
  48
  49                 port {
  50                         hdmi_con: endpoint {
  51                                 remote-endpoint = <&adv7511_out>;
  52                         };
  53                 };
  54         };
  55
  56         lvds-decoder {
  57                 compatible = "thine,thc63lvd1024";
  58                 vcc-supply = <&d3_3v>;
  59
  60                 ports {
  61                         #address-cells = <1>;
  62                         #size-cells = <0>;
  63
  64                         port@0 {
  65                                 reg = <0>;
  66                                 thc63lvd1024_in: endpoint {
  67                                         remote-endpoint = <&lvds0_out>;
  68                                 };
  69                         };
  70
  71                         port@2 {
  72                                 reg = <2>;
  73                                 thc63lvd1024_out: endpoint {
  74                                         remote-endpoint = <&adv7511_in>;
  75                                 };
  76                         };
  77                 };
  78         };
  79
  80         memory@48000000 {
  81                 device_type = "memory";
  82                 /* first 128MB is reserved for secure area. */
  83                 reg = <0 0x48000000 0 0x78000000>;
  84         };
  85
  86         vddq_vin01: regulator-1 {
  87                 compatible = "regulator-fixed";
  88                 regulator-name = "VDDQ_VIN01";
  89                 regulator-min-microvolt = <1800000>;
  90                 regulator-max-microvolt = <1800000>;
  91                 regulator-boot-on;
  92                 regulator-always-on;
  93         };
  94
  95         x1_clk: x1-clock {
  96                 compatible = "fixed-clock";
  97                 #clock-cells = <0>;
  98                 clock-frequency = <148500000>;
  99         };
 100 };
 101
 102 &canfd {
 103         pinctrl-0 = <&canfd0_pins>;
 104         pinctrl-names = "default";
 105         status = "okay";
 106
 107         channel0 {
 108                 status = "okay";
 109         };
 110 };
 111
 112 &csi40 {
 113         status = "okay";
 114
 115         ports {
 116                 port@0 {
 117                         csi40_in: endpoint {
 118                                 clock-lanes = <0>;
 119                                 data-lanes = <1 2 3 4>;
 120                                 remote-endpoint = <&max9286_out0>;
 121                         };
 122                 };
 123         };
 124 };
 125
 126 &csi41 {
 127         status = "okay";
 128
 129         ports {
 130                 port@0 {
 131                         csi41_in: endpoint {
 132                                 clock-lanes = <0>;
 133                                 data-lanes = <1 2 3 4>;
 134                                 remote-endpoint = <&max9286_out1>;
 135                         };
 136                 };
 137         };
 138 };
 139
 140 &du {
 141         clocks = <&cpg CPG_MOD 724>,
 142                  <&x1_clk>;
 143         clock-names = "du.0", "dclkin.0";
 144         status = "okay";
 145 };
 146
 147 &extal_clk {
 148         clock-frequency = <16666666>;
 149 };
 150
 151 &extalr_clk {
 152         clock-frequency = <32768>;
 153 };
 154
 155 &gether {
 156         pinctrl-0 = <&gether_pins>;
 157         pinctrl-names = "default";
 158
 159         phy-mode = "rgmii-id";
 160         phy-handle = <&phy0>;
 161         renesas,no-ether-link;
 162         status = "okay";
 163
 164         phy0: ethernet-phy@0 {
 165                 compatible = "ethernet-phy-id0022.1622",
 166                              "ethernet-phy-ieee802.3-c22";
 167                 rxc-skew-ps = <1500>;
 168                 reg = <0>;
 169                 interrupt-parent = <&gpio4>;
 170                 interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
 171                 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
 172         };
 173 };
 174
 175 &i2c0 {
 176         pinctrl-0 = <&i2c0_pins>;
 177         pinctrl-names = "default";
 178
 179         status = "okay";
 180         clock-frequency = <400000>;
 181
 182         io_expander0: gpio@20 {
 183                 compatible = "onnn,pca9654";
 184                 reg = <0x20>;
 185                 gpio-controller;
 186                 #gpio-cells = <2>;
 187         };
 188
 189         io_expander1: gpio@21 {
 190                 compatible = "onnn,pca9654";
 191                 reg = <0x21>;
 192                 gpio-controller;
 193                 #gpio-cells = <2>;
 194         };
 195
 196         hdmi@39 {
 197                 compatible = "adi,adv7511w";
 198                 reg = <0x39>;
 199                 interrupt-parent = <&gpio1>;
 200                 interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
 201                 avdd-supply = <&d1_8v>;
 202                 dvdd-supply = <&d1_8v>;
 203                 pvdd-supply = <&d1_8v>;
 204                 bgvdd-supply = <&d1_8v>;
 205                 dvdd-3v-supply = <&d3_3v>;
 206
 207                 adi,input-depth = <8>;
 208                 adi,input-colorspace = "rgb";
 209                 adi,input-clock = "1x";
 210
 211                 ports {
 212                         #address-cells = <1>;
 213                         #size-cells = <0>;
 214
 215                         port@0 {
 216                                 reg = <0>;
 217                                 adv7511_in: endpoint {
 218                                         remote-endpoint = <&thc63lvd1024_out>;
 219                                 };
 220                         };
 221
 222                         port@1 {
 223                                 reg = <1>;
 224                                 adv7511_out: endpoint {
 225                                         remote-endpoint = <&hdmi_con>;
 226                                 };
 227                         };
 228                 };
 229         };
 230
 231         eeprom@50 {
 232                 compatible = "rohm,br24t01", "atmel,24c01";
 233                 reg = <0x50>;
 234                 pagesize = <8>;
 235         };
 236 };
 237
 238 &i2c1 {
 239         pinctrl-0 = <&i2c1_pins>;
 240         pinctrl-names = "default";
 241
 242         status = "okay";
 243         clock-frequency = <400000>;
 244
 245         gmsl0: gmsl-deserializer@48 {
 246                 compatible = "maxim,max9286";
 247                 reg = <0x48>;
 248
 249                 maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>;
 250                 enable-gpios = <&io_expander0 0 GPIO_ACTIVE_HIGH>;
 251
 252                 ports {
 253                         #address-cells = <1>;
 254                         #size-cells = <0>;
 255
 256                         port@0 {
 257                                 reg = <0>;
 258                         };
 259
 260                         port@1 {
 261                                 reg = <1>;
 262                         };
 263
 264                         port@2 {
 265                                 reg = <2>;
 266                         };
 267
 268                         port@3 {
 269                                 reg = <3>;
 270                         };
 271
 272                         port@4 {
 273                                 reg = <4>;
 274                                 max9286_out0: endpoint {
 275                                         clock-lanes = <0>;
 276                                         data-lanes = <1 2 3 4>;
 277                                         remote-endpoint = <&csi40_in>;
 278                                 };
 279                         };
 280                 };
 281
 282                 i2c-mux {
 283                         #address-cells = <1>;
 284                         #size-cells = <0>;
 285
 286                         i2c@0 {
 287                                 #address-cells = <1>;
 288                                 #size-cells = <0>;
 289                                 reg = <0>;
 290
 291                                 status = "disabled";
 292                         };
 293
 294                         i2c@1 {
 295                                 #address-cells = <1>;
 296                                 #size-cells = <0>;
 297                                 reg = <1>;
 298
 299                                 status = "disabled";
 300                         };
 301
 302                         i2c@2 {
 303                                 #address-cells = <1>;
 304                                 #size-cells = <0>;
 305                                 reg = <2>;
 306
 307                                 status = "disabled";
 308                         };
 309
 310                         i2c@3 {
 311                                 #address-cells = <1>;
 312                                 #size-cells = <0>;
 313                                 reg = <3>;
 314
 315                                 status = "disabled";
 316                         };
 317                 };
 318         };
 319
 320         gmsl1: gmsl-deserializer@4a {
 321                 compatible = "maxim,max9286";
 322                 reg = <0x4a>;
 323
 324                 maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>;
 325                 enable-gpios = <&io_expander1 0 GPIO_ACTIVE_HIGH>;
 326
 327                 ports {
 328                         #address-cells = <1>;
 329                         #size-cells = <0>;
 330
 331                         port@0 {
 332                                 reg = <0>;
 333                         };
 334
 335                         port@1 {
 336                                 reg = <1>;
 337                         };
 338
 339                         port@2 {
 340                                 reg = <2>;
 341                         };
 342
 343                         port@3 {
 344                                 reg = <3>;
 345                         };
 346
 347                         port@4 {
 348                                 reg = <4>;
 349                                 max9286_out1: endpoint {
 350                                         clock-lanes = <0>;
 351                                         data-lanes = <1 2 3 4>;
 352                                         remote-endpoint = <&csi41_in>;
 353                                 };
 354                         };
 355                 };
 356
 357                 i2c-mux {
 358                         #address-cells = <1>;
 359                         #size-cells = <0>;
 360
 361                         i2c@0 {
 362                                 #address-cells = <1>;
 363                                 #size-cells = <0>;
 364                                 reg = <0>;
 365
 366                                 status = "disabled";
 367                         };
 368
 369                         i2c@1 {
 370                                 #address-cells = <1>;
 371                                 #size-cells = <0>;
 372                                 reg = <1>;
 373
 374                                 status = "disabled";
 375                         };
 376
 377                         i2c@2 {
 378                                 #address-cells = <1>;
 379                                 #size-cells = <0>;
 380                                 reg = <2>;
 381
 382                                 status = "disabled";
 383                         };
 384
 385                         i2c@3 {
 386                                 #address-cells = <1>;
 387                                 #size-cells = <0>;
 388                                 reg = <3>;
 389
 390                                 status = "disabled";
 391                         };
 392                 };
 393         };
 394 };
 395
 396 &lvds0 {
 397         status = "okay";
 398
 399         ports {
 400                 port@1 {
 401                         lvds0_out: endpoint {
 402                                 remote-endpoint = <&thc63lvd1024_in>;
 403                         };
 404                 };
 405         };
 406 };
 407
 408 &mmc0 {
 409         pinctrl-0 = <&mmc_pins>;
 410         pinctrl-1 = <&mmc_pins>;
 411         pinctrl-names = "default", "state_uhs";
 412
 413         vmmc-supply = <&d3_3v>;
 414         vqmmc-supply = <&vddq_vin01>;
 415         mmc-hs200-1_8v;
 416         bus-width = <8>;
 417         no-sd;
 418         no-sdio;
 419         non-removable;
 420         status = "okay";
 421 };
 422
 423 &pciec {
 424         status = "okay";
 425 };
 426
 427 &pcie_bus_clk {
 428         clock-frequency = <100000000>;
 429 };
 430
 431 &pcie_phy {
 432         status = "okay";
 433 };
 434
 435 &pfc {
 436         canfd0_pins: canfd0 {
 437                 groups = "canfd0_data_a";
 438                 function = "canfd0";
 439         };
 440
 441         gether_pins: gether {
 442                 groups = "gether_mdio_a", "gether_rgmii",
 443                          "gether_txcrefclk", "gether_txcrefclk_mega";
 444                 function = "gether";
 445         };
 446
 447         i2c0_pins: i2c0 {
 448                 groups = "i2c0";
 449                 function = "i2c0";
 450         };
 451
 452         i2c1_pins: i2c1 {
 453                 groups = "i2c1";
 454                 function = "i2c1";
 455         };
 456
 457         mmc_pins: mmc {
 458                 groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
 459                 function = "mmc";
 460                 power-source = <1800>;
 461         };
 462
 463         qspi0_pins: qspi0 {
 464                 groups = "qspi0_ctrl", "qspi0_data4";
 465                 function = "qspi0";
 466         };
 467
 468         scif0_pins: scif0 {
 469                 groups = "scif0_data";
 470                 function = "scif0";
 471         };
 472
 473         scif_clk_pins: scif_clk {
 474                 groups = "scif_clk_b";
 475                 function = "scif_clk";
 476         };
 477 };
 478
 479 &rpc {
 480         pinctrl-0 = <&qspi0_pins>;
 481         pinctrl-names = "default";
 482
 483         status = "okay";
 484
 485         flash@0 {
 486                 compatible = "spansion,s25fs512s", "jedec,spi-nor";
 487                 reg = <0>;
 488                 spi-max-frequency = <50000000>;
 489                 spi-rx-bus-width = <4>;
 490
 491                 partitions {
 492                         compatible = "fixed-partitions";
 493                         #address-cells = <1>;
 494                         #size-cells = <1>;
 495
 496                         bootparam@0 {
 497                                 reg = <0x00000000 0x040000>;
 498                                 read-only;
 499                         };
 500                         cr7@40000 {
 501                                 reg = <0x00040000 0x080000>;
 502                                 read-only;
 503                         };
 504                         cert_header_sa3@c0000 {
 505                                 reg = <0x000c0000 0x080000>;
 506                                 read-only;
 507                         };
 508                         bl2@140000 {
 509                                 reg = <0x00140000 0x040000>;
 510                                 read-only;
 511                         };
 512                         cert_header_sa6@180000 {
 513                                 reg = <0x00180000 0x040000>;
 514                                 read-only;
 515                         };
 516                         bl31@1c0000 {
 517                                 reg = <0x001c0000 0x460000>;
 518                                 read-only;
 519                         };
 520                         uboot@640000 {
 521                                 reg = <0x00640000 0x0c0000>;
 522                                 read-only;
 523                         };
 524                         uboot-env@700000 {
 525                                 reg = <0x00700000 0x040000>;
 526                                 read-only;
 527                         };
 528                         dtb@740000 {
 529                                 reg = <0x00740000 0x080000>;
 530                         };
 531                         kernel@7c0000 {
 532                                 reg = <0x007c0000 0x1400000>;
 533                         };
 534                         user@1bc0000 {
 535                                 reg = <0x01bc0000 0x2440000>;
 536                         };
 537                 };
 538         };
 539 };
 540
 541 &rwdt {
 542         timeout-sec = <60>;
 543         status = "okay";
 544 };
 545
 546 &scif0 {
 547         pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
 548         pinctrl-names = "default";
 549
 550         status = "okay";
 551 };
 552
 553 &scif_clk {
 554         clock-frequency = <14745600>;
 555 };