1 // SPDX-License-Identifier: GPL-2.0
3 * MediaTek timer driver
5 * Copyright (C) 2018 MediaTek Inc.
14 #include <linux/bitops.h>
16 #define MTK_GPT4_CTRL 0x40
17 #define MTK_GPT4_CLK 0x44
18 #define MTK_GPT4_CNT 0x48
20 #define GPT4_ENABLE BIT(0)
21 #define GPT4_CLEAR BIT(1)
22 #define GPT4_FREERUN GENMASK(5, 4)
23 #define GPT4_CLK_SYS 0x0
24 #define GPT4_CLK_DIV1 0x0
26 struct mtk_timer_priv {
30 static u64 mtk_timer_get_count(struct udevice *dev)
32 struct mtk_timer_priv *priv = dev_get_priv(dev);
33 u32 val = readl(priv->base + MTK_GPT4_CNT);
35 return timer_conv_64(val);
38 static int mtk_timer_probe(struct udevice *dev)
40 struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
41 struct mtk_timer_priv *priv = dev_get_priv(dev);
42 struct clk clk, parent;
45 priv->base = dev_read_addr_ptr(dev);
49 ret = clk_get_by_index(dev, 0, &clk);
53 ret = clk_get_by_index(dev, 1, &parent);
55 ret = clk_set_parent(&clk, &parent);
60 uc_priv->clock_rate = clk_get_rate(&clk);
61 if (!uc_priv->clock_rate)
67 static const struct timer_ops mtk_timer_ops = {
68 .get_count = mtk_timer_get_count,
71 static const struct udevice_id mtk_timer_ids[] = {
72 { .compatible = "mediatek,timer" },
73 { .compatible = "mediatek,mt6577-timer" },
77 U_BOOT_DRIVER(mtk_timer) = {
80 .of_match = mtk_timer_ids,
81 .priv_auto = sizeof(struct mtk_timer_priv),
82 .probe = mtk_timer_probe,
83 .ops = &mtk_timer_ops,
84 .flags = DM_FLAG_PRE_RELOC,