board/advantech/dms-ba16/dms-ba16.c

   1 /*
   2  * Copyright 2016 Timesys Corporation
   3  * Copyright 2016 Advantech Corporation
   4  * Copyright 2012 Freescale Semiconductor, Inc.
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/imx-regs.h>
  11 #include <asm/arch/iomux.h>
  12 #include <asm/arch/mx6-pins.h>
  13 #include <linux/errno.h>
  14 #include <asm/gpio.h>
  15 #include <asm/imx-common/mxc_i2c.h>
  16 #include <asm/imx-common/iomux-v3.h>
  17 #include <asm/imx-common/boot_mode.h>
  18 #include <asm/imx-common/video.h>
  19 #include <mmc.h>
  20 #include <fsl_esdhc.h>
  21 #include <miiphy.h>
  22 #include <netdev.h>
  23 #include <asm/arch/mxc_hdmi.h>
  24 #include <asm/arch/crm_regs.h>
  25 #include <asm/io.h>
  26 #include <asm/arch/sys_proto.h>
  27 #include <i2c.h>
  28 #include <pwm.h>
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 #define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP |      \
  32         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  33         PAD_CTL_HYS)
  34
  35 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  36         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  37         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  38
  39 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  40         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  41         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  42
  43 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
  44         PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
  45
  46 #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
  47         PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
  48
  49 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  50         PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
  51
  52 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  53                       PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  54
  55 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                    \
  56         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  57         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  58
  59 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
  60
  61 int dram_init(void)
  62 {
  63         gd->ram_size = imx_ddr_size();
  64
  65         return 0;
  66 }
  67
  68 static iomux_v3_cfg_t const uart3_pads[] = {
  69         MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  70         MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  71         MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  72         MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  73 };
  74
  75 static iomux_v3_cfg_t const uart4_pads[] = {
  76         MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  77         MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  78 };
  79
  80 static iomux_v3_cfg_t const enet_pads[] = {
  81         MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  82         MX6_PAD_ENET_MDC__ENET_MDC   | MUX_PAD_CTRL(ENET_PAD_CTRL),
  83         MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  84         MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  85         MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  86         MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  87         MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  88         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  89         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK  | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
  90         MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  91         MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  92         MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  93         MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  94         MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  95         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  96         /* AR8033 PHY Reset */
  97         MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
  98 };
  99
 100 static void setup_iomux_enet(void)
 101 {
 102         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 103
 104         /* Reset AR8033 PHY */
 105         gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
 106         udelay(500);
 107         gpio_set_value(IMX_GPIO_NR(1, 28), 1);
 108 }
 109
 110 static iomux_v3_cfg_t const usdhc2_pads[] = {
 111         MX6_PAD_SD2_CLK__SD2_CLK        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 112         MX6_PAD_SD2_CMD__SD2_CMD        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 113         MX6_PAD_SD2_DAT0__SD2_DATA0     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 114         MX6_PAD_SD2_DAT1__SD2_DATA1     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 115         MX6_PAD_SD2_DAT2__SD2_DATA2     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 116         MX6_PAD_SD2_DAT3__SD2_DATA3     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 117         MX6_PAD_GPIO_4__GPIO1_IO04      | MUX_PAD_CTRL(NO_PAD_CTRL),
 118 };
 119
 120 static iomux_v3_cfg_t const usdhc3_pads[] = {
 121         MX6_PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 122         MX6_PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 123         MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 124         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 125         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 126         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 127         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 128         MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 129         MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 130         MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 131         MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 132 };
 133
 134 static iomux_v3_cfg_t const usdhc4_pads[] = {
 135         MX6_PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 136         MX6_PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 137         MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 138         MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 139         MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 140         MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 141         MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 142         MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 143         MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 144         MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 145         MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
 146         MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
 147 };
 148
 149 static iomux_v3_cfg_t const ecspi1_pads[] = {
 150         MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 151         MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 152         MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 153         MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
 154 };
 155
 156 static struct i2c_pads_info i2c_pad_info1 = {
 157         .scl = {
 158                 .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
 159                 .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD,
 160                 .gp = IMX_GPIO_NR(5, 27)
 161         },
 162         .sda = {
 163                 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD,
 164                 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD,
 165                 .gp = IMX_GPIO_NR(5, 26)
 166         }
 167 };
 168
 169 static struct i2c_pads_info i2c_pad_info2 = {
 170         .scl = {
 171                 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
 172                 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
 173                 .gp = IMX_GPIO_NR(4, 12)
 174         },
 175         .sda = {
 176                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
 177                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
 178                 .gp = IMX_GPIO_NR(4, 13)
 179         }
 180 };
 181
 182 static struct i2c_pads_info i2c_pad_info3 = {
 183         .scl = {
 184                 .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD,
 185                 .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD,
 186                 .gp = IMX_GPIO_NR(1, 3)
 187         },
 188         .sda = {
 189                 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
 190                 .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
 191                 .gp = IMX_GPIO_NR(1, 6)
 192         }
 193 };
 194
 195 #ifdef CONFIG_MXC_SPI
 196 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 197 {
 198         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
 199 }
 200
 201 static void setup_spi(void)
 202 {
 203         imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
 204 }
 205 #endif
 206
 207 static iomux_v3_cfg_t const pcie_pads[] = {
 208         MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
 209         MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
 210 };
 211
 212 static void setup_pcie(void)
 213 {
 214         imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
 215 }
 216
 217 static void setup_iomux_uart(void)
 218 {
 219         imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
 220         imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
 221 }
 222
 223 #ifdef CONFIG_FSL_ESDHC
 224 struct fsl_esdhc_cfg usdhc_cfg[3] = {
 225         {USDHC2_BASE_ADDR},
 226         {USDHC3_BASE_ADDR},
 227         {USDHC4_BASE_ADDR},
 228 };
 229
 230 #define USDHC2_CD_GPIO  IMX_GPIO_NR(1, 4)
 231 #define USDHC4_CD_GPIO  IMX_GPIO_NR(6, 11)
 232
 233 int board_mmc_getcd(struct mmc *mmc)
 234 {
 235         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 236         int ret = 0;
 237
 238         switch (cfg->esdhc_base) {
 239         case USDHC2_BASE_ADDR:
 240                 ret = !gpio_get_value(USDHC2_CD_GPIO);
 241                 break;
 242         case USDHC3_BASE_ADDR:
 243                 ret = 1; /* eMMC is always present */
 244                 break;
 245         case USDHC4_BASE_ADDR:
 246                 ret = !gpio_get_value(USDHC4_CD_GPIO);
 247                 break;
 248         }
 249
 250         return ret;
 251 }
 252
 253 int board_mmc_init(bd_t *bis)
 254 {
 255         int ret;
 256         int i;
 257
 258         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 259                 switch (i) {
 260                 case 0:
 261                         imx_iomux_v3_setup_multiple_pads(
 262                                 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 263                         gpio_direction_input(USDHC2_CD_GPIO);
 264                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 265                         break;
 266                 case 1:
 267                         imx_iomux_v3_setup_multiple_pads(
 268                                 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 269                         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 270                         break;
 271                 case 2:
 272                         imx_iomux_v3_setup_multiple_pads(
 273                                 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 274                         gpio_direction_input(USDHC4_CD_GPIO);
 275                         usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 276                         break;
 277                 default:
 278                         printf("Warning: you configured more USDHC controllers\n"
 279                                "(%d) then supported by the board (%d)\n",
 280                                i + 1, CONFIG_SYS_FSL_USDHC_NUM);
 281                         return -EINVAL;
 282                 }
 283
 284                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 285                 if (ret)
 286                         return ret;
 287         }
 288
 289         return 0;
 290 }
 291 #endif
 292
 293 static int mx6_rgmii_rework(struct phy_device *phydev)
 294 {
 295         /* set device address 0x7 */
 296         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 297         /* offset 0x8016: CLK_25M Clock Select */
 298         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 299         /* enable register write, no post increment, address 0x7 */
 300         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 301         /* set to 125 MHz from local PLL source */
 302         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);
 303         /* set debug port address: SerDes Test and System Mode Control */
 304         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
 305         /* enable rgmii tx clock delay */
 306         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
 307
 308         return 0;
 309 }
 310
 311 int board_phy_config(struct phy_device *phydev)
 312 {
 313         mx6_rgmii_rework(phydev);
 314
 315         if (phydev->drv->config)
 316                 phydev->drv->config(phydev);
 317
 318         return 0;
 319 }
 320
 321 #if defined(CONFIG_VIDEO_IPUV3)
 322 static iomux_v3_cfg_t const backlight_pads[] = {
 323         /* Power for LVDS Display */
 324         MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
 325 #define LVDS_POWER_GP IMX_GPIO_NR(3, 22)
 326         /* Backlight enable for LVDS display */
 327         MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
 328 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0)
 329         /* backlight PWM brightness control */
 330         MX6_PAD_SD1_DAT3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
 331 };
 332
 333 static void do_enable_hdmi(struct display_info_t const *dev)
 334 {
 335         imx_enable_hdmi_phy();
 336 }
 337
 338 int board_cfb_skip(void)
 339 {
 340         gpio_direction_output(LVDS_POWER_GP, 1);
 341
 342         return 0;
 343 }
 344
 345 static int detect_baseboard(struct display_info_t const *dev)
 346 {
 347         return 0 == dev->addr;
 348 }
 349
 350 struct display_info_t const displays[] = {{
 351         .bus    = -1,
 352         .addr   = 0,
 353         .pixfmt = IPU_PIX_FMT_RGB24,
 354         .detect = detect_baseboard,
 355         .enable = NULL,
 356         .mode   = {
 357                 .name           = "SHARP-LQ156M1LG21",
 358                 .refresh        = 60,
 359                 .xres           = 1920,
 360                 .yres           = 1080,
 361                 .pixclock       = 7851,
 362                 .left_margin    = 100,
 363                 .right_margin   = 40,
 364                 .upper_margin   = 30,
 365                 .lower_margin   = 3,
 366                 .hsync_len      = 10,
 367                 .vsync_len      = 2,
 368                 .sync           = FB_SYNC_EXT,
 369                 .vmode          = FB_VMODE_NONINTERLACED
 370 } }, {
 371         .bus    = -1,
 372         .addr   = 3,
 373         .pixfmt = IPU_PIX_FMT_RGB24,
 374         .detect = detect_hdmi,
 375         .enable = do_enable_hdmi,
 376         .mode   = {
 377                 .name           = "HDMI",
 378                 .refresh        = 60,
 379                 .xres           = 1024,
 380                 .yres           = 768,
 381                 .pixclock       = 15385,
 382                 .left_margin    = 220,
 383                 .right_margin   = 40,
 384                 .upper_margin   = 21,
 385                 .lower_margin   = 7,
 386                 .hsync_len      = 60,
 387                 .vsync_len      = 10,
 388                 .sync           = FB_SYNC_EXT,
 389                 .vmode          = FB_VMODE_NONINTERLACED
 390 } } };
 391 size_t display_count = ARRAY_SIZE(displays);
 392
 393 static void setup_display(void)
 394 {
 395         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 396         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 397
 398         clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
 399
 400         imx_setup_hdmi();
 401
 402         /* Set LDB_DI0 as clock source for IPU_DI0 */
 403         clrsetbits_le32(&mxc_ccm->chsccdr,
 404                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
 405                         (CHSCCDR_CLK_SEL_LDB_DI0 <<
 406                          MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
 407
 408         /* Turn on IPU LDB DI0 clocks */
 409         setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 410
 411         enable_ipu_clock();
 412
 413         writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
 414                IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH |
 415                IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
 416                IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
 417                IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
 418                IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
 419                IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
 420                IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
 421                IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
 422                IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
 423                &iomux->gpr[2]);
 424
 425         clrsetbits_le32(&iomux->gpr[3],
 426                         IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
 427                         IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
 428                         IOMUXC_GPR3_HDMI_MUX_CTL_MASK,
 429                        (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
 430                         IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
 431
 432         /* backlights off until needed */
 433         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 434                                          ARRAY_SIZE(backlight_pads));
 435
 436         gpio_direction_input(LVDS_POWER_GP);
 437         gpio_direction_input(LVDS_BACKLIGHT_GP);
 438 }
 439 #endif /* CONFIG_VIDEO_IPUV3 */
 440
 441 /*
 442  * Do not overwrite the console
 443  * Use always serial for U-Boot console
 444  */
 445 int overwrite_console(void)
 446 {
 447         return 1;
 448 }
 449
 450 int board_eth_init(bd_t *bis)
 451 {
 452         setup_iomux_enet();
 453         setup_pcie();
 454
 455         return cpu_eth_init(bis);
 456 }
 457
 458 static iomux_v3_cfg_t const misc_pads[] = {
 459         MX6_PAD_KEY_ROW2__GPIO4_IO11    | MUX_PAD_CTRL(NO_PAD_CTRL),
 460         MX6_PAD_EIM_A25__GPIO5_IO02     | MUX_PAD_CTRL(NC_PAD_CTRL),
 461         MX6_PAD_EIM_CS0__GPIO2_IO23     | MUX_PAD_CTRL(NC_PAD_CTRL),
 462         MX6_PAD_EIM_CS1__GPIO2_IO24     | MUX_PAD_CTRL(NC_PAD_CTRL),
 463         MX6_PAD_EIM_OE__GPIO2_IO25      | MUX_PAD_CTRL(NC_PAD_CTRL),
 464         MX6_PAD_EIM_BCLK__GPIO6_IO31    | MUX_PAD_CTRL(NC_PAD_CTRL),
 465         MX6_PAD_GPIO_1__GPIO1_IO01      | MUX_PAD_CTRL(NC_PAD_CTRL),
 466 };
 467 #define SUS_S3_OUT      IMX_GPIO_NR(4, 11)
 468 #define WIFI_EN IMX_GPIO_NR(6, 14)
 469
 470 int setup_ba16_sata(void)
 471 {
 472         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 473         int ret;
 474
 475         ret = enable_sata_clock();
 476         if (ret)
 477                 return ret;
 478
 479         clrsetbits_le32(&iomuxc_regs->gpr[13],
 480                         IOMUXC_GPR13_SATA_MASK,
 481                         IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
 482                         |IOMUXC_GPR13_SATA_PHY_7_SATA2M
 483                         |IOMUXC_GPR13_SATA_SPEED_3G
 484                         |(1<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
 485                         |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
 486                         |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_12_16
 487                         |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB
 488                         |IOMUXC_GPR13_SATA_PHY_2_TX_1P133V
 489                         |IOMUXC_GPR13_SATA_PHY_1_SLOW);
 490
 491         return 0;
 492 }
 493
 494 int board_early_init_f(void)
 495 {
 496         imx_iomux_v3_setup_multiple_pads(misc_pads,
 497                                          ARRAY_SIZE(misc_pads));
 498
 499         setup_iomux_uart();
 500
 501 #if defined(CONFIG_VIDEO_IPUV3)
 502         /* Set LDB clock to PLL2 PFD0 */
 503         select_ldb_di_clock_source(MXC_PLL2_PFD0_CLK);
 504 #endif
 505         return 0;
 506 }
 507
 508 int board_init(void)
 509 {
 510         gpio_direction_output(SUS_S3_OUT, 1);
 511         gpio_direction_output(WIFI_EN, 1);
 512 #if defined(CONFIG_VIDEO_IPUV3)
 513         setup_display();
 514 #endif
 515         /* address of boot parameters */
 516         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 517
 518 #ifdef CONFIG_MXC_SPI
 519         setup_spi();
 520 #endif
 521         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 522         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 523         setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
 524
 525         return 0;
 526 }
 527
 528 #ifdef CONFIG_CMD_BMODE
 529 static const struct boot_mode board_boot_modes[] = {
 530         /* 4 bit bus width */
 531         {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 532         {"sd3",  MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 533         {NULL,   0},
 534 };
 535 #endif
 536
 537 int board_late_init(void)
 538 {
 539 #ifdef CONFIG_CMD_BMODE
 540         add_board_boot_modes(board_boot_modes);
 541 #endif
 542         /*
 543          * We need at least 200ms between power on and backlight on
 544          * as per specifications from CHI MEI
 545          */
 546         mdelay(250);
 547
 548         /* enable backlight PWM 1 */
 549         pwm_init(0, 0, 0);
 550
 551         /* duty cycle 5000000ns, period: 5000000ns */
 552         pwm_config(0, 5000000, 5000000);
 553
 554         /* Backlight Power */
 555         gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
 556
 557         pwm_enable(0);
 558
 559 #ifdef CONFIG_CMD_SATA
 560         setup_ba16_sata();
 561 #endif
 562
 563         return 0;
 564 }
 565
 566 int checkboard(void)
 567 {
 568         printf("BOARD: %s\n", CONFIG_BOARD_NAME);
 569         return 0;
 570 }