drivers/clk/sunxi/clk_a10.c

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (C) 2018 Amarula Solutions.
   4  * Author: Jagan Teki <[email protected]>
   5  */
   6
   7 #include <clk-uclass.h>
   8 #include <dm.h>
   9 #include <errno.h>
  10 #include <clk/sunxi.h>
  11 #include <dt-bindings/clock/sun4i-a10-ccu.h>
  12 #include <dt-bindings/reset/sun4i-a10-ccu.h>
  13 #include <linux/bitops.h>
  14
  15 static struct ccu_clk_gate a10_gates[] = {
  16         [CLK_AHB_OTG]           = GATE(0x060, BIT(0)),
  17         [CLK_AHB_EHCI0]         = GATE(0x060, BIT(1)),
  18         [CLK_AHB_OHCI0]         = GATE(0x060, BIT(2)),
  19         [CLK_AHB_EHCI1]         = GATE(0x060, BIT(3)),
  20         [CLK_AHB_OHCI1]         = GATE(0x060, BIT(4)),
  21         [CLK_AHB_MMC0]          = GATE(0x060, BIT(8)),
  22         [CLK_AHB_MMC1]          = GATE(0x060, BIT(9)),
  23         [CLK_AHB_MMC2]          = GATE(0x060, BIT(10)),
  24         [CLK_AHB_MMC3]          = GATE(0x060, BIT(11)),
  25         [CLK_AHB_NAND]          = GATE(0x060, BIT(13)),
  26         [CLK_AHB_EMAC]          = GATE(0x060, BIT(17)),
  27         [CLK_AHB_SPI0]          = GATE(0x060, BIT(20)),
  28         [CLK_AHB_SPI1]          = GATE(0x060, BIT(21)),
  29         [CLK_AHB_SPI2]          = GATE(0x060, BIT(22)),
  30         [CLK_AHB_SPI3]          = GATE(0x060, BIT(23)),
  31
  32         [CLK_AHB_GMAC]          = GATE(0x064, BIT(17)),
  33
  34         [CLK_APB0_PIO]          = GATE(0x068, BIT(5)),
  35
  36         [CLK_APB1_I2C0]         = GATE(0x06c, BIT(0)),
  37         [CLK_APB1_I2C1]         = GATE(0x06c, BIT(1)),
  38         [CLK_APB1_I2C2]         = GATE(0x06c, BIT(2)),
  39         [CLK_APB1_I2C3]         = GATE(0x06c, BIT(3)),
  40         [CLK_APB1_I2C4]         = GATE(0x06c, BIT(15)),
  41         [CLK_APB1_UART0]        = GATE(0x06c, BIT(16)),
  42         [CLK_APB1_UART1]        = GATE(0x06c, BIT(17)),
  43         [CLK_APB1_UART2]        = GATE(0x06c, BIT(18)),
  44         [CLK_APB1_UART3]        = GATE(0x06c, BIT(19)),
  45         [CLK_APB1_UART4]        = GATE(0x06c, BIT(20)),
  46         [CLK_APB1_UART5]        = GATE(0x06c, BIT(21)),
  47         [CLK_APB1_UART6]        = GATE(0x06c, BIT(22)),
  48         [CLK_APB1_UART7]        = GATE(0x06c, BIT(23)),
  49
  50         [CLK_NAND]              = GATE(0x080, BIT(31)),
  51         [CLK_SPI0]              = GATE(0x0a0, BIT(31)),
  52         [CLK_SPI1]              = GATE(0x0a4, BIT(31)),
  53         [CLK_SPI2]              = GATE(0x0a8, BIT(31)),
  54
  55         [CLK_USB_OHCI0]         = GATE(0x0cc, BIT(6)),
  56         [CLK_USB_OHCI1]         = GATE(0x0cc, BIT(7)),
  57         [CLK_USB_PHY]           = GATE(0x0cc, BIT(8)),
  58
  59         [CLK_SPI3]              = GATE(0x0d4, BIT(31)),
  60 };
  61
  62 static struct ccu_reset a10_resets[] = {
  63         [RST_USB_PHY0]          = RESET(0x0cc, BIT(0)),
  64         [RST_USB_PHY1]          = RESET(0x0cc, BIT(1)),
  65         [RST_USB_PHY2]          = RESET(0x0cc, BIT(2)),
  66 };
  67
  68 const struct ccu_desc a10_ccu_desc = {
  69         .gates = a10_gates,
  70         .resets = a10_resets,
  71         .num_gates = ARRAY_SIZE(a10_gates),
  72         .num_resets = ARRAY_SIZE(a10_resets),
  73 };