board/boundary/nitrogen6x/nitrogen6x.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
   4  * Copyright (C) 2013, Boundary Devices <[email protected]>
   5  */
   6
   7 #include <command.h>
   8 #include <env.h>
   9 #include <init.h>
  10 #include <net.h>
  11 #include <asm/global_data.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/imx-regs.h>
  15 #include <asm/arch/iomux.h>
  16 #include <asm/arch/sys_proto.h>
  17 #include <malloc.h>
  18 #include <asm/arch/mx6-pins.h>
  19 #include <linux/delay.h>
  20 #include <linux/errno.h>
  21 #include <asm/gpio.h>
  22 #include <asm/mach-imx/iomux-v3.h>
  23 #include <asm/mach-imx/mxc_i2c.h>
  24 #include <asm/mach-imx/sata.h>
  25 #include <asm/mach-imx/spi.h>
  26 #include <asm/mach-imx/boot_mode.h>
  27 #include <asm/mach-imx/video.h>
  28 #include <fsl_esdhc_imx.h>
  29 #include <micrel.h>
  30 #include <miiphy.h>
  31 #include <netdev.h>
  32 #include <asm/arch/crm_regs.h>
  33 #include <asm/arch/mxc_hdmi.h>
  34 #include <i2c.h>
  35 #include <input.h>
  36 #include <netdev.h>
  37 #include <usb/ehci-ci.h>
  38
  39 DECLARE_GLOBAL_DATA_PTR;
  40 #define GP_USB_OTG_PWR  IMX_GPIO_NR(3, 22)
  41
  42 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  43         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  44         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  45
  46 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  47         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  48         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  49
  50 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  51         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  52
  53 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED |         \
  54         PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
  55
  56 #define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP |                  \
  57         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  58
  59 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP |                  \
  60         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  61         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  62
  63 #define RGB_PAD_CTRL    PAD_CTL_DSE_120ohm
  64
  65 #define WEAK_PULLUP     (PAD_CTL_PUS_100K_UP |                  \
  66         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  67         PAD_CTL_SRE_SLOW)
  68
  69 #define WEAK_PULLDOWN   (PAD_CTL_PUS_100K_DOWN |                \
  70         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  71         PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
  72
  73 #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
  74
  75 /* Prevent compiler error if gpio number 08 or 09 is used */
  76 #define not_octal(gp) ((((0x##gp >> 4) & 0xf) * 10) + ((0x##gp & 0xf)))
  77
  78 #define _I2C_PADS_INFO_CPU(cpu, i2cnum, scl_pad, scl_bank, scl_gp,             \
  79                 sda_pad, sda_bank, sda_gp, pad_ctrl, join_io) {                \
  80         .scl = {                                                               \
  81                 .i2c_mode = NEW_PAD_CTRL(cpu##_PAD_##scl_pad##__##i2cnum##_SCL,\
  82                                          pad_ctrl),                            \
  83                 .gpio_mode = NEW_PAD_CTRL(                                     \
  84                         cpu##_PAD_##scl_pad##__GPIO##scl_bank##join_io##scl_gp,\
  85                         pad_ctrl),                                             \
  86                 .gp = IMX_GPIO_NR(scl_bank, not_octal(scl_gp))                 \
  87         },                                                                     \
  88         .sda = {                                                               \
  89                 .i2c_mode = NEW_PAD_CTRL(cpu##_PAD_##sda_pad##__##i2cnum##_SDA,\
  90                                          pad_ctrl),                            \
  91                 .gpio_mode = NEW_PAD_CTRL(                                     \
  92                         cpu##_PAD_##sda_pad##__GPIO##sda_bank##join_io##sda_gp,\
  93                         pad_ctrl),                                             \
  94                         .gp = IMX_GPIO_NR(sda_bank, not_octal(sda_gp))         \
  95         }                                                                      \
  96 }
  97
  98 #define I2C_PADS_INFO_CPU(cpu, i2cnum, scl_pad, scl_bank, scl_gp,              \
  99                 sda_pad, sda_bank, sda_gp, pad_ctrl)                           \
 100                 _I2C_PADS_INFO_CPU(cpu, i2cnum, scl_pad, scl_bank, scl_gp,     \
 101                                 sda_pad, sda_bank, sda_gp, pad_ctrl, _IO)
 102
 103 #if defined(CONFIG_MX6QDL)
 104 #define I2C_PADS_INFO_ENTRY(i2cnum, scl_pad, scl_bank, scl_gp,          \
 105                 sda_pad, sda_bank, sda_gp, pad_ctrl)                    \
 106         I2C_PADS_INFO_CPU(MX6Q, i2cnum, scl_pad, scl_bank, scl_gp,      \
 107                 sda_pad, sda_bank, sda_gp, pad_ctrl),                   \
 108         I2C_PADS_INFO_CPU(MX6DL, i2cnum, scl_pad, scl_bank, scl_gp,     \
 109                 sda_pad, sda_bank, sda_gp, pad_ctrl)
 110 #define I2C_PADS_INFO_ENTRY_SPACING 2
 111
 112 #define IOMUX_PAD_CTRL(name, pad_ctrl) \
 113                 NEW_PAD_CTRL(MX6Q_PAD_##name, pad_ctrl),        \
 114                 NEW_PAD_CTRL(MX6DL_PAD_##name, pad_ctrl)
 115 #else
 116 #define I2C_PADS_INFO_ENTRY(i2cnum, scl_pad, scl_bank, scl_gp,          \
 117                 sda_pad, sda_bank, sda_gp, pad_ctrl)                    \
 118         I2C_PADS_INFO_CPU(MX6, i2cnum, scl_pad, scl_bank, scl_gp,       \
 119                 sda_pad, sda_bank, sda_gp, pad_ctrl)
 120 #define I2C_PADS_INFO_ENTRY_SPACING 1
 121
 122 #define IOMUX_PAD_CTRL(name, pad_ctrl) NEW_PAD_CTRL(MX6_PAD_##name, pad_ctrl)
 123 #endif
 124
 125 int dram_init(void)
 126 {
 127         gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024);
 128
 129         return 0;
 130 }
 131
 132 static iomux_v3_cfg_t const uart1_pads[] = {
 133         IOMUX_PAD_CTRL(SD3_DAT6__UART1_RX_DATA, UART_PAD_CTRL),
 134         IOMUX_PAD_CTRL(SD3_DAT7__UART1_TX_DATA, UART_PAD_CTRL),
 135 };
 136
 137 static iomux_v3_cfg_t const uart2_pads[] = {
 138         IOMUX_PAD_CTRL(EIM_D26__UART2_TX_DATA, UART_PAD_CTRL),
 139         IOMUX_PAD_CTRL(EIM_D27__UART2_RX_DATA, UART_PAD_CTRL),
 140 };
 141
 142 static struct i2c_pads_info i2c_pads[] = {
 143         /* I2C1, SGTL5000 */
 144         I2C_PADS_INFO_ENTRY(I2C1, EIM_D21, 3, 21, EIM_D28, 3, 28, I2C_PAD_CTRL),
 145         /* I2C2 Camera, MIPI */
 146         I2C_PADS_INFO_ENTRY(I2C2, KEY_COL3, 4, 12, KEY_ROW3, 4, 13,
 147                             I2C_PAD_CTRL),
 148         /* I2C3, J15 - RGB connector */
 149         I2C_PADS_INFO_ENTRY(I2C3, GPIO_5, 1, 05, GPIO_16, 7, 11, I2C_PAD_CTRL),
 150 };
 151
 152 #define I2C_BUS_CNT    3
 153
 154 static iomux_v3_cfg_t const usdhc2_pads[] = {
 155         IOMUX_PAD_CTRL(SD2_CLK__SD2_CLK, USDHC_PAD_CTRL),
 156         IOMUX_PAD_CTRL(SD2_CMD__SD2_CMD, USDHC_PAD_CTRL),
 157         IOMUX_PAD_CTRL(SD2_DAT0__SD2_DATA0, USDHC_PAD_CTRL),
 158         IOMUX_PAD_CTRL(SD2_DAT1__SD2_DATA1, USDHC_PAD_CTRL),
 159         IOMUX_PAD_CTRL(SD2_DAT2__SD2_DATA2, USDHC_PAD_CTRL),
 160         IOMUX_PAD_CTRL(SD2_DAT3__SD2_DATA3, USDHC_PAD_CTRL),
 161 };
 162
 163 static iomux_v3_cfg_t const enet_pads1[] = {
 164         IOMUX_PAD_CTRL(ENET_MDIO__ENET_MDIO, ENET_PAD_CTRL),
 165         IOMUX_PAD_CTRL(ENET_MDC__ENET_MDC, ENET_PAD_CTRL),
 166         IOMUX_PAD_CTRL(RGMII_TXC__RGMII_TXC, ENET_PAD_CTRL),
 167         IOMUX_PAD_CTRL(RGMII_TD0__RGMII_TD0, ENET_PAD_CTRL),
 168         IOMUX_PAD_CTRL(RGMII_TD1__RGMII_TD1, ENET_PAD_CTRL),
 169         IOMUX_PAD_CTRL(RGMII_TD2__RGMII_TD2, ENET_PAD_CTRL),
 170         IOMUX_PAD_CTRL(RGMII_TD3__RGMII_TD3, ENET_PAD_CTRL),
 171         IOMUX_PAD_CTRL(RGMII_TX_CTL__RGMII_TX_CTL, ENET_PAD_CTRL),
 172         IOMUX_PAD_CTRL(ENET_REF_CLK__ENET_TX_CLK, ENET_PAD_CTRL),
 173         /* pin 35 - 1 (PHY_AD2) on reset */
 174         IOMUX_PAD_CTRL(RGMII_RXC__GPIO6_IO30, NO_PAD_CTRL),
 175         /* pin 32 - 1 - (MODE0) all */
 176         IOMUX_PAD_CTRL(RGMII_RD0__GPIO6_IO25, NO_PAD_CTRL),
 177         /* pin 31 - 1 - (MODE1) all */
 178         IOMUX_PAD_CTRL(RGMII_RD1__GPIO6_IO27, NO_PAD_CTRL),
 179         /* pin 28 - 1 - (MODE2) all */
 180         IOMUX_PAD_CTRL(RGMII_RD2__GPIO6_IO28, NO_PAD_CTRL),
 181         /* pin 27 - 1 - (MODE3) all */
 182         IOMUX_PAD_CTRL(RGMII_RD3__GPIO6_IO29, NO_PAD_CTRL),
 183         /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
 184         IOMUX_PAD_CTRL(RGMII_RX_CTL__GPIO6_IO24, NO_PAD_CTRL),
 185         /* pin 42 PHY nRST */
 186         IOMUX_PAD_CTRL(EIM_D23__GPIO3_IO23, NO_PAD_CTRL),
 187         IOMUX_PAD_CTRL(ENET_RXD0__GPIO1_IO27, NO_PAD_CTRL),
 188 };
 189
 190 static iomux_v3_cfg_t const enet_pads2[] = {
 191         IOMUX_PAD_CTRL(RGMII_RXC__RGMII_RXC, ENET_PAD_CTRL),
 192         IOMUX_PAD_CTRL(RGMII_RD0__RGMII_RD0, ENET_PAD_CTRL),
 193         IOMUX_PAD_CTRL(RGMII_RD1__RGMII_RD1, ENET_PAD_CTRL),
 194         IOMUX_PAD_CTRL(RGMII_RD2__RGMII_RD2, ENET_PAD_CTRL),
 195         IOMUX_PAD_CTRL(RGMII_RD3__RGMII_RD3, ENET_PAD_CTRL),
 196         IOMUX_PAD_CTRL(RGMII_RX_CTL__RGMII_RX_CTL, ENET_PAD_CTRL),
 197 };
 198
 199 static iomux_v3_cfg_t const misc_pads[] = {
 200         IOMUX_PAD_CTRL(GPIO_1__USB_OTG_ID, WEAK_PULLUP),
 201         IOMUX_PAD_CTRL(KEY_COL4__USB_OTG_OC, WEAK_PULLUP),
 202         IOMUX_PAD_CTRL(EIM_D30__USB_H1_OC, WEAK_PULLUP),
 203         /* OTG Power enable */
 204         IOMUX_PAD_CTRL(EIM_D22__GPIO3_IO22, OUTPUT_40OHM),
 205 };
 206
 207 /* wl1271 pads on nitrogen6x */
 208 static iomux_v3_cfg_t const wl12xx_pads[] = {
 209         IOMUX_PAD_CTRL(NANDF_CS1__GPIO6_IO14, WEAK_PULLDOWN),
 210         IOMUX_PAD_CTRL(NANDF_CS2__GPIO6_IO15, OUTPUT_40OHM),
 211         IOMUX_PAD_CTRL(NANDF_CS3__GPIO6_IO16, OUTPUT_40OHM),
 212 };
 213 #define WL12XX_WL_IRQ_GP        IMX_GPIO_NR(6, 14)
 214 #define WL12XX_WL_ENABLE_GP     IMX_GPIO_NR(6, 15)
 215 #define WL12XX_BT_ENABLE_GP     IMX_GPIO_NR(6, 16)
 216
 217 /* Button assignments for J14 */
 218 static iomux_v3_cfg_t const button_pads[] = {
 219         /* Menu */
 220         IOMUX_PAD_CTRL(NANDF_D1__GPIO2_IO01, BUTTON_PAD_CTRL),
 221         /* Back */
 222         IOMUX_PAD_CTRL(NANDF_D2__GPIO2_IO02, BUTTON_PAD_CTRL),
 223         /* Labelled Search (mapped to Power under Android) */
 224         IOMUX_PAD_CTRL(NANDF_D3__GPIO2_IO03, BUTTON_PAD_CTRL),
 225         /* Home */
 226         IOMUX_PAD_CTRL(NANDF_D4__GPIO2_IO04, BUTTON_PAD_CTRL),
 227         /* Volume Down */
 228         IOMUX_PAD_CTRL(GPIO_19__GPIO4_IO05, BUTTON_PAD_CTRL),
 229         /* Volume Up */
 230         IOMUX_PAD_CTRL(GPIO_18__GPIO7_IO13, BUTTON_PAD_CTRL),
 231 };
 232
 233 static void setup_iomux_enet(void)
 234 {
 235         gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* SABRE Lite PHY rst */
 236         gpio_direction_output(IMX_GPIO_NR(1, 27), 0); /* Nitrogen6X PHY rst */
 237         gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
 238         gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
 239         gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
 240         gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
 241         gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
 242         SETUP_IOMUX_PADS(enet_pads1);
 243         gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
 244
 245         /* Need delay 10ms according to KSZ9021 spec */
 246         udelay(1000 * 10);
 247         gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* SABRE Lite PHY reset */
 248         gpio_set_value(IMX_GPIO_NR(1, 27), 1); /* Nitrogen6X PHY reset */
 249
 250         SETUP_IOMUX_PADS(enet_pads2);
 251         udelay(100);    /* Wait 100 us before using mii interface */
 252 }
 253
 254 static iomux_v3_cfg_t const usb_pads[] = {
 255         IOMUX_PAD_CTRL(GPIO_17__GPIO7_IO12, NO_PAD_CTRL),
 256 };
 257
 258 static void setup_iomux_uart(void)
 259 {
 260         SETUP_IOMUX_PADS(uart1_pads);
 261         SETUP_IOMUX_PADS(uart2_pads);
 262 }
 263
 264 #ifdef CONFIG_USB_EHCI_MX6
 265 int board_ehci_hcd_init(int port)
 266 {
 267         SETUP_IOMUX_PADS(usb_pads);
 268
 269         /* Reset USB hub */
 270         gpio_direction_output(IMX_GPIO_NR(7, 12), 0);
 271         mdelay(2);
 272         gpio_set_value(IMX_GPIO_NR(7, 12), 1);
 273
 274         return 0;
 275 }
 276
 277 int board_ehci_power(int port, int on)
 278 {
 279         if (port)
 280                 return 0;
 281         gpio_set_value(GP_USB_OTG_PWR, on);
 282         return 0;
 283 }
 284
 285 #endif
 286
 287 #ifdef CONFIG_MXC_SPI
 288 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 289 {
 290         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
 291 }
 292
 293 static iomux_v3_cfg_t const ecspi1_pads[] = {
 294         /* SS1 */
 295         IOMUX_PAD_CTRL(EIM_D19__GPIO3_IO19, NO_PAD_CTRL),
 296         IOMUX_PAD_CTRL(EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL),
 297         IOMUX_PAD_CTRL(EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL),
 298         IOMUX_PAD_CTRL(EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL),
 299 };
 300
 301 static void setup_spi(void)
 302 {
 303         SETUP_IOMUX_PADS(ecspi1_pads);
 304 }
 305 #endif
 306
 307 int board_phy_config(struct phy_device *phydev)
 308 {
 309         /* min rx data delay */
 310         ksz9021_phy_extended_write(phydev,
 311                         MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
 312         /* min tx data delay */
 313         ksz9021_phy_extended_write(phydev,
 314                         MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
 315         /* max rx/tx clock delay, min rx/tx control */
 316         ksz9021_phy_extended_write(phydev,
 317                         MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
 318         if (phydev->drv->config)
 319                 phydev->drv->config(phydev);
 320
 321         return 0;
 322 }
 323
 324 int board_eth_init(struct bd_info *bis)
 325 {
 326         uint32_t base = IMX_FEC_BASE;
 327         struct mii_dev *bus = NULL;
 328         struct phy_device *phydev = NULL;
 329         int ret;
 330
 331         gpio_request(WL12XX_WL_IRQ_GP, "wifi_irq");
 332         gpio_request(IMX_GPIO_NR(6, 30), "rgmii_rxc");
 333         gpio_request(IMX_GPIO_NR(6, 25), "rgmii_rd0");
 334         gpio_request(IMX_GPIO_NR(6, 27), "rgmii_rd1");
 335         gpio_request(IMX_GPIO_NR(6, 28), "rgmii_rd2");
 336         gpio_request(IMX_GPIO_NR(6, 29), "rgmii_rd3");
 337         gpio_request(IMX_GPIO_NR(6, 24), "rgmii_rx_ctl");
 338         gpio_request(IMX_GPIO_NR(3, 23), "rgmii_reset_sabrelite");
 339         gpio_request(IMX_GPIO_NR(1, 27), "rgmii_reset_nitrogen6x");
 340         setup_iomux_enet();
 341
 342 #ifdef CONFIG_FEC_MXC
 343         bus = fec_get_miibus(base, -1);
 344         if (!bus)
 345                 return -EINVAL;
 346         /* scan phy 4,5,6,7 */
 347         phydev = phy_find_by_mask(bus, (0xf << 4));
 348         if (!phydev) {
 349                 ret = -EINVAL;
 350                 goto free_bus;
 351         }
 352         printf("using phy at %d\n", phydev->addr);
 353         ret  = fec_probe(bis, -1, base, bus, phydev);
 354         if (ret)
 355                 goto free_phydev;
 356 #endif
 357
 358         return 0;
 359
 360 free_phydev:
 361         free(phydev);
 362 free_bus:
 363         free(bus);
 364         return ret;
 365 }
 366
 367 static void setup_buttons(void)
 368 {
 369         SETUP_IOMUX_PADS(button_pads);
 370 }
 371
 372 #if defined(CONFIG_VIDEO_IPUV3)
 373
 374 static iomux_v3_cfg_t const backlight_pads[] = {
 375         /* Backlight on RGB connector: J15 */
 376         IOMUX_PAD_CTRL(SD1_DAT3__GPIO1_IO21, NO_PAD_CTRL),
 377 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
 378
 379         /* Backlight on LVDS connector: J6 */
 380         IOMUX_PAD_CTRL(SD1_CMD__GPIO1_IO18, NO_PAD_CTRL),
 381 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
 382 };
 383
 384 static iomux_v3_cfg_t const rgb_pads[] = {
 385         IOMUX_PAD_CTRL(DI0_DISP_CLK__IPU1_DI0_DISP_CLK, RGB_PAD_CTRL),
 386         IOMUX_PAD_CTRL(DI0_PIN15__IPU1_DI0_PIN15, RGB_PAD_CTRL),
 387         IOMUX_PAD_CTRL(DI0_PIN2__IPU1_DI0_PIN02, RGB_PAD_CTRL),
 388         IOMUX_PAD_CTRL(DI0_PIN3__IPU1_DI0_PIN03, RGB_PAD_CTRL),
 389         IOMUX_PAD_CTRL(DI0_PIN4__GPIO4_IO20, RGB_PAD_CTRL),
 390         IOMUX_PAD_CTRL(DISP0_DAT0__IPU1_DISP0_DATA00, RGB_PAD_CTRL),
 391         IOMUX_PAD_CTRL(DISP0_DAT1__IPU1_DISP0_DATA01, RGB_PAD_CTRL),
 392         IOMUX_PAD_CTRL(DISP0_DAT2__IPU1_DISP0_DATA02, RGB_PAD_CTRL),
 393         IOMUX_PAD_CTRL(DISP0_DAT3__IPU1_DISP0_DATA03, RGB_PAD_CTRL),
 394         IOMUX_PAD_CTRL(DISP0_DAT4__IPU1_DISP0_DATA04, RGB_PAD_CTRL),
 395         IOMUX_PAD_CTRL(DISP0_DAT5__IPU1_DISP0_DATA05, RGB_PAD_CTRL),
 396         IOMUX_PAD_CTRL(DISP0_DAT6__IPU1_DISP0_DATA06, RGB_PAD_CTRL),
 397         IOMUX_PAD_CTRL(DISP0_DAT7__IPU1_DISP0_DATA07, RGB_PAD_CTRL),
 398         IOMUX_PAD_CTRL(DISP0_DAT8__IPU1_DISP0_DATA08, RGB_PAD_CTRL),
 399         IOMUX_PAD_CTRL(DISP0_DAT9__IPU1_DISP0_DATA09, RGB_PAD_CTRL),
 400         IOMUX_PAD_CTRL(DISP0_DAT10__IPU1_DISP0_DATA10, RGB_PAD_CTRL),
 401         IOMUX_PAD_CTRL(DISP0_DAT11__IPU1_DISP0_DATA11, RGB_PAD_CTRL),
 402         IOMUX_PAD_CTRL(DISP0_DAT12__IPU1_DISP0_DATA12, RGB_PAD_CTRL),
 403         IOMUX_PAD_CTRL(DISP0_DAT13__IPU1_DISP0_DATA13, RGB_PAD_CTRL),
 404         IOMUX_PAD_CTRL(DISP0_DAT14__IPU1_DISP0_DATA14, RGB_PAD_CTRL),
 405         IOMUX_PAD_CTRL(DISP0_DAT15__IPU1_DISP0_DATA15, RGB_PAD_CTRL),
 406         IOMUX_PAD_CTRL(DISP0_DAT16__IPU1_DISP0_DATA16, RGB_PAD_CTRL),
 407         IOMUX_PAD_CTRL(DISP0_DAT17__IPU1_DISP0_DATA17, RGB_PAD_CTRL),
 408         IOMUX_PAD_CTRL(DISP0_DAT18__IPU1_DISP0_DATA18, RGB_PAD_CTRL),
 409         IOMUX_PAD_CTRL(DISP0_DAT19__IPU1_DISP0_DATA19, RGB_PAD_CTRL),
 410         IOMUX_PAD_CTRL(DISP0_DAT20__IPU1_DISP0_DATA20, RGB_PAD_CTRL),
 411         IOMUX_PAD_CTRL(DISP0_DAT21__IPU1_DISP0_DATA21, RGB_PAD_CTRL),
 412         IOMUX_PAD_CTRL(DISP0_DAT22__IPU1_DISP0_DATA22, RGB_PAD_CTRL),
 413         IOMUX_PAD_CTRL(DISP0_DAT23__IPU1_DISP0_DATA23, RGB_PAD_CTRL),
 414 };
 415
 416 static void do_enable_hdmi(struct display_info_t const *dev)
 417 {
 418         imx_enable_hdmi_phy();
 419 }
 420
 421 static int detect_i2c(struct display_info_t const *dev)
 422 {
 423         return ((0 == i2c_set_bus_num(dev->bus))
 424                 &&
 425                 (0 == i2c_probe(dev->addr)));
 426 }
 427
 428 static void enable_lvds(struct display_info_t const *dev)
 429 {
 430         struct iomuxc *iomux = (struct iomuxc *)
 431                                 IOMUXC_BASE_ADDR;
 432         u32 reg = readl(&iomux->gpr[2]);
 433         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
 434         writel(reg, &iomux->gpr[2]);
 435         gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
 436 }
 437
 438 static void enable_lvds_jeida(struct display_info_t const *dev)
 439 {
 440         struct iomuxc *iomux = (struct iomuxc *)
 441                                 IOMUXC_BASE_ADDR;
 442         u32 reg = readl(&iomux->gpr[2]);
 443         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
 444              |IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA;
 445         writel(reg, &iomux->gpr[2]);
 446         gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
 447 }
 448
 449 static void enable_rgb(struct display_info_t const *dev)
 450 {
 451         SETUP_IOMUX_PADS(rgb_pads);
 452         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 453 }
 454
 455 struct display_info_t const displays[] = {{
 456         .bus    = 1,
 457         .addr   = 0x50,
 458         .pixfmt = IPU_PIX_FMT_RGB24,
 459         .detect = detect_i2c,
 460         .enable = do_enable_hdmi,
 461         .mode   = {
 462                 .name           = "HDMI",
 463                 .refresh        = 60,
 464                 .xres           = 1024,
 465                 .yres           = 768,
 466                 .pixclock       = 15385,
 467                 .left_margin    = 220,
 468                 .right_margin   = 40,
 469                 .upper_margin   = 21,
 470                 .lower_margin   = 7,
 471                 .hsync_len      = 60,
 472                 .vsync_len      = 10,
 473                 .sync           = FB_SYNC_EXT,
 474                 .vmode          = FB_VMODE_NONINTERLACED
 475 } }, {
 476         .bus    = 0,
 477         .addr   = 0,
 478         .pixfmt = IPU_PIX_FMT_RGB24,
 479         .detect = NULL,
 480         .enable = enable_lvds_jeida,
 481         .mode   = {
 482                 .name           = "LDB-WXGA",
 483                 .refresh        = 60,
 484                 .xres           = 1280,
 485                 .yres           = 800,
 486                 .pixclock       = 14065,
 487                 .left_margin    = 40,
 488                 .right_margin   = 40,
 489                 .upper_margin   = 3,
 490                 .lower_margin   = 80,
 491                 .hsync_len      = 10,
 492                 .vsync_len      = 10,
 493                 .sync           = FB_SYNC_EXT,
 494                 .vmode          = FB_VMODE_NONINTERLACED
 495 } }, {
 496         .bus    = 0,
 497         .addr   = 0,
 498         .pixfmt = IPU_PIX_FMT_RGB24,
 499         .detect = NULL,
 500         .enable = enable_lvds,
 501         .mode   = {
 502                 .name           = "LDB-WXGA-S",
 503                 .refresh        = 60,
 504                 .xres           = 1280,
 505                 .yres           = 800,
 506                 .pixclock       = 14065,
 507                 .left_margin    = 40,
 508                 .right_margin   = 40,
 509                 .upper_margin   = 3,
 510                 .lower_margin   = 80,
 511                 .hsync_len      = 10,
 512                 .vsync_len      = 10,
 513                 .sync           = FB_SYNC_EXT,
 514                 .vmode          = FB_VMODE_NONINTERLACED
 515 } }, {
 516         .bus    = 2,
 517         .addr   = 0x4,
 518         .pixfmt = IPU_PIX_FMT_LVDS666,
 519         .detect = detect_i2c,
 520         .enable = enable_lvds,
 521         .mode   = {
 522                 .name           = "Hannstar-XGA",
 523                 .refresh        = 60,
 524                 .xres           = 1024,
 525                 .yres           = 768,
 526                 .pixclock       = 15385,
 527                 .left_margin    = 220,
 528                 .right_margin   = 40,
 529                 .upper_margin   = 21,
 530                 .lower_margin   = 7,
 531                 .hsync_len      = 60,
 532                 .vsync_len      = 10,
 533                 .sync           = FB_SYNC_EXT,
 534                 .vmode          = FB_VMODE_NONINTERLACED
 535 } }, {
 536         .bus    = 0,
 537         .addr   = 0,
 538         .pixfmt = IPU_PIX_FMT_LVDS666,
 539         .detect = NULL,
 540         .enable = enable_lvds,
 541         .mode   = {
 542                 .name           = "LG-9.7",
 543                 .refresh        = 60,
 544                 .xres           = 1024,
 545                 .yres           = 768,
 546                 .pixclock       = 15385, /* ~65MHz */
 547                 .left_margin    = 480,
 548                 .right_margin   = 260,
 549                 .upper_margin   = 16,
 550                 .lower_margin   = 6,
 551                 .hsync_len      = 250,
 552                 .vsync_len      = 10,
 553                 .sync           = FB_SYNC_EXT,
 554                 .vmode          = FB_VMODE_NONINTERLACED
 555 } }, {
 556         .bus    = 2,
 557         .addr   = 0x38,
 558         .pixfmt = IPU_PIX_FMT_LVDS666,
 559         .detect = detect_i2c,
 560         .enable = enable_lvds,
 561         .mode   = {
 562                 .name           = "wsvga-lvds",
 563                 .refresh        = 60,
 564                 .xres           = 1024,
 565                 .yres           = 600,
 566                 .pixclock       = 15385,
 567                 .left_margin    = 220,
 568                 .right_margin   = 40,
 569                 .upper_margin   = 21,
 570                 .lower_margin   = 7,
 571                 .hsync_len      = 60,
 572                 .vsync_len      = 10,
 573                 .sync           = FB_SYNC_EXT,
 574                 .vmode          = FB_VMODE_NONINTERLACED
 575 } }, {
 576         .bus    = 2,
 577         .addr   = 0x10,
 578         .pixfmt = IPU_PIX_FMT_RGB666,
 579         .detect = detect_i2c,
 580         .enable = enable_rgb,
 581         .mode   = {
 582                 .name           = "fusion7",
 583                 .refresh        = 60,
 584                 .xres           = 800,
 585                 .yres           = 480,
 586                 .pixclock       = 33898,
 587                 .left_margin    = 96,
 588                 .right_margin   = 24,
 589                 .upper_margin   = 3,
 590                 .lower_margin   = 10,
 591                 .hsync_len      = 72,
 592                 .vsync_len      = 7,
 593                 .sync           = 0x40000002,
 594                 .vmode          = FB_VMODE_NONINTERLACED
 595 } }, {
 596         .bus    = 0,
 597         .addr   = 0,
 598         .pixfmt = IPU_PIX_FMT_RGB666,
 599         .detect = NULL,
 600         .enable = enable_rgb,
 601         .mode   = {
 602                 .name           = "svga",
 603                 .refresh        = 60,
 604                 .xres           = 800,
 605                 .yres           = 600,
 606                 .pixclock       = 15385,
 607                 .left_margin    = 220,
 608                 .right_margin   = 40,
 609                 .upper_margin   = 21,
 610                 .lower_margin   = 7,
 611                 .hsync_len      = 60,
 612                 .vsync_len      = 10,
 613                 .sync           = 0,
 614                 .vmode          = FB_VMODE_NONINTERLACED
 615 } }, {
 616         .bus    = 2,
 617         .addr   = 0x41,
 618         .pixfmt = IPU_PIX_FMT_LVDS666,
 619         .detect = detect_i2c,
 620         .enable = enable_lvds,
 621         .mode   = {
 622                 .name           = "amp1024x600",
 623                 .refresh        = 60,
 624                 .xres           = 1024,
 625                 .yres           = 600,
 626                 .pixclock       = 15385,
 627                 .left_margin    = 220,
 628                 .right_margin   = 40,
 629                 .upper_margin   = 21,
 630                 .lower_margin   = 7,
 631                 .hsync_len      = 60,
 632                 .vsync_len      = 10,
 633                 .sync           = FB_SYNC_EXT,
 634                 .vmode          = FB_VMODE_NONINTERLACED
 635 } }, {
 636         .bus    = 0,
 637         .addr   = 0,
 638         .pixfmt = IPU_PIX_FMT_LVDS666,
 639         .detect = 0,
 640         .enable = enable_lvds,
 641         .mode   = {
 642                 .name           = "wvga-lvds",
 643                 .refresh        = 57,
 644                 .xres           = 800,
 645                 .yres           = 480,
 646                 .pixclock       = 15385,
 647                 .left_margin    = 220,
 648                 .right_margin   = 40,
 649                 .upper_margin   = 21,
 650                 .lower_margin   = 7,
 651                 .hsync_len      = 60,
 652                 .vsync_len      = 10,
 653                 .sync           = FB_SYNC_EXT,
 654                 .vmode          = FB_VMODE_NONINTERLACED
 655 } }, {
 656         .bus    = 2,
 657         .addr   = 0x48,
 658         .pixfmt = IPU_PIX_FMT_RGB666,
 659         .detect = detect_i2c,
 660         .enable = enable_rgb,
 661         .mode   = {
 662                 .name           = "wvga-rgb",
 663                 .refresh        = 57,
 664                 .xres           = 800,
 665                 .yres           = 480,
 666                 .pixclock       = 37037,
 667                 .left_margin    = 40,
 668                 .right_margin   = 60,
 669                 .upper_margin   = 10,
 670                 .lower_margin   = 10,
 671                 .hsync_len      = 20,
 672                 .vsync_len      = 10,
 673                 .sync           = 0,
 674                 .vmode          = FB_VMODE_NONINTERLACED
 675 } }, {
 676         .bus    = 0,
 677         .addr   = 0,
 678         .pixfmt = IPU_PIX_FMT_RGB24,
 679         .detect = NULL,
 680         .enable = enable_rgb,
 681         .mode   = {
 682                 .name           = "qvga",
 683                 .refresh        = 60,
 684                 .xres           = 320,
 685                 .yres           = 240,
 686                 .pixclock       = 37037,
 687                 .left_margin    = 38,
 688                 .right_margin   = 37,
 689                 .upper_margin   = 16,
 690                 .lower_margin   = 15,
 691                 .hsync_len      = 30,
 692                 .vsync_len      = 3,
 693                 .sync           = 0,
 694                 .vmode          = FB_VMODE_NONINTERLACED
 695 } } };
 696 size_t display_count = ARRAY_SIZE(displays);
 697
 698 int board_cfb_skip(void)
 699 {
 700         return NULL != env_get("novideo");
 701 }
 702
 703 static void setup_display(void)
 704 {
 705         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 706         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 707         int reg;
 708
 709         enable_ipu_clock();
 710         imx_setup_hdmi();
 711         /* Turn on LDB0,IPU,IPU DI0 clocks */
 712         reg = __raw_readl(&mxc_ccm->CCGR3);
 713         reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK;
 714         writel(reg, &mxc_ccm->CCGR3);
 715
 716         /* set LDB0, LDB1 clk select to 011/011 */
 717         reg = readl(&mxc_ccm->cs2cdr);
 718         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 719                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 720         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 721               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 722         writel(reg, &mxc_ccm->cs2cdr);
 723
 724         reg = readl(&mxc_ccm->cscmr2);
 725         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 726         writel(reg, &mxc_ccm->cscmr2);
 727
 728         reg = readl(&mxc_ccm->chsccdr);
 729         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 730                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 731         writel(reg, &mxc_ccm->chsccdr);
 732
 733         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 734              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 735              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 736              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 737              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 738              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 739              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 740              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 741              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 742         writel(reg, &iomux->gpr[2]);
 743
 744         reg = readl(&iomux->gpr[3]);
 745         reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
 746                         |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
 747             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 748                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 749         writel(reg, &iomux->gpr[3]);
 750
 751         /* backlights off until needed */
 752         SETUP_IOMUX_PADS(backlight_pads);
 753         gpio_direction_input(LVDS_BACKLIGHT_GP);
 754         gpio_direction_input(RGB_BACKLIGHT_GP);
 755 }
 756 #endif
 757
 758 static iomux_v3_cfg_t const init_pads[] = {
 759         /* SGTL5000 sys_mclk */
 760         IOMUX_PAD_CTRL(GPIO_0__CCM_CLKO1, OUTPUT_40OHM),
 761
 762         /* J5 - Camera MCLK */
 763         IOMUX_PAD_CTRL(GPIO_3__CCM_CLKO2, OUTPUT_40OHM),
 764
 765         /* wl1271 pads on nitrogen6x */
 766         /* WL12XX_WL_IRQ_GP */
 767         IOMUX_PAD_CTRL(NANDF_CS1__GPIO6_IO14, WEAK_PULLDOWN),
 768         /* WL12XX_WL_ENABLE_GP */
 769         IOMUX_PAD_CTRL(NANDF_CS2__GPIO6_IO15, OUTPUT_40OHM),
 770         /* WL12XX_BT_ENABLE_GP */
 771         IOMUX_PAD_CTRL(NANDF_CS3__GPIO6_IO16, OUTPUT_40OHM),
 772         /* USB otg power */
 773         IOMUX_PAD_CTRL(EIM_D22__GPIO3_IO22, OUTPUT_40OHM),
 774         IOMUX_PAD_CTRL(NANDF_D5__GPIO2_IO05, OUTPUT_40OHM),
 775         IOMUX_PAD_CTRL(NANDF_WP_B__GPIO6_IO09, OUTPUT_40OHM),
 776         IOMUX_PAD_CTRL(GPIO_8__GPIO1_IO08, OUTPUT_40OHM),
 777         IOMUX_PAD_CTRL(GPIO_6__GPIO1_IO06, OUTPUT_40OHM),
 778 };
 779
 780 #define WL12XX_WL_IRQ_GP        IMX_GPIO_NR(6, 14)
 781
 782 static unsigned gpios_out_low[] = {
 783         /* Disable wl1271 */
 784         IMX_GPIO_NR(6, 15),     /* disable wireless */
 785         IMX_GPIO_NR(6, 16),     /* disable bluetooth */
 786         IMX_GPIO_NR(3, 22),     /* disable USB otg power */
 787         IMX_GPIO_NR(2, 5),      /* ov5640 mipi camera reset */
 788         IMX_GPIO_NR(1, 8),      /* ov5642 reset */
 789 };
 790
 791 static unsigned gpios_out_high[] = {
 792         IMX_GPIO_NR(1, 6),      /* ov5642 powerdown */
 793         IMX_GPIO_NR(6, 9),      /* ov5640 mipi camera power down */
 794 };
 795
 796 static void set_gpios(unsigned *p, int cnt, int val)
 797 {
 798         int i;
 799
 800         for (i = 0; i < cnt; i++)
 801                 gpio_direction_output(*p++, val);
 802 }
 803
 804 int board_early_init_f(void)
 805 {
 806         setup_iomux_uart();
 807
 808         set_gpios(gpios_out_high, ARRAY_SIZE(gpios_out_high), 1);
 809         set_gpios(gpios_out_low, ARRAY_SIZE(gpios_out_low), 0);
 810         gpio_direction_input(WL12XX_WL_IRQ_GP);
 811
 812         SETUP_IOMUX_PADS(wl12xx_pads);
 813         SETUP_IOMUX_PADS(init_pads);
 814         setup_buttons();
 815
 816 #if defined(CONFIG_VIDEO_IPUV3)
 817         setup_display();
 818 #endif
 819         return 0;
 820 }
 821
 822 /*
 823  * Do not overwrite the console
 824  * Use always serial for U-Boot console
 825  */
 826 int overwrite_console(void)
 827 {
 828         return 1;
 829 }
 830
 831 int board_init(void)
 832 {
 833         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 834         struct i2c_pads_info *p = i2c_pads;
 835         int i;
 836         int stride = 1;
 837
 838 #if defined(CONFIG_MX6QDL)
 839         stride = 2;
 840         if (!is_mx6dq() && !is_mx6dqp())
 841                 p += 1;
 842 #endif
 843         clrsetbits_le32(&iomuxc_regs->gpr[1],
 844                         IOMUXC_GPR1_OTG_ID_MASK,
 845                         IOMUXC_GPR1_OTG_ID_GPIO1);
 846
 847         SETUP_IOMUX_PADS(misc_pads);
 848
 849         /* address of boot parameters */
 850         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 851
 852 #ifdef CONFIG_MXC_SPI
 853         setup_spi();
 854 #endif
 855         SETUP_IOMUX_PADS(usdhc2_pads);
 856         for (i = 0; i < I2C_BUS_CNT; i++) {
 857                 setup_i2c(i, CONFIG_SYS_I2C_SPEED, 0x7f, p);
 858                 p += stride;
 859         }
 860
 861 #ifdef CONFIG_SATA
 862         setup_sata();
 863 #endif
 864
 865         return 0;
 866 }
 867
 868 int checkboard(void)
 869 {
 870         int ret = gpio_get_value(WL12XX_WL_IRQ_GP);
 871
 872         if (ret < 0) {
 873                 /* The gpios have not been probed yet. Read it myself */
 874                 struct gpio_regs *regs = (struct gpio_regs *)GPIO6_BASE_ADDR;
 875                 int gpio = WL12XX_WL_IRQ_GP & 0x1f;
 876
 877                 ret = (readl(&regs->gpio_psr) >> gpio) & 0x01;
 878         }
 879         if (ret)
 880                 puts("Board: Nitrogen6X\n");
 881         else
 882                 puts("Board: SABRE Lite\n");
 883
 884         return 0;
 885 }
 886
 887 struct button_key {
 888         char const      *name;
 889         unsigned        gpnum;
 890         char            ident;
 891 };
 892
 893 static struct button_key const buttons[] = {
 894         {"back",        IMX_GPIO_NR(2, 2),      'B'},
 895         {"home",        IMX_GPIO_NR(2, 4),      'H'},
 896         {"menu",        IMX_GPIO_NR(2, 1),      'M'},
 897         {"search",      IMX_GPIO_NR(2, 3),      'S'},
 898         {"volup",       IMX_GPIO_NR(7, 13),     'V'},
 899         {"voldown",     IMX_GPIO_NR(4, 5),      'v'},
 900 };
 901
 902 /*
 903  * generate a null-terminated string containing the buttons pressed
 904  * returns number of keys pressed
 905  */
 906 static int read_keys(char *buf)
 907 {
 908         int i, numpressed = 0;
 909         for (i = 0; i < ARRAY_SIZE(buttons); i++) {
 910                 if (!gpio_get_value(buttons[i].gpnum))
 911                         buf[numpressed++] = buttons[i].ident;
 912         }
 913         buf[numpressed] = '\0';
 914         return numpressed;
 915 }
 916
 917 static int do_kbd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 918 {
 919         char envvalue[ARRAY_SIZE(buttons)+1];
 920         int numpressed = read_keys(envvalue);
 921         env_set("keybd", envvalue);
 922         return numpressed == 0;
 923 }
 924
 925 U_BOOT_CMD(
 926         kbd, 1, 1, do_kbd,
 927         "Tests for keypresses, sets 'keybd' environment variable",
 928         "Returns 0 (true) to shell if key is pressed."
 929 );
 930
 931 #ifdef CONFIG_USE_PREBOOT
 932 static char const kbd_magic_prefix[] = "key_magic";
 933 static char const kbd_command_prefix[] = "key_cmd";
 934
 935 static void preboot_keys(void)
 936 {
 937         int numpressed;
 938         char keypress[ARRAY_SIZE(buttons)+1];
 939         numpressed = read_keys(keypress);
 940         if (numpressed) {
 941                 char *kbd_magic_keys = env_get("magic_keys");
 942                 char *suffix;
 943                 /*
 944                  * loop over all magic keys
 945                  */
 946                 for (suffix = kbd_magic_keys; *suffix; ++suffix) {
 947                         char *keys;
 948                         char magic[sizeof(kbd_magic_prefix) + 1];
 949                         sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
 950                         keys = env_get(magic);
 951                         if (keys) {
 952                                 if (!strcmp(keys, keypress))
 953                                         break;
 954                         }
 955                 }
 956                 if (*suffix) {
 957                         char cmd_name[sizeof(kbd_command_prefix) + 1];
 958                         char *cmd;
 959                         sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
 960                         cmd = env_get(cmd_name);
 961                         if (cmd) {
 962                                 env_set("preboot", cmd);
 963                                 return;
 964                         }
 965                 }
 966         }
 967 }
 968 #endif
 969
 970 #ifdef CONFIG_CMD_BMODE
 971 static const struct boot_mode board_boot_modes[] = {
 972         /* 4 bit bus width */
 973         {"mmc0",        MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 974         {"mmc1",        MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
 975         {NULL,          0},
 976 };
 977 #endif
 978
 979 int misc_init_r(void)
 980 {
 981         gpio_request(RGB_BACKLIGHT_GP, "lvds backlight");
 982         gpio_request(LVDS_BACKLIGHT_GP, "lvds backlight");
 983         gpio_request(GP_USB_OTG_PWR, "usbotg power");
 984         gpio_request(IMX_GPIO_NR(7, 12), "usbh1 hub reset");
 985         gpio_request(IMX_GPIO_NR(2, 2), "back");
 986         gpio_request(IMX_GPIO_NR(2, 4), "home");
 987         gpio_request(IMX_GPIO_NR(2, 1), "menu");
 988         gpio_request(IMX_GPIO_NR(2, 3), "search");
 989         gpio_request(IMX_GPIO_NR(7, 13), "volup");
 990         gpio_request(IMX_GPIO_NR(4, 5), "voldown");
 991 #ifdef CONFIG_USE_PREBOOT
 992         preboot_keys();
 993 #endif
 994
 995 #ifdef CONFIG_CMD_BMODE
 996         add_board_boot_modes(board_boot_modes);
 997 #endif
 998         env_set_hex("reset_cause", get_imx_reset_cause());
 999         return 0;
1000 }