arch/arm/mach-rockchip/tpl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2019 Rockchip Electronics Co., Ltd
   4  */
   5
   6 #include <bootstage.h>
   7 #include <debug_uart.h>
   8 #include <dm.h>
   9 #include <hang.h>
  10 #include <init.h>
  11 #include <log.h>
  12 #include <ram.h>
  13 #include <spl.h>
  14 #include <version.h>
  15 #include <asm/io.h>
  16 #include <asm/arch-rockchip/bootrom.h>
  17 #include <linux/bitops.h>
  18
  19 #if CONFIG_IS_ENABLED(BANNER_PRINT)
  20 #include <timestamp.h>
  21 #endif
  22
  23 #define TIMER_LOAD_COUNT_L      0x00
  24 #define TIMER_LOAD_COUNT_H      0x04
  25 #define TIMER_CONTROL_REG       0x10
  26 #define TIMER_EN        0x1
  27 #define TIMER_FMODE     BIT(0)
  28 #define TIMER_RMODE     BIT(1)
  29
  30 __weak void rockchip_stimer_init(void)
  31 {
  32 #if defined(CONFIG_ROCKCHIP_STIMER_BASE)
  33         /* If Timer already enabled, don't re-init it */
  34         u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
  35
  36         if (reg & TIMER_EN)
  37                 return;
  38
  39 #ifndef CONFIG_ARM64
  40         asm volatile("mcr p15, 0, %0, c14, c0, 0"
  41                      : : "r"(CONFIG_COUNTER_FREQUENCY));
  42 #endif
  43
  44         writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
  45         writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE);
  46         writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4);
  47         writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE +
  48                TIMER_CONTROL_REG);
  49 #endif
  50 }
  51
  52 void board_init_f(ulong dummy)
  53 {
  54         struct udevice *dev;
  55         int ret;
  56
  57 #if defined(CONFIG_DEBUG_UART) && defined(CONFIG_TPL_SERIAL)
  58         /*
  59          * Debug UART can be used from here if required:
  60          *
  61          * debug_uart_init();
  62          * printch('a');
  63          * printhex8(0x1234);
  64          * printascii("string");
  65          */
  66         debug_uart_init();
  67 #ifdef CONFIG_TPL_BANNER_PRINT
  68         printascii("\nU-Boot TPL " PLAIN_VERSION " (" U_BOOT_DATE " - " \
  69                                 U_BOOT_TIME ")\n");
  70 #endif
  71 #endif
  72         /* Init secure timer */
  73         rockchip_stimer_init();
  74
  75         ret = spl_early_init();
  76         if (ret) {
  77                 debug("spl_early_init() failed: %d\n", ret);
  78                 hang();
  79         }
  80
  81         /* Init ARM arch timer */
  82         if (IS_ENABLED(CONFIG_SYS_ARCH_TIMER))
  83                 timer_init();
  84
  85         ret = uclass_get_device(UCLASS_RAM, 0, &dev);
  86         if (ret) {
  87                 printf("DRAM init failed: %d\n", ret);
  88                 return;
  89         }
  90 }
  91
  92 int board_return_to_bootrom(struct spl_image_info *spl_image,
  93                             struct spl_boot_device *bootdev)
  94 {
  95 #ifdef CONFIG_BOOTSTAGE_STASH
  96         int ret;
  97
  98         bootstage_mark_name(BOOTSTAGE_ID_END_TPL, "end tpl");
  99         ret = bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH_ADDR,
 100                               CONFIG_BOOTSTAGE_STASH_SIZE);
 101         if (ret)
 102                 debug("Failed to stash bootstage: err=%d\n", ret);
 103 #endif
 104         back_to_bootrom(BROM_BOOT_NEXTSTAGE);
 105
 106         return 0;
 107 }
 108
 109 u32 spl_boot_device(void)
 110 {
 111         return BOOT_DEVICE_BOOTROM;
 112 }