[u-boot.git] / arch / x86 / Kconfig

menu "x86 architecture"
	depends on X86

config SYS_ARCH
	default "x86"

choice
	prompt "Mainboard vendor"
	default VENDOR_EMULATION

config VENDOR_COREBOOT
	bool "coreboot"

config VENDOR_EFI
	bool "efi"

config VENDOR_EMULATION
	bool "emulation"

config VENDOR_GOOGLE
	bool "Google"

config VENDOR_INTEL
	bool "Intel"

endchoice

# board-specific options below
source "board/coreboot/Kconfig"
source "board/efi/Kconfig"
source "board/emulation/Kconfig"
source "board/google/Kconfig"
source "board/intel/Kconfig"

# platform-specific options below
source "arch/x86/cpu/baytrail/Kconfig"
source "arch/x86/cpu/coreboot/Kconfig"
source "arch/x86/cpu/ivybridge/Kconfig"
source "arch/x86/cpu/qemu/Kconfig"
source "arch/x86/cpu/quark/Kconfig"
source "arch/x86/cpu/queensbay/Kconfig"

# architecture-specific options below

config SYS_MALLOC_F_LEN
	default 0x800

config RAMBASE
	hex
	default 0x100000

config XIP_ROM_SIZE
	hex
	depends on X86_RESET_VECTOR
	default ROM_SIZE

config CPU_ADDR_BITS
	int
	default 36

config HPET_ADDRESS
	hex
	default 0xfed00000 if !HPET_ADDRESS_OVERRIDE

config SMM_TSEG
	bool
	default n

config SMM_TSEG_SIZE
	hex

config X86_RESET_VECTOR
	bool
	default n

config RESET_SEG_START
	hex
	depends on X86_RESET_VECTOR
	default 0xffff0000

config RESET_SEG_SIZE
	hex
	depends on X86_RESET_VECTOR
	default 0x10000

config RESET_VEC_LOC
	hex
	depends on X86_RESET_VECTOR
	default 0xfffffff0

config SYS_X86_START16
	hex
	depends on X86_RESET_VECTOR
	default 0xfffff800

config BOARD_ROMSIZE_KB_512
	bool
config BOARD_ROMSIZE_KB_1024
	bool
config BOARD_ROMSIZE_KB_2048
	bool
config BOARD_ROMSIZE_KB_4096
	bool
config BOARD_ROMSIZE_KB_8192
	bool
config BOARD_ROMSIZE_KB_16384
	bool

choice
	prompt "ROM chip size"
	depends on X86_RESET_VECTOR
	default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
	default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
	default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
	default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
	default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
	default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
	help
	  Select the size of the ROM chip you intend to flash U-Boot on.

	  The build system will take care of creating a u-boot.rom file
	  of the matching size.

config UBOOT_ROMSIZE_KB_512
	bool "512 KB"
	help
	  Choose this option if you have a 512 KB ROM chip.

config UBOOT_ROMSIZE_KB_1024
	bool "1024 KB (1 MB)"
	help
	  Choose this option if you have a 1024 KB (1 MB) ROM chip.

config UBOOT_ROMSIZE_KB_2048
	bool "2048 KB (2 MB)"
	help
	  Choose this option if you have a 2048 KB (2 MB) ROM chip.

config UBOOT_ROMSIZE_KB_4096
	bool "4096 KB (4 MB)"
	help
	  Choose this option if you have a 4096 KB (4 MB) ROM chip.

config UBOOT_ROMSIZE_KB_8192
	bool "8192 KB (8 MB)"
	help
	  Choose this option if you have a 8192 KB (8 MB) ROM chip.

config UBOOT_ROMSIZE_KB_16384
	bool "16384 KB (16 MB)"
	help
	  Choose this option if you have a 16384 KB (16 MB) ROM chip.

endchoice

# Map the config names to an integer (KB).
config UBOOT_ROMSIZE_KB
	int
	default 512 if UBOOT_ROMSIZE_KB_512
	default 1024 if UBOOT_ROMSIZE_KB_1024
	default 2048 if UBOOT_ROMSIZE_KB_2048
	default 4096 if UBOOT_ROMSIZE_KB_4096
	default 8192 if UBOOT_ROMSIZE_KB_8192
	default 16384 if UBOOT_ROMSIZE_KB_16384

# Map the config names to a hex value (bytes).
config ROM_SIZE
	hex
	default 0x80000 if UBOOT_ROMSIZE_KB_512
	default 0x100000 if UBOOT_ROMSIZE_KB_1024
	default 0x200000 if UBOOT_ROMSIZE_KB_2048
	default 0x400000 if UBOOT_ROMSIZE_KB_4096
	default 0x800000 if UBOOT_ROMSIZE_KB_8192
	default 0xc00000 if UBOOT_ROMSIZE_KB_12288
	default 0x1000000 if UBOOT_ROMSIZE_KB_16384

config HAVE_INTEL_ME
	bool "Platform requires Intel Management Engine"
	help
	  Newer higher-end devices have an Intel Management Engine (ME)
	  which is a very large binary blob (typically 1.5MB) which is
	  required for the platform to work. This enforces a particular
	  SPI flash format. You will need to supply the me.bin file in
	  your board directory.

config X86_RAMTEST
	bool "Perform a simple RAM test after SDRAM initialisation"
	help
	  If there is something wrong with SDRAM then the platform will
	  often crash within U-Boot or the kernel. This option enables a
	  very simple RAM test that quickly checks whether the SDRAM seems
	  to work correctly. It is not exhaustive but can save time by
	  detecting obvious failures.

config HAVE_FSP
	bool "Add an Firmware Support Package binary"
	depends on !EFI
	help
	  Select this option to add an Firmware Support Package binary to
	  the resulting U-Boot image. It is a binary blob which U-Boot uses
	  to set up SDRAM and other chipset specific initialization.

	  Note: Without this binary U-Boot will not be able to set up its
	  SDRAM so will not boot.

config FSP_FILE
	string "Firmware Support Package binary filename"
	depends on HAVE_FSP
	default "fsp.bin"
	help
	  The filename of the file to use as Firmware Support Package binary
	  in the board directory.

config FSP_ADDR
	hex "Firmware Support Package binary location"
	depends on HAVE_FSP
	default 0xfffc0000
	help
	  FSP is not Position Independent Code (PIC) and the whole FSP has to
	  be rebased if it is placed at a location which is different from the
	  perferred base address specified during the FSP build. Use Intel's
	  Binary Configuration Tool (BCT) to do the rebase.

	  The default base address of 0xfffc0000 indicates that the binary must
	  be located at offset 0xc0000 from the beginning of a 1MB flash device.

config FSP_TEMP_RAM_ADDR
	hex
	depends on HAVE_FSP
	default 0x2000000
	help
	  Stack top address which is used in fsp_init() after DRAM is ready and
	  CAR is disabled.

config FSP_SYS_MALLOC_F_LEN
	hex
	depends on HAVE_FSP
	default 0x100000
	help
	  Additional size of malloc() pool before relocation.

config FSP_USE_UPD
	bool
	depends on HAVE_FSP
	default y
	help
	  Most FSPs use UPD data region for some FSP customization. But there
	  are still some FSPs that might not even have UPD. For such FSPs,
	  override this to n in their platform Kconfig files.

config FSP_BROKEN_HOB
	bool
	depends on HAVE_FSP
	help
	  Indicate some buggy FSPs that does not report memory used by FSP
	  itself as reserved in the resource descriptor HOB. Select this to
	  tell U-Boot to do some additional work to ensure U-Boot relocation
	  do not overwrite the important boot service data which is used by
	  FSP, otherwise the subsequent call to fsp_notify() will fail.

config ENABLE_MRC_CACHE
	bool "Enable MRC cache"
	depends on !EFI && !SYS_COREBOOT
	help
	  Enable this feature to cause MRC data to be cached in NV storage
	  to be used for speeding up boot time on future reboots and/or
	  power cycles.

config SMP
	bool "Enable Symmetric Multiprocessing"
	default n
	help
	  Enable use of more than one CPU in U-Boot and the Operating System
	  when loaded. Each CPU will be started up and information can be
	  obtained using the 'cpu' command. If this option is disabled, then
	  only one CPU will be enabled regardless of the number of CPUs
	  available.

config MAX_CPUS
	int "Maximum number of CPUs permitted"
	depends on SMP
	default 4
	help
	  When using multi-CPU chips it is possible for U-Boot to start up
	  more than one CPU. The stack memory used by all of these CPUs is
	  pre-allocated so at present U-Boot wants to know the maximum
	  number of CPUs that may be present. Set this to at least as high
	  as the number of CPUs in your system (it uses about 4KB of RAM for
	  each CPU).

config AP_STACK_SIZE
	hex
	depends on SMP
	default 0x1000
	help
	  Each additional CPU started by U-Boot requires its own stack. This
	  option sets the stack size used by each CPU and directly affects
	  the memory used by this initialisation process. Typically 4KB is
	  enough space.

config HAVE_VGA_BIOS
	bool "Add a VGA BIOS image"
	help
	  Select this option if you have a VGA BIOS image that you would
	  like to add to your ROM.

config VGA_BIOS_FILE
	string "VGA BIOS image filename"
	depends on HAVE_VGA_BIOS
	default "vga.bin"
	help
	  The filename of the VGA BIOS image in the board directory.

config VGA_BIOS_ADDR
	hex "VGA BIOS image location"
	depends on HAVE_VGA_BIOS
	default 0xfff90000
	help
	  The location of VGA BIOS image in the SPI flash. For example, base
	  address of 0xfff90000 indicates that the image will be put at offset
	  0x90000 from the beginning of a 1MB flash device.

menu "System tables"
	depends on !EFI && !SYS_COREBOOT

config GENERATE_PIRQ_TABLE
	bool "Generate a PIRQ table"
	default n
	help
	  Generate a PIRQ routing table for this board. The PIRQ routing table
	  is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
	  at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
	  It specifies the interrupt router information as well how all the PCI
	  devices' interrupt pins are wired to PIRQs.

config GENERATE_SFI_TABLE
	bool "Generate a SFI (Simple Firmware Interface) table"
	help
	  The Simple Firmware Interface (SFI) provides a lightweight method
	  for platform firmware to pass information to the operating system
	  via static tables in memory.  Kernel SFI support is required to
	  boot on SFI-only platforms.  If you have ACPI tables then these are
	  used instead.

	  U-Boot writes this table in write_sfi_table() just before booting
	  the OS.

	  For more information, see http://simplefirmware.org

config GENERATE_MP_TABLE
	bool "Generate an MP (Multi-Processor) table"
	default n
	help
	  Generate an MP (Multi-Processor) table for this board. The MP table
	  provides a way for the operating system to support for symmetric
	  multiprocessing as well as symmetric I/O interrupt handling with
	  the local APIC and I/O APIC.

config GENERATE_ACPI_TABLE
	bool "Generate an ACPI (Advanced Configuration and Power Interface) table"
	default n
	help
	  The Advanced Configuration and Power Interface (ACPI) specification
	  provides an open standard for device configuration and management
	  by the operating system. It defines platform-independent interfaces
	  for configuration and power management monitoring.

config QEMU_ACPI_TABLE
	bool "Load ACPI table from QEMU fw_cfg interface"
	depends on GENERATE_ACPI_TABLE && QEMU
	default y
	help
	  By default, U-Boot generates its own ACPI tables. This option, if
	  enabled, disables U-Boot's version and loads ACPI tables generated
	  by QEMU.

config GENERATE_SMBIOS_TABLE
	bool "Generate an SMBIOS (System Management BIOS) table"
	default y
	help
	  The System Management BIOS (SMBIOS) specification addresses how
	  motherboard and system vendors present management information about
	  their products in a standard format by extending the BIOS interface
	  on Intel architecture systems.

	  Check http://www.dmtf.org/standards/smbios for details.

endmenu

config MAX_PIRQ_LINKS
	int
	default 8
	help
	  This variable specifies the number of PIRQ interrupt links which are
	  routable. On most older chipsets, this is 4, PIRQA through PIRQD.
	  Some newer chipsets offer more than four links, commonly up to PIRQH.

config IRQ_SLOT_COUNT
	int
	default 128
	help
	  U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
	  which in turns forms a table of exact 4KiB. The default value 128
	  should be enough for most boards. If this does not fit your board,
	  change it according to your needs.

config PCIE_ECAM_BASE
	hex
	default 0xe0000000
	help
	  This is the memory-mapped address of PCI configuration space, which
	  is only available through the Enhanced Configuration Access
	  Mechanism (ECAM) with PCI Express. It can be set up almost
	  anywhere. Before it is set up, it is possible to access PCI
	  configuration space through I/O access, but memory access is more
	  convenient. Using this, PCI can be scanned and configured. This
	  should be set to a region that does not conflict with memory
	  assigned to PCI devices - i.e. the memory and prefetch regions, as
	  passed to pci_set_region().

config PCIE_ECAM_SIZE
	hex
	default 0x10000000
	help
	  This is the size of memory-mapped address of PCI configuration space,
	  which is only available through the Enhanced Configuration Access
	  Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory,
	  so a default 0x10000000 size covers all of the 256 buses which is the
	  maximum number of PCI buses as defined by the PCI specification.

config I8259_PIC
	bool
	default y
	help
	  Intel 8259 ISA compatible chipset incorporates two 8259 (master and
	  slave) interrupt controllers. Include this to have U-Boot set up
	  the interrupt correctly.

config I8254_TIMER
	bool
	default y
	help
	  Intel 8254 timer contains three counters which have fixed uses.
	  Include this to have U-Boot set up the timer correctly.

config I8042_KEYB
	default y

config DM_KEYBOARD
	default y

config SEABIOS
	bool "Support booting SeaBIOS"
	help
	  SeaBIOS is an open source implementation of a 16-bit X86 BIOS.
	  It can run in an emulator or natively on X86 hardware with the use
	  of coreboot/U-Boot. By turning on this option, U-Boot prepares
	  all the configuration tables that are necessary to boot SeaBIOS.

	  Check http://www.seabios.org/SeaBIOS for details.

source "arch/x86/lib/efi/Kconfig"

endmenu
Commit	Line	Data
dd84058d MY	1	menu "x86 architecture"
	2	depends on X86
	3
	4	config SYS_ARCH
dd84058d MY	5	default "x86"
	6
	7	choice
65c4ac0a	8	prompt "Mainboard vendor"
99a309f3	9	default VENDOR_EMULATION
dd84058d	10
65c4ac0a BM	11	config VENDOR_COREBOOT
65c4ac0a BM	12	bool "coreboot"
3a1a18ff	13
3dcdd17b BS	14	config VENDOR_EFI
	15	bool "efi"
	16
a65b25d1 BM	17	config VENDOR_EMULATION
	18	bool "emulation"
	19
65c4ac0a BM	20	config VENDOR_GOOGLE
65c4ac0a BM	21	bool "Google"
3a1a18ff	22
65c4ac0a BM	23	config VENDOR_INTEL
65c4ac0a BM	24	bool "Intel"
ef46bea0	25
dd84058d MY	26	endchoice
dd84058d MY	27
65c4ac0a BM	28	# board-specific options below
65c4ac0a BM	29	source "board/coreboot/Kconfig"
3e9aa320	30	source "board/efi/Kconfig"
a65b25d1	31	source "board/emulation/Kconfig"
65c4ac0a BM	32	source "board/google/Kconfig"
	33	source "board/intel/Kconfig"
	34
029194a3 BM	35	# platform-specific options below
	36	source "arch/x86/cpu/baytrail/Kconfig"
	37	source "arch/x86/cpu/coreboot/Kconfig"
	38	source "arch/x86/cpu/ivybridge/Kconfig"
a65b25d1	39	source "arch/x86/cpu/qemu/Kconfig"
029194a3 BM	40	source "arch/x86/cpu/quark/Kconfig"
	41	source "arch/x86/cpu/queensbay/Kconfig"
	42
	43	# architecture-specific options below
	44
b724bd7d SG	45	config SYS_MALLOC_F_LEN
	46	default 0x800
	47
70a09c6c SG	48	config RAMBASE
	49	hex
	50	default 0x100000
	51
70a09c6c SG	52	config XIP_ROM_SIZE
70a09c6c SG	53	hex
7698d36a	54	depends on X86_RESET_VECTOR
bbd43d65	55	default ROM_SIZE
70a09c6c SG	56
	57	config CPU_ADDR_BITS
	58	int
	59	default 36
	60
65dd74a6 SG	61	config HPET_ADDRESS
	62	hex
	63	default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
	64
	65	config SMM_TSEG
	66	bool
	67	default n
	68
	69	config SMM_TSEG_SIZE
	70	hex
	71
8cb20ccc BM	72	config X86_RESET_VECTOR
	73	bool
	74	default n
	75
343fb990 BM	76	config RESET_SEG_START
	77	hex
	78	depends on X86_RESET_VECTOR
	79	default 0xffff0000
	80
	81	config RESET_SEG_SIZE
	82	hex
	83	depends on X86_RESET_VECTOR
	84	default 0x10000
	85
	86	config RESET_VEC_LOC
	87	hex
	88	depends on X86_RESET_VECTOR
	89	default 0xfffffff0
	90
8cb20ccc BM	91	config SYS_X86_START16
	92	hex
	93	depends on X86_RESET_VECTOR
	94	default 0xfffff800
	95
64542f46 BM	96	config BOARD_ROMSIZE_KB_512
	97	bool
	98	config BOARD_ROMSIZE_KB_1024
	99	bool
	100	config BOARD_ROMSIZE_KB_2048
	101	bool
	102	config BOARD_ROMSIZE_KB_4096
	103	bool
	104	config BOARD_ROMSIZE_KB_8192
	105	bool
	106	config BOARD_ROMSIZE_KB_16384
	107	bool
	108
	109	choice
	110	prompt "ROM chip size"
7698d36a	111	depends on X86_RESET_VECTOR
64542f46 BM	112	default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
	113	default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
	114	default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
	115	default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
	116	default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
	117	default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
	118	help
	119	Select the size of the ROM chip you intend to flash U-Boot on.
	120
	121	The build system will take care of creating a u-boot.rom file
	122	of the matching size.
	123
	124	config UBOOT_ROMSIZE_KB_512
	125	bool "512 KB"
	126	help
	127	Choose this option if you have a 512 KB ROM chip.
	128
	129	config UBOOT_ROMSIZE_KB_1024
	130	bool "1024 KB (1 MB)"
	131	help
	132	Choose this option if you have a 1024 KB (1 MB) ROM chip.
	133
	134	config UBOOT_ROMSIZE_KB_2048
	135	bool "2048 KB (2 MB)"
	136	help
	137	Choose this option if you have a 2048 KB (2 MB) ROM chip.
	138
	139	config UBOOT_ROMSIZE_KB_4096
	140	bool "4096 KB (4 MB)"
	141	help
	142	Choose this option if you have a 4096 KB (4 MB) ROM chip.
	143
	144	config UBOOT_ROMSIZE_KB_8192
	145	bool "8192 KB (8 MB)"
	146	help
	147	Choose this option if you have a 8192 KB (8 MB) ROM chip.
	148
	149	config UBOOT_ROMSIZE_KB_16384
	150	bool "16384 KB (16 MB)"
	151	help
	152	Choose this option if you have a 16384 KB (16 MB) ROM chip.
	153
	154	endchoice
	155
	156	# Map the config names to an integer (KB).
	157	config UBOOT_ROMSIZE_KB
	158	int
	159	default 512 if UBOOT_ROMSIZE_KB_512
	160	default 1024 if UBOOT_ROMSIZE_KB_1024
	161	default 2048 if UBOOT_ROMSIZE_KB_2048
	162	default 4096 if UBOOT_ROMSIZE_KB_4096
	163	default 8192 if UBOOT_ROMSIZE_KB_8192
	164	default 16384 if UBOOT_ROMSIZE_KB_16384
	165
	166	# Map the config names to a hex value (bytes).
fce7b276 SG	167	config ROM_SIZE
fce7b276 SG	168	hex
64542f46 BM	169	default 0x80000 if UBOOT_ROMSIZE_KB_512
	170	default 0x100000 if UBOOT_ROMSIZE_KB_1024
	171	default 0x200000 if UBOOT_ROMSIZE_KB_2048
	172	default 0x400000 if UBOOT_ROMSIZE_KB_4096
	173	default 0x800000 if UBOOT_ROMSIZE_KB_8192
	174	default 0xc00000 if UBOOT_ROMSIZE_KB_12288
	175	default 0x1000000 if UBOOT_ROMSIZE_KB_16384
fce7b276 SG	176
	177	config HAVE_INTEL_ME
	178	bool "Platform requires Intel Management Engine"
	179	help
	180	Newer higher-end devices have an Intel Management Engine (ME)
	181	which is a very large binary blob (typically 1.5MB) which is
	182	required for the platform to work. This enforces a particular
	183	SPI flash format. You will need to supply the me.bin file in
	184	your board directory.
	185
65dd74a6 SG	186	config X86_RAMTEST
	187	bool "Perform a simple RAM test after SDRAM initialisation"
	188	help
	189	If there is something wrong with SDRAM then the platform will
	190	often crash within U-Boot or the kernel. This option enables a
	191	very simple RAM test that quickly checks whether the SDRAM seems
	192	to work correctly. It is not exhaustive but can save time by
	193	detecting obvious failures.
	194
8ce24cd9 SG	195	config HAVE_FSP
8ce24cd9 SG	196	bool "Add an Firmware Support Package binary"
e49cceac	197	depends on !EFI
8ce24cd9 SG	198	help
	199	Select this option to add an Firmware Support Package binary to
	200	the resulting U-Boot image. It is a binary blob which U-Boot uses
	201	to set up SDRAM and other chipset specific initialization.
	202
	203	Note: Without this binary U-Boot will not be able to set up its
	204	SDRAM so will not boot.
	205
	206	config FSP_FILE
	207	string "Firmware Support Package binary filename"
	208	depends on HAVE_FSP
	209	default "fsp.bin"
	210	help
	211	The filename of the file to use as Firmware Support Package binary
	212	in the board directory.
	213
	214	config FSP_ADDR
	215	hex "Firmware Support Package binary location"
	216	depends on HAVE_FSP
	217	default 0xfffc0000
	218	help
	219	FSP is not Position Independent Code (PIC) and the whole FSP has to
	220	be rebased if it is placed at a location which is different from the
	221	perferred base address specified during the FSP build. Use Intel's
	222	Binary Configuration Tool (BCT) to do the rebase.
	223
	224	The default base address of 0xfffc0000 indicates that the binary must
	225	be located at offset 0xc0000 from the beginning of a 1MB flash device.
	226
	227	config FSP_TEMP_RAM_ADDR
	228	hex
d04e30b8	229	depends on HAVE_FSP
8ce24cd9 SG	230	default 0x2000000
8ce24cd9 SG	231	help
48aa6c26	232	Stack top address which is used in fsp_init() after DRAM is ready and
8ce24cd9 SG	233	CAR is disabled.
8ce24cd9 SG	234
57b10f59 BM	235	config FSP_SYS_MALLOC_F_LEN
	236	hex
	237	depends on HAVE_FSP
	238	default 0x100000
	239	help
	240	Additional size of malloc() pool before relocation.
	241
3340f2cc BM	242	config FSP_USE_UPD
	243	bool
	244	depends on HAVE_FSP
	245	default y
	246	help
	247	Most FSPs use UPD data region for some FSP customization. But there
	248	are still some FSPs that might not even have UPD. For such FSPs,
	249	override this to n in their platform Kconfig files.
	250
dc5be508 BM	251	config FSP_BROKEN_HOB
	252	bool
	253	depends on HAVE_FSP
	254	help
	255	Indicate some buggy FSPs that does not report memory used by FSP
	256	itself as reserved in the resource descriptor HOB. Select this to
	257	tell U-Boot to do some additional work to ensure U-Boot relocation
	258	do not overwrite the important boot service data which is used by
	259	FSP, otherwise the subsequent call to fsp_notify() will fail.
	260
e2d76e95 BM	261	config ENABLE_MRC_CACHE
	262	bool "Enable MRC cache"
	263	depends on !EFI && !SYS_COREBOOT
	264	help
	265	Enable this feature to cause MRC data to be cached in NV storage
	266	to be used for speeding up boot time on future reboots and/or
	267	power cycles.
	268
45b5a378 SG	269	config SMP
	270	bool "Enable Symmetric Multiprocessing"
	271	default n
	272	help
	273	Enable use of more than one CPU in U-Boot and the Operating System
	274	when loaded. Each CPU will be started up and information can be
	275	obtained using the 'cpu' command. If this option is disabled, then
	276	only one CPU will be enabled regardless of the number of CPUs
	277	available.
	278
4c71322b BM	279	config MAX_CPUS
	280	int "Maximum number of CPUs permitted"
	281	depends on SMP
	282	default 4
	283	help
	284	When using multi-CPU chips it is possible for U-Boot to start up
	285	more than one CPU. The stack memory used by all of these CPUs is
	286	pre-allocated so at present U-Boot wants to know the maximum
	287	number of CPUs that may be present. Set this to at least as high
	288	as the number of CPUs in your system (it uses about 4KB of RAM for
	289	each CPU).
	290
45b5a378 SG	291	config AP_STACK_SIZE
45b5a378 SG	292	hex
063374d2	293	depends on SMP
45b5a378 SG	294	default 0x1000
	295	help
	296	Each additional CPU started by U-Boot requires its own stack. This
	297	option sets the stack size used by each CPU and directly affects
	298	the memory used by this initialisation process. Typically 4KB is
	299	enough space.
	300
786a08e0 BM	301	config HAVE_VGA_BIOS
	302	bool "Add a VGA BIOS image"
	303	help
	304	Select this option if you have a VGA BIOS image that you would
	305	like to add to your ROM.
	306
	307	config VGA_BIOS_FILE
	308	string "VGA BIOS image filename"
	309	depends on HAVE_VGA_BIOS
	310	default "vga.bin"
	311	help
	312	The filename of the VGA BIOS image in the board directory.
	313
	314	config VGA_BIOS_ADDR
	315	hex "VGA BIOS image location"
	316	depends on HAVE_VGA_BIOS
	317	default 0xfff90000
	318	help
	319	The location of VGA BIOS image in the SPI flash. For example, base
	320	address of 0xfff90000 indicates that the image will be put at offset
	321	0x90000 from the beginning of a 1MB flash device.
	322
b5b6b019	323	menu "System tables"
8744bef5	324	depends on !EFI && !SYS_COREBOOT
b5b6b019 BM	325
	326	config GENERATE_PIRQ_TABLE
	327	bool "Generate a PIRQ table"
	328	default n
	329	help
	330	Generate a PIRQ routing table for this board. The PIRQ routing table
	331	is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
	332	at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
	333	It specifies the interrupt router information as well how all the PCI
	334	devices' interrupt pins are wired to PIRQs.
	335
6388e357 SG	336	config GENERATE_SFI_TABLE
	337	bool "Generate a SFI (Simple Firmware Interface) table"
	338	help
	339	The Simple Firmware Interface (SFI) provides a lightweight method
	340	for platform firmware to pass information to the operating system
	341	via static tables in memory. Kernel SFI support is required to
	342	boot on SFI-only platforms. If you have ACPI tables then these are
	343	used instead.
	344
	345	U-Boot writes this table in write_sfi_table() just before booting
	346	the OS.
	347
	348	For more information, see http://simplefirmware.org
	349
07545d86 BM	350	config GENERATE_MP_TABLE
	351	bool "Generate an MP (Multi-Processor) table"
	352	default n
	353	help
	354	Generate an MP (Multi-Processor) table for this board. The MP table
	355	provides a way for the operating system to support for symmetric
	356	multiprocessing as well as symmetric I/O interrupt handling with
	357	the local APIC and I/O APIC.
	358
867bcb63 SS	359	config GENERATE_ACPI_TABLE
	360	bool "Generate an ACPI (Advanced Configuration and Power Interface) table"
	361	default n
	362	help
	363	The Advanced Configuration and Power Interface (ACPI) specification
	364	provides an open standard for device configuration and management
	365	by the operating system. It defines platform-independent interfaces
	366	for configuration and power management monitoring.
	367
a5dd1e67 MY	368	config QEMU_ACPI_TABLE
	369	bool "Load ACPI table from QEMU fw_cfg interface"
	370	depends on GENERATE_ACPI_TABLE && QEMU
	371	default y
	372	help
	373	By default, U-Boot generates its own ACPI tables. This option, if
	374	enabled, disables U-Boot's version and loads ACPI tables generated
	375	by QEMU.
	376
721e992a BM	377	config GENERATE_SMBIOS_TABLE
	378	bool "Generate an SMBIOS (System Management BIOS) table"
	379	default y
	380	help
	381	The System Management BIOS (SMBIOS) specification addresses how
	382	motherboard and system vendors present management information about
	383	their products in a standard format by extending the BIOS interface
	384	on Intel architecture systems.
	385
	386	Check http://www.dmtf.org/standards/smbios for details.
	387
b5b6b019 BM	388	endmenu
	389
	390	config MAX_PIRQ_LINKS
	391	int
	392	default 8
	393	help
	394	This variable specifies the number of PIRQ interrupt links which are
	395	routable. On most older chipsets, this is 4, PIRQA through PIRQD.
	396	Some newer chipsets offer more than four links, commonly up to PIRQH.
	397
	398	config IRQ_SLOT_COUNT
	399	int
	400	default 128
	401	help
	402	U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
	403	which in turns forms a table of exact 4KiB. The default value 128
	404	should be enough for most boards. If this does not fit your board,
	405	change it according to your needs.
	406
2d934e57 SG	407	config PCIE_ECAM_BASE
2d934e57 SG	408	hex
ba877efb	409	default 0xe0000000
2d934e57 SG	410	help
	411	This is the memory-mapped address of PCI configuration space, which
	412	is only available through the Enhanced Configuration Access
	413	Mechanism (ECAM) with PCI Express. It can be set up almost
	414	anywhere. Before it is set up, it is possible to access PCI
	415	configuration space through I/O access, but memory access is more
	416	convenient. Using this, PCI can be scanned and configured. This
	417	should be set to a region that does not conflict with memory
	418	assigned to PCI devices - i.e. the memory and prefetch regions, as
	419	passed to pci_set_region().
	420
1ed6648b BM	421	config PCIE_ECAM_SIZE
	422	hex
	423	default 0x10000000
	424	help
	425	This is the size of memory-mapped address of PCI configuration space,
	426	which is only available through the Enhanced Configuration Access
	427	Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory,
	428	so a default 0x10000000 size covers all of the 256 buses which is the
	429	maximum number of PCI buses as defined by the PCI specification.
	430
1eb39a50 BM	431	config I8259_PIC
	432	bool
	433	default y
	434	help
	435	Intel 8259 ISA compatible chipset incorporates two 8259 (master and
	436	slave) interrupt controllers. Include this to have U-Boot set up
	437	the interrupt correctly.
	438
	439	config I8254_TIMER
	440	bool
	441	default y
	442	help
	443	Intel 8254 timer contains three counters which have fixed uses.
	444	Include this to have U-Boot set up the timer correctly.
	445
6b44ae6b SG	446	config I8042_KEYB
	447	default y
	448
	449	config DM_KEYBOARD
	450	default y
	451
3cf23719 BM	452	config SEABIOS
	453	bool "Support booting SeaBIOS"
	454	help
	455	SeaBIOS is an open source implementation of a 16-bit X86 BIOS.
	456	It can run in an emulator or natively on X86 hardware with the use
	457	of coreboot/U-Boot. By turning on this option, U-Boot prepares
	458	all the configuration tables that are necessary to boot SeaBIOS.
	459
	460	Check http://www.seabios.org/SeaBIOS for details.
	461
e49cceac SG	462	source "arch/x86/lib/efi/Kconfig"
e49cceac SG	463
dd84058d	464	endmenu