[u-boot.git] / arch / x86 / Kconfig

menu "x86 architecture"
	depends on X86

config SYS_ARCH
	default "x86"

choice
	prompt "Mainboard vendor"
	default VENDOR_EMULATION

config VENDOR_COREBOOT
	bool "coreboot"

config VENDOR_EMULATION
	bool "emulation"

config VENDOR_GOOGLE
	bool "Google"

config VENDOR_INTEL
	bool "Intel"

endchoice

# board-specific options below
source "board/coreboot/Kconfig"
source "board/emulation/Kconfig"
source "board/google/Kconfig"
source "board/intel/Kconfig"

# platform-specific options below
source "arch/x86/cpu/baytrail/Kconfig"
source "arch/x86/cpu/coreboot/Kconfig"
source "arch/x86/cpu/ivybridge/Kconfig"
source "arch/x86/cpu/qemu/Kconfig"
source "arch/x86/cpu/quark/Kconfig"
source "arch/x86/cpu/queensbay/Kconfig"

# architecture-specific options below

config SYS_MALLOC_F_LEN
	default 0x800

config RAMBASE
	hex
	default 0x100000

config XIP_ROM_SIZE
	hex
	depends on X86_RESET_VECTOR
	default ROM_SIZE

config CPU_ADDR_BITS
	int
	default 36

config HPET_ADDRESS
	hex
	default 0xfed00000 if !HPET_ADDRESS_OVERRIDE

config SMM_TSEG
	bool
	default n

config SMM_TSEG_SIZE
	hex

config X86_RESET_VECTOR
	bool
	default n

config RESET_SEG_START
	hex
	depends on X86_RESET_VECTOR
	default 0xffff0000

config RESET_SEG_SIZE
	hex
	depends on X86_RESET_VECTOR
	default 0x10000

config RESET_VEC_LOC
	hex
	depends on X86_RESET_VECTOR
	default 0xfffffff0

config SYS_X86_START16
	hex
	depends on X86_RESET_VECTOR
	default 0xfffff800

config BOARD_ROMSIZE_KB_512
	bool
config BOARD_ROMSIZE_KB_1024
	bool
config BOARD_ROMSIZE_KB_2048
	bool
config BOARD_ROMSIZE_KB_4096
	bool
config BOARD_ROMSIZE_KB_8192
	bool
config BOARD_ROMSIZE_KB_16384
	bool

choice
	prompt "ROM chip size"
	depends on X86_RESET_VECTOR
	default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
	default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
	default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
	default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
	default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
	default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
	help
	  Select the size of the ROM chip you intend to flash U-Boot on.

	  The build system will take care of creating a u-boot.rom file
	  of the matching size.

config UBOOT_ROMSIZE_KB_512
	bool "512 KB"
	help
	  Choose this option if you have a 512 KB ROM chip.

config UBOOT_ROMSIZE_KB_1024
	bool "1024 KB (1 MB)"
	help
	  Choose this option if you have a 1024 KB (1 MB) ROM chip.

config UBOOT_ROMSIZE_KB_2048
	bool "2048 KB (2 MB)"
	help
	  Choose this option if you have a 2048 KB (2 MB) ROM chip.

config UBOOT_ROMSIZE_KB_4096
	bool "4096 KB (4 MB)"
	help
	  Choose this option if you have a 4096 KB (4 MB) ROM chip.

config UBOOT_ROMSIZE_KB_8192
	bool "8192 KB (8 MB)"
	help
	  Choose this option if you have a 8192 KB (8 MB) ROM chip.

config UBOOT_ROMSIZE_KB_16384
	bool "16384 KB (16 MB)"
	help
	  Choose this option if you have a 16384 KB (16 MB) ROM chip.

endchoice

# Map the config names to an integer (KB).
config UBOOT_ROMSIZE_KB
	int
	default 512 if UBOOT_ROMSIZE_KB_512
	default 1024 if UBOOT_ROMSIZE_KB_1024
	default 2048 if UBOOT_ROMSIZE_KB_2048
	default 4096 if UBOOT_ROMSIZE_KB_4096
	default 8192 if UBOOT_ROMSIZE_KB_8192
	default 16384 if UBOOT_ROMSIZE_KB_16384

# Map the config names to a hex value (bytes).
config ROM_SIZE
	hex
	default 0x80000 if UBOOT_ROMSIZE_KB_512
	default 0x100000 if UBOOT_ROMSIZE_KB_1024
	default 0x200000 if UBOOT_ROMSIZE_KB_2048
	default 0x400000 if UBOOT_ROMSIZE_KB_4096
	default 0x800000 if UBOOT_ROMSIZE_KB_8192
	default 0xc00000 if UBOOT_ROMSIZE_KB_12288
	default 0x1000000 if UBOOT_ROMSIZE_KB_16384

config HAVE_INTEL_ME
	bool "Platform requires Intel Management Engine"
	help
	  Newer higher-end devices have an Intel Management Engine (ME)
	  which is a very large binary blob (typically 1.5MB) which is
	  required for the platform to work. This enforces a particular
	  SPI flash format. You will need to supply the me.bin file in
	  your board directory.

config X86_RAMTEST
	bool "Perform a simple RAM test after SDRAM initialisation"
	help
	  If there is something wrong with SDRAM then the platform will
	  often crash within U-Boot or the kernel. This option enables a
	  very simple RAM test that quickly checks whether the SDRAM seems
	  to work correctly. It is not exhaustive but can save time by
	  detecting obvious failures.

config HAVE_FSP
	bool "Add an Firmware Support Package binary"
	help
	  Select this option to add an Firmware Support Package binary to
	  the resulting U-Boot image. It is a binary blob which U-Boot uses
	  to set up SDRAM and other chipset specific initialization.

	  Note: Without this binary U-Boot will not be able to set up its
	  SDRAM so will not boot.

config FSP_FILE
	string "Firmware Support Package binary filename"
	depends on HAVE_FSP
	default "fsp.bin"
	help
	  The filename of the file to use as Firmware Support Package binary
	  in the board directory.

config FSP_ADDR
	hex "Firmware Support Package binary location"
	depends on HAVE_FSP
	default 0xfffc0000
	help
	  FSP is not Position Independent Code (PIC) and the whole FSP has to
	  be rebased if it is placed at a location which is different from the
	  perferred base address specified during the FSP build. Use Intel's
	  Binary Configuration Tool (BCT) to do the rebase.

	  The default base address of 0xfffc0000 indicates that the binary must
	  be located at offset 0xc0000 from the beginning of a 1MB flash device.

config FSP_TEMP_RAM_ADDR
	hex
	depends on HAVE_FSP
	default 0x2000000
	help
	  Stack top address which is used in FspInit after DRAM is ready and
	  CAR is disabled.

config SMP
	bool "Enable Symmetric Multiprocessing"
	default n
	help
	  Enable use of more than one CPU in U-Boot and the Operating System
	  when loaded. Each CPU will be started up and information can be
	  obtained using the 'cpu' command. If this option is disabled, then
	  only one CPU will be enabled regardless of the number of CPUs
	  available.

config MAX_CPUS
	int "Maximum number of CPUs permitted"
	depends on SMP
	default 4
	help
	  When using multi-CPU chips it is possible for U-Boot to start up
	  more than one CPU. The stack memory used by all of these CPUs is
	  pre-allocated so at present U-Boot wants to know the maximum
	  number of CPUs that may be present. Set this to at least as high
	  as the number of CPUs in your system (it uses about 4KB of RAM for
	  each CPU).

config AP_STACK_SIZE
	hex
	depends on SMP
	default 0x1000
	help
	  Each additional CPU started by U-Boot requires its own stack. This
	  option sets the stack size used by each CPU and directly affects
	  the memory used by this initialisation process. Typically 4KB is
	  enough space.

config TSC_CALIBRATION_BYPASS
	bool "Bypass Time-Stamp Counter (TSC) calibration"
	default n
	help
	  By default U-Boot automatically calibrates Time-Stamp Counter (TSC)
	  running frequency via Model-Specific Register (MSR) and Programmable
	  Interval Timer (PIT). If the calibration does not work on your board,
	  select this option and provide a hardcoded TSC running frequency with
	  CONFIG_TSC_FREQ_IN_MHZ below.

	  Normally this option should be turned on in a simulation environment
	  like qemu.

config TSC_FREQ_IN_MHZ
	int "Time-Stamp Counter (TSC) running frequency in MHz"
	depends on TSC_CALIBRATION_BYPASS
	default 1000
	help
	  The running frequency in MHz of Time-Stamp Counter (TSC).

config HAVE_VGA_BIOS
	bool "Add a VGA BIOS image"
	help
	  Select this option if you have a VGA BIOS image that you would
	  like to add to your ROM.

config VGA_BIOS_FILE
	string "VGA BIOS image filename"
	depends on HAVE_VGA_BIOS
	default "vga.bin"
	help
	  The filename of the VGA BIOS image in the board directory.

config VGA_BIOS_ADDR
	hex "VGA BIOS image location"
	depends on HAVE_VGA_BIOS
	default 0xfff90000
	help
	  The location of VGA BIOS image in the SPI flash. For example, base
	  address of 0xfff90000 indicates that the image will be put at offset
	  0x90000 from the beginning of a 1MB flash device.

menu "System tables"

config GENERATE_PIRQ_TABLE
	bool "Generate a PIRQ table"
	default n
	help
	  Generate a PIRQ routing table for this board. The PIRQ routing table
	  is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
	  at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
	  It specifies the interrupt router information as well how all the PCI
	  devices' interrupt pins are wired to PIRQs.

config GENERATE_SFI_TABLE
	bool "Generate a SFI (Simple Firmware Interface) table"
	help
	  The Simple Firmware Interface (SFI) provides a lightweight method
	  for platform firmware to pass information to the operating system
	  via static tables in memory.  Kernel SFI support is required to
	  boot on SFI-only platforms.  If you have ACPI tables then these are
	  used instead.

	  U-Boot writes this table in write_sfi_table() just before booting
	  the OS.

	  For more information, see http://simplefirmware.org

config GENERATE_MP_TABLE
	bool "Generate an MP (Multi-Processor) table"
	default n
	help
	  Generate an MP (Multi-Processor) table for this board. The MP table
	  provides a way for the operating system to support for symmetric
	  multiprocessing as well as symmetric I/O interrupt handling with
	  the local APIC and I/O APIC.

endmenu

config MAX_PIRQ_LINKS
	int
	default 8
	help
	  This variable specifies the number of PIRQ interrupt links which are
	  routable. On most older chipsets, this is 4, PIRQA through PIRQD.
	  Some newer chipsets offer more than four links, commonly up to PIRQH.

config IRQ_SLOT_COUNT
	int
	default 128
	help
	  U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
	  which in turns forms a table of exact 4KiB. The default value 128
	  should be enough for most boards. If this does not fit your board,
	  change it according to your needs.

config PCIE_ECAM_BASE
	hex
	default 0xe0000000
	help
	  This is the memory-mapped address of PCI configuration space, which
	  is only available through the Enhanced Configuration Access
	  Mechanism (ECAM) with PCI Express. It can be set up almost
	  anywhere. Before it is set up, it is possible to access PCI
	  configuration space through I/O access, but memory access is more
	  convenient. Using this, PCI can be scanned and configured. This
	  should be set to a region that does not conflict with memory
	  assigned to PCI devices - i.e. the memory and prefetch regions, as
	  passed to pci_set_region().

endmenu
Commit	Line	Data
dd84058d MY	1	menu "x86 architecture"
	2	depends on X86
	3
	4	config SYS_ARCH
dd84058d MY	5	default "x86"
	6
	7	choice
65c4ac0a	8	prompt "Mainboard vendor"
99a309f3	9	default VENDOR_EMULATION
dd84058d	10
65c4ac0a BM	11	config VENDOR_COREBOOT
65c4ac0a BM	12	bool "coreboot"
3a1a18ff	13
a65b25d1 BM	14	config VENDOR_EMULATION
	15	bool "emulation"
	16
65c4ac0a BM	17	config VENDOR_GOOGLE
65c4ac0a BM	18	bool "Google"
3a1a18ff	19
65c4ac0a BM	20	config VENDOR_INTEL
65c4ac0a BM	21	bool "Intel"
ef46bea0	22
dd84058d MY	23	endchoice
dd84058d MY	24
65c4ac0a BM	25	# board-specific options below
65c4ac0a BM	26	source "board/coreboot/Kconfig"
a65b25d1	27	source "board/emulation/Kconfig"
65c4ac0a BM	28	source "board/google/Kconfig"
	29	source "board/intel/Kconfig"
	30
029194a3 BM	31	# platform-specific options below
	32	source "arch/x86/cpu/baytrail/Kconfig"
	33	source "arch/x86/cpu/coreboot/Kconfig"
	34	source "arch/x86/cpu/ivybridge/Kconfig"
a65b25d1	35	source "arch/x86/cpu/qemu/Kconfig"
029194a3 BM	36	source "arch/x86/cpu/quark/Kconfig"
	37	source "arch/x86/cpu/queensbay/Kconfig"
	38
	39	# architecture-specific options below
	40
b724bd7d SG	41	config SYS_MALLOC_F_LEN
	42	default 0x800
	43
70a09c6c SG	44	config RAMBASE
	45	hex
	46	default 0x100000
	47
70a09c6c SG	48	config XIP_ROM_SIZE
70a09c6c SG	49	hex
7698d36a	50	depends on X86_RESET_VECTOR
bbd43d65	51	default ROM_SIZE
70a09c6c SG	52
	53	config CPU_ADDR_BITS
	54	int
	55	default 36
	56
65dd74a6 SG	57	config HPET_ADDRESS
	58	hex
	59	default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
	60
	61	config SMM_TSEG
	62	bool
	63	default n
	64
	65	config SMM_TSEG_SIZE
	66	hex
	67
8cb20ccc BM	68	config X86_RESET_VECTOR
	69	bool
	70	default n
	71
343fb990 BM	72	config RESET_SEG_START
	73	hex
	74	depends on X86_RESET_VECTOR
	75	default 0xffff0000
	76
	77	config RESET_SEG_SIZE
	78	hex
	79	depends on X86_RESET_VECTOR
	80	default 0x10000
	81
	82	config RESET_VEC_LOC
	83	hex
	84	depends on X86_RESET_VECTOR
	85	default 0xfffffff0
	86
8cb20ccc BM	87	config SYS_X86_START16
	88	hex
	89	depends on X86_RESET_VECTOR
	90	default 0xfffff800
	91
64542f46 BM	92	config BOARD_ROMSIZE_KB_512
	93	bool
	94	config BOARD_ROMSIZE_KB_1024
	95	bool
	96	config BOARD_ROMSIZE_KB_2048
	97	bool
	98	config BOARD_ROMSIZE_KB_4096
	99	bool
	100	config BOARD_ROMSIZE_KB_8192
	101	bool
	102	config BOARD_ROMSIZE_KB_16384
	103	bool
	104
	105	choice
	106	prompt "ROM chip size"
7698d36a	107	depends on X86_RESET_VECTOR
64542f46 BM	108	default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
	109	default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
	110	default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
	111	default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
	112	default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
	113	default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
	114	help
	115	Select the size of the ROM chip you intend to flash U-Boot on.
	116
	117	The build system will take care of creating a u-boot.rom file
	118	of the matching size.
	119
	120	config UBOOT_ROMSIZE_KB_512
	121	bool "512 KB"
	122	help
	123	Choose this option if you have a 512 KB ROM chip.
	124
	125	config UBOOT_ROMSIZE_KB_1024
	126	bool "1024 KB (1 MB)"
	127	help
	128	Choose this option if you have a 1024 KB (1 MB) ROM chip.
	129
	130	config UBOOT_ROMSIZE_KB_2048
	131	bool "2048 KB (2 MB)"
	132	help
	133	Choose this option if you have a 2048 KB (2 MB) ROM chip.
	134
	135	config UBOOT_ROMSIZE_KB_4096
	136	bool "4096 KB (4 MB)"
	137	help
	138	Choose this option if you have a 4096 KB (4 MB) ROM chip.
	139
	140	config UBOOT_ROMSIZE_KB_8192
	141	bool "8192 KB (8 MB)"
	142	help
	143	Choose this option if you have a 8192 KB (8 MB) ROM chip.
	144
	145	config UBOOT_ROMSIZE_KB_16384
	146	bool "16384 KB (16 MB)"
	147	help
	148	Choose this option if you have a 16384 KB (16 MB) ROM chip.
	149
	150	endchoice
	151
	152	# Map the config names to an integer (KB).
	153	config UBOOT_ROMSIZE_KB
	154	int
	155	default 512 if UBOOT_ROMSIZE_KB_512
	156	default 1024 if UBOOT_ROMSIZE_KB_1024
	157	default 2048 if UBOOT_ROMSIZE_KB_2048
	158	default 4096 if UBOOT_ROMSIZE_KB_4096
	159	default 8192 if UBOOT_ROMSIZE_KB_8192
	160	default 16384 if UBOOT_ROMSIZE_KB_16384
	161
	162	# Map the config names to a hex value (bytes).
fce7b276 SG	163	config ROM_SIZE
fce7b276 SG	164	hex
64542f46 BM	165	default 0x80000 if UBOOT_ROMSIZE_KB_512
	166	default 0x100000 if UBOOT_ROMSIZE_KB_1024
	167	default 0x200000 if UBOOT_ROMSIZE_KB_2048
	168	default 0x400000 if UBOOT_ROMSIZE_KB_4096
	169	default 0x800000 if UBOOT_ROMSIZE_KB_8192
	170	default 0xc00000 if UBOOT_ROMSIZE_KB_12288
	171	default 0x1000000 if UBOOT_ROMSIZE_KB_16384
fce7b276 SG	172
	173	config HAVE_INTEL_ME
	174	bool "Platform requires Intel Management Engine"
	175	help
	176	Newer higher-end devices have an Intel Management Engine (ME)
	177	which is a very large binary blob (typically 1.5MB) which is
	178	required for the platform to work. This enforces a particular
	179	SPI flash format. You will need to supply the me.bin file in
	180	your board directory.
	181
65dd74a6 SG	182	config X86_RAMTEST
	183	bool "Perform a simple RAM test after SDRAM initialisation"
	184	help
	185	If there is something wrong with SDRAM then the platform will
	186	often crash within U-Boot or the kernel. This option enables a
	187	very simple RAM test that quickly checks whether the SDRAM seems
	188	to work correctly. It is not exhaustive but can save time by
	189	detecting obvious failures.
	190
8ce24cd9 SG	191	config HAVE_FSP
	192	bool "Add an Firmware Support Package binary"
	193	help
	194	Select this option to add an Firmware Support Package binary to
	195	the resulting U-Boot image. It is a binary blob which U-Boot uses
	196	to set up SDRAM and other chipset specific initialization.
	197
	198	Note: Without this binary U-Boot will not be able to set up its
	199	SDRAM so will not boot.
	200
	201	config FSP_FILE
	202	string "Firmware Support Package binary filename"
	203	depends on HAVE_FSP
	204	default "fsp.bin"
	205	help
	206	The filename of the file to use as Firmware Support Package binary
	207	in the board directory.
	208
	209	config FSP_ADDR
	210	hex "Firmware Support Package binary location"
	211	depends on HAVE_FSP
	212	default 0xfffc0000
	213	help
	214	FSP is not Position Independent Code (PIC) and the whole FSP has to
	215	be rebased if it is placed at a location which is different from the
	216	perferred base address specified during the FSP build. Use Intel's
	217	Binary Configuration Tool (BCT) to do the rebase.
	218
	219	The default base address of 0xfffc0000 indicates that the binary must
	220	be located at offset 0xc0000 from the beginning of a 1MB flash device.
	221
	222	config FSP_TEMP_RAM_ADDR
	223	hex
d04e30b8	224	depends on HAVE_FSP
8ce24cd9 SG	225	default 0x2000000
	226	help
	227	Stack top address which is used in FspInit after DRAM is ready and
	228	CAR is disabled.
	229
45b5a378 SG	230	config SMP
	231	bool "Enable Symmetric Multiprocessing"
	232	default n
	233	help
	234	Enable use of more than one CPU in U-Boot and the Operating System
	235	when loaded. Each CPU will be started up and information can be
	236	obtained using the 'cpu' command. If this option is disabled, then
	237	only one CPU will be enabled regardless of the number of CPUs
	238	available.
	239
4c71322b BM	240	config MAX_CPUS
	241	int "Maximum number of CPUs permitted"
	242	depends on SMP
	243	default 4
	244	help
	245	When using multi-CPU chips it is possible for U-Boot to start up
	246	more than one CPU. The stack memory used by all of these CPUs is
	247	pre-allocated so at present U-Boot wants to know the maximum
	248	number of CPUs that may be present. Set this to at least as high
	249	as the number of CPUs in your system (it uses about 4KB of RAM for
	250	each CPU).
	251
45b5a378 SG	252	config AP_STACK_SIZE
45b5a378 SG	253	hex
063374d2	254	depends on SMP
45b5a378 SG	255	default 0x1000
	256	help
	257	Each additional CPU started by U-Boot requires its own stack. This
	258	option sets the stack size used by each CPU and directly affects
	259	the memory used by this initialisation process. Typically 4KB is
	260	enough space.
	261
f56aeaa4 BM	262	config TSC_CALIBRATION_BYPASS
	263	bool "Bypass Time-Stamp Counter (TSC) calibration"
	264	default n
	265	help
	266	By default U-Boot automatically calibrates Time-Stamp Counter (TSC)
	267	running frequency via Model-Specific Register (MSR) and Programmable
	268	Interval Timer (PIT). If the calibration does not work on your board,
	269	select this option and provide a hardcoded TSC running frequency with
	270	CONFIG_TSC_FREQ_IN_MHZ below.
	271
	272	Normally this option should be turned on in a simulation environment
	273	like qemu.
	274
	275	config TSC_FREQ_IN_MHZ
	276	int "Time-Stamp Counter (TSC) running frequency in MHz"
	277	depends on TSC_CALIBRATION_BYPASS
	278	default 1000
	279	help
	280	The running frequency in MHz of Time-Stamp Counter (TSC).
	281
786a08e0 BM	282	config HAVE_VGA_BIOS
	283	bool "Add a VGA BIOS image"
	284	help
	285	Select this option if you have a VGA BIOS image that you would
	286	like to add to your ROM.
	287
	288	config VGA_BIOS_FILE
	289	string "VGA BIOS image filename"
	290	depends on HAVE_VGA_BIOS
	291	default "vga.bin"
	292	help
	293	The filename of the VGA BIOS image in the board directory.
	294
	295	config VGA_BIOS_ADDR
	296	hex "VGA BIOS image location"
	297	depends on HAVE_VGA_BIOS
	298	default 0xfff90000
	299	help
	300	The location of VGA BIOS image in the SPI flash. For example, base
	301	address of 0xfff90000 indicates that the image will be put at offset
	302	0x90000 from the beginning of a 1MB flash device.
	303
b5b6b019 BM	304	menu "System tables"
	305
	306	config GENERATE_PIRQ_TABLE
	307	bool "Generate a PIRQ table"
	308	default n
	309	help
	310	Generate a PIRQ routing table for this board. The PIRQ routing table
	311	is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
	312	at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
	313	It specifies the interrupt router information as well how all the PCI
	314	devices' interrupt pins are wired to PIRQs.
	315
6388e357 SG	316	config GENERATE_SFI_TABLE
	317	bool "Generate a SFI (Simple Firmware Interface) table"
	318	help
	319	The Simple Firmware Interface (SFI) provides a lightweight method
	320	for platform firmware to pass information to the operating system
	321	via static tables in memory. Kernel SFI support is required to
	322	boot on SFI-only platforms. If you have ACPI tables then these are
	323	used instead.
	324
	325	U-Boot writes this table in write_sfi_table() just before booting
	326	the OS.
	327
	328	For more information, see http://simplefirmware.org
	329
07545d86 BM	330	config GENERATE_MP_TABLE
	331	bool "Generate an MP (Multi-Processor) table"
	332	default n
	333	help
	334	Generate an MP (Multi-Processor) table for this board. The MP table
	335	provides a way for the operating system to support for symmetric
	336	multiprocessing as well as symmetric I/O interrupt handling with
	337	the local APIC and I/O APIC.
	338
b5b6b019 BM	339	endmenu
	340
	341	config MAX_PIRQ_LINKS
	342	int
	343	default 8
	344	help
	345	This variable specifies the number of PIRQ interrupt links which are
	346	routable. On most older chipsets, this is 4, PIRQA through PIRQD.
	347	Some newer chipsets offer more than four links, commonly up to PIRQH.
	348
	349	config IRQ_SLOT_COUNT
	350	int
	351	default 128
	352	help
	353	U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
	354	which in turns forms a table of exact 4KiB. The default value 128
	355	should be enough for most boards. If this does not fit your board,
	356	change it according to your needs.
	357
2d934e57 SG	358	config PCIE_ECAM_BASE
2d934e57 SG	359	hex
ba877efb	360	default 0xe0000000
2d934e57 SG	361	help
	362	This is the memory-mapped address of PCI configuration space, which
	363	is only available through the Enhanced Configuration Access
	364	Mechanism (ECAM) with PCI Express. It can be set up almost
	365	anywhere. Before it is set up, it is possible to access PCI
	366	configuration space through I/O access, but memory access is more
	367	convenient. Using this, PCI can be scanned and configured. This
	368	should be set to a region that does not conflict with memory
	369	assigned to PCI devices - i.e. the memory and prefetch regions, as
	370	passed to pci_set_region().
	371
dd84058d	372	endmenu