[u-boot.git] / cpu / ppc4xx / i2c.c

/*****************************************************************************/
/* I2C Bus interface initialisation and I2C Commands                         */
/* for PPC405GP		                                                     */
/* Author : AS HARNOIS                                                       */
/* Date   : 13.Dec.00                                                        */
/*****************************************************************************/

#include <common.h>
#include <ppc4xx.h>
#if defined(CONFIG_440)
#   include <440_i2c.h>
#else
#   include <405gp_i2c.h>
#endif
#include <i2c.h>

#ifdef CONFIG_HARD_I2C

DECLARE_GLOBAL_DATA_PTR;

#define IIC_OK		0
#define IIC_NOK		1
#define IIC_NOK_LA	2		/* Lost arbitration */
#define IIC_NOK_ICT	3		/* Incomplete transfer */
#define IIC_NOK_XFRA	4		/* Transfer aborted */
#define IIC_NOK_DATA	5		/* No data in buffer */
#define IIC_NOK_TOUT	6		/* Transfer timeout */

#define IIC_TIMEOUT 1			/* 1 seconde */


static void _i2c_bus_reset (void)
{
	int i, status;

	/* Reset status register */
	/* write 1 in SCMP and IRQA to clear these fields */
	out8 (IIC_STS, 0x0A);

	/* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */
	out8 (IIC_EXTSTS, 0x8F);
	__asm__ volatile ("eieio");

	/*
	 * Get current state, reset bus
	 * only if no transfers are pending.
	 */
	i = 10;
	do {
		/* Get status */
		status = in8 (IIC_STS);
		udelay (500);			/* 500us */
		i--;
	} while ((status & IIC_STS_PT) && (i > 0));
	/* Soft reset controller */
	status = in8 (IIC_XTCNTLSS);
	out8 (IIC_XTCNTLSS, (status | IIC_XTCNTLSS_SRST));
	__asm__ volatile ("eieio");

	/* make sure where in initial state, data hi, clock hi */
	out8 (IIC_DIRECTCNTL, 0xC);
	for (i = 0; i < 10; i++) {
		if ((in8 (IIC_DIRECTCNTL) & 0x3) != 0x3) {
			/* clock until we get to known state */
			out8 (IIC_DIRECTCNTL, 0x8);	/* clock lo */
			udelay (100);		/* 100us */
			out8 (IIC_DIRECTCNTL, 0xC);	/* clock hi */
			udelay (100);		/* 100us */
		} else {
			break;
		}
	}
	/* send start condition */
	out8 (IIC_DIRECTCNTL, 0x4);
	udelay (1000);				/* 1ms */
	/* send stop condition */
	out8 (IIC_DIRECTCNTL, 0xC);
	udelay (1000);				/* 1ms */
	/* Unreset controller */
	out8 (IIC_XTCNTLSS, (status & ~IIC_XTCNTLSS_SRST));
	udelay (1000);				/* 1ms */
}

void i2c_init (int speed, int slaveadd)
{
	sys_info_t sysInfo;
	unsigned long freqOPB;
	int val, divisor;

#ifdef CFG_I2C_INIT_BOARD
	/* call board specific i2c bus reset routine before accessing the   */
	/* environment, which might be in a chip on that bus. For details   */
	/* about this problem see doc/I2C_Edge_Conditions.                  */
	i2c_init_board();
#endif

	/* Handle possible failed I2C state */
	/* FIXME: put this into i2c_init_board()? */
	_i2c_bus_reset ();

	/* clear lo master address */
	out8 (IIC_LMADR, 0);

	/* clear hi master address */
	out8 (IIC_HMADR, 0);

	/* clear lo slave address */
	out8 (IIC_LSADR, 0);

	/* clear hi slave address */
	out8 (IIC_HSADR, 0);

	/* Clock divide Register */
	/* get OPB frequency */
	get_sys_info (&sysInfo);
	freqOPB = sysInfo.freqPLB / sysInfo.pllOpbDiv;
	/* set divisor according to freqOPB */
	divisor = (freqOPB - 1) / 10000000;
	if (divisor == 0)
		divisor = 1;
	out8 (IIC_CLKDIV, divisor);

	/* no interrupts */
	out8 (IIC_INTRMSK, 0);

	/* clear transfer count */
	out8 (IIC_XFRCNT, 0);

	/* clear extended control & stat */
	/* write 1 in SRC SRS SWC SWS to clear these fields */
	out8 (IIC_XTCNTLSS, 0xF0);

	/* Mode Control Register
	   Flush Slave/Master data buffer */
	out8 (IIC_MDCNTL, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB);
	__asm__ volatile ("eieio");


	val = in8(IIC_MDCNTL);
	__asm__ volatile ("eieio");

	/* Ignore General Call, slave transfers are ignored,
	   disable interrupts, exit unknown bus state, enable hold
	   SCL
	   100kHz normaly or FastMode for 400kHz and above
	*/

	val |= IIC_MDCNTL_EUBS|IIC_MDCNTL_HSCL;
	if( speed >= 400000 ){
		val |= IIC_MDCNTL_FSM;
	}
	out8 (IIC_MDCNTL, val);

	/* clear control reg */
	out8 (IIC_CNTL, 0x00);
	__asm__ volatile ("eieio");

}

/*
  This code tries to use the features of the 405GP i2c
  controller. It will transfer up to 4 bytes in one pass
  on the loop. It only does out8(lbz) to the buffer when it
  is possible to do out16(lhz) transfers.

  cmd_type is 0 for write 1 for read.

  addr_len can take any value from 0-255, it is only limited
  by the char, we could make it larger if needed. If it is
  0 we skip the address write cycle.

  Typical case is a Write of an addr followd by a Read. The
  IBM FAQ does not cover this. On the last byte of the write
  we don't set the creg CHT bit, and on the first bytes of the
  read we set the RPST bit.

  It does not support address only transfers, there must be
  a data part. If you want to write the address yourself, put
  it in the data pointer.

  It does not support transfer to/from address 0.

  It does not check XFRCNT.
*/
static
int i2c_transfer(unsigned char cmd_type,
		 unsigned char chip,
		 unsigned char addr[],
		 unsigned char addr_len,
		 unsigned char data[],
		 unsigned short data_len )
{
	unsigned char* ptr;
	int reading;
	int tran,cnt;
	int result;
	int status;
	int i;
	uchar creg;

	if( data == 0 || data_len == 0 ){
		/*Don't support data transfer of no length or to address 0*/
		printf( "i2c_transfer: bad call\n" );
		return IIC_NOK;
	}
	if( addr && addr_len ){
		ptr = addr;
		cnt = addr_len;
		reading = 0;
	}else{
		ptr = data;
		cnt = data_len;
		reading = cmd_type;
	}

	/*Clear Stop Complete Bit*/
	out8(IIC_STS,IIC_STS_SCMP);
	/* Check init */
	i=10;
	do {
		/* Get status */
		status = in8(IIC_STS);
		__asm__ volatile("eieio");
		i--;
	} while ((status & IIC_STS_PT) && (i>0));

	if (status & IIC_STS_PT) {
		result = IIC_NOK_TOUT;
		return(result);
	}
	/*flush the Master/Slave Databuffers*/
	out8(IIC_MDCNTL, ((in8(IIC_MDCNTL))|IIC_MDCNTL_FMDB|IIC_MDCNTL_FSDB));
	/*need to wait 4 OPB clocks? code below should take that long*/

	/* 7-bit adressing */
	out8(IIC_HMADR,0);
	out8(IIC_LMADR, chip);
	__asm__ volatile("eieio");

	tran = 0;
	result = IIC_OK;
	creg = 0;

	while ( tran != cnt && (result == IIC_OK)) {
		int  bc,j;

		/* Control register =
		   Normal transfer, 7-bits adressing, Transfer up to bc bytes, Normal start,
		   Transfer is a sequence of transfers
		*/
		creg |= IIC_CNTL_PT;

		bc = (cnt - tran) > 4 ? 4 :
			cnt - tran;
		creg |= (bc-1)<<4;
		/* if the real cmd type is write continue trans*/
		if ( (!cmd_type && (ptr == addr)) || ((tran+bc) != cnt) )
			creg |= IIC_CNTL_CHT;

		if (reading)
			creg |= IIC_CNTL_READ;
		else {
			for(j=0; j<bc; j++) {
				/* Set buffer */
				out8(IIC_MDBUF,ptr[tran+j]);
				__asm__ volatile("eieio");
			}
		}
		out8(IIC_CNTL, creg );
		__asm__ volatile("eieio");

		/* Transfer is in progress
		   we have to wait for upto 5 bytes of data
		   1 byte chip address+r/w bit then bc bytes
		   of data.
		   udelay(10) is 1 bit time at 100khz
		   Doubled for slop. 20 is too small.
		*/
		i=2*5*8;
		do {
			/* Get status */
			status = in8(IIC_STS);
			__asm__ volatile("eieio");
			udelay (10);
			i--;
		} while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR)
			 && (i>0));

		if (status & IIC_STS_ERR) {
			result = IIC_NOK;
			status = in8 (IIC_EXTSTS);
			/* Lost arbitration? */
			if (status & IIC_EXTSTS_LA)
				result = IIC_NOK_LA;
			/* Incomplete transfer? */
			if (status & IIC_EXTSTS_ICT)
				result = IIC_NOK_ICT;
			/* Transfer aborted? */
			if (status & IIC_EXTSTS_XFRA)
				result = IIC_NOK_XFRA;
		} else if ( status & IIC_STS_PT) {
			result = IIC_NOK_TOUT;
		}
		/* Command is reading => get buffer */
		if ((reading) && (result == IIC_OK)) {
			/* Are there data in buffer */
			if (status & IIC_STS_MDBS) {
				/*
				  even if we have data we have to wait 4OPB clocks
				  for it to hit the front of the FIFO, after that
				  we can just read. We should check XFCNT here and
				  if the FIFO is full there is no need to wait.
				*/
				udelay (1);
				for(j=0;j<bc;j++) {
					ptr[tran+j] = in8(IIC_MDBUF);
					__asm__ volatile("eieio");
				}
			} else
				result = IIC_NOK_DATA;
		}
		creg = 0;
		tran+=bc;
		if( ptr == addr && tran == cnt ) {
			ptr = data;
			cnt = data_len;
			tran = 0;
			reading = cmd_type;
			if( reading )
				creg = IIC_CNTL_RPST;
		}
	}
	return (result);
}

int i2c_probe (uchar chip)
{
	uchar buf[1];

	buf[0] = 0;

	/*
	 * What is needed is to send the chip address and verify that the
	 * address was <ACK>ed (i.e. there was a chip at that address which
	 * drove the data line low).
	 */
	return(i2c_transfer (1, chip << 1, 0,0, buf, 1) != 0);
}


int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
{
	uchar xaddr[4];
	int ret;

	if ( alen > 4 ) {
		printf ("I2C read: addr len %d not supported\n", alen);
		return 1;
	}

	if ( alen > 0 ) {
		xaddr[0] = (addr >> 24) & 0xFF;
		xaddr[1] = (addr >> 16) & 0xFF;
		xaddr[2] = (addr >> 8) & 0xFF;
		xaddr[3] = addr & 0xFF;
	}


#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
	/*
	 * EEPROM chips that implement "address overflow" are ones
	 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
	 * address and the extra bits end up in the "chip address"
	 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
	 * four 256 byte chips.
	 *
	 * Note that we consider the length of the address field to
	 * still be one byte because the extra address bits are
	 * hidden in the chip address.
	 */
	if( alen > 0 )
		chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
#endif
	if( (ret = i2c_transfer( 1, chip<<1, &xaddr[4-alen], alen, buffer, len )) != 0) {
		if (gd->have_console)
			printf( "I2c read: failed %d\n", ret);
		return 1;
	}
	return 0;
}

int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
{
	uchar xaddr[4];

	if ( alen > 4 ) {
		printf ("I2C write: addr len %d not supported\n", alen);
		return 1;

	}
	if ( alen > 0 ) {
		xaddr[0] = (addr >> 24) & 0xFF;
		xaddr[1] = (addr >> 16) & 0xFF;
		xaddr[2] = (addr >> 8) & 0xFF;
		xaddr[3] = addr & 0xFF;
	}

#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
	/*
	 * EEPROM chips that implement "address overflow" are ones
	 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
	 * address and the extra bits end up in the "chip address"
	 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
	 * four 256 byte chips.
	 *
	 * Note that we consider the length of the address field to
	 * still be one byte because the extra address bits are
	 * hidden in the chip address.
	 */
	if( alen > 0 )
		chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
#endif

	return (i2c_transfer( 0, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0);
}

/*-----------------------------------------------------------------------
 * Read a register
 */
uchar i2c_reg_read(uchar i2c_addr, uchar reg)
{
	uchar buf;

	i2c_read(i2c_addr, reg, 1, &buf, 1);

	return(buf);
}

/*-----------------------------------------------------------------------
 * Write a register
 */
void i2c_reg_write(uchar i2c_addr, uchar reg, uchar val)
{
	i2c_write(i2c_addr, reg, 1, &val, 1);
}
#endif	/* CONFIG_HARD_I2C */
Commit	Line	Data
c609719b WD	1	/*****************************************************************************/
	2	/* I2C Bus interface initialisation and I2C Commands */
	3	/* for PPC405GP */
	4	/* Author : AS HARNOIS */
	5	/* Date : 13.Dec.00 */
	6	/*****************************************************************************/
	7
	8	#include <common.h>
	9	#include <ppc4xx.h>
	10	#if defined(CONFIG_440)
	11	# include <440_i2c.h>
	12	#else
	13	# include <405gp_i2c.h>
	14	#endif
	15	#include <i2c.h>
	16
	17	#ifdef CONFIG_HARD_I2C
	18
d87080b7 WD	19	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	20
c609719b WD	21	#define IIC_OK 0
	22	#define IIC_NOK 1
	23	#define IIC_NOK_LA 2 /* Lost arbitration */
	24	#define IIC_NOK_ICT 3 /* Incomplete transfer */
	25	#define IIC_NOK_XFRA 4 /* Transfer aborted */
	26	#define IIC_NOK_DATA 5 /* No data in buffer */
	27	#define IIC_NOK_TOUT 6 /* Transfer timeout */
	28
	29	#define IIC_TIMEOUT 1 /* 1 seconde */
	30
	31
	32	static void _i2c_bus_reset (void)
	33	{
	34	int i, status;
	35
	36	/* Reset status register */
	37	/* write 1 in SCMP and IRQA to clear these fields */
	38	out8 (IIC_STS, 0x0A);
	39
	40	/* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */
	41	out8 (IIC_EXTSTS, 0x8F);
	42	__asm__ volatile ("eieio");
	43
	44	/*
	45	* Get current state, reset bus
	46	* only if no transfers are pending.
	47	*/
	48	i = 10;
	49	do {
	50	/* Get status */
	51	status = in8 (IIC_STS);
	52	udelay (500); /* 500us */
	53	i--;
	54	} while ((status & IIC_STS_PT) && (i > 0));
	55	/* Soft reset controller */
	56	status = in8 (IIC_XTCNTLSS);
	57	out8 (IIC_XTCNTLSS, (status \| IIC_XTCNTLSS_SRST));
	58	__asm__ volatile ("eieio");
	59
	60	/* make sure where in initial state, data hi, clock hi */
	61	out8 (IIC_DIRECTCNTL, 0xC);
	62	for (i = 0; i < 10; i++) {
	63	if ((in8 (IIC_DIRECTCNTL) & 0x3) != 0x3) {
	64	/* clock until we get to known state */
	65	out8 (IIC_DIRECTCNTL, 0x8); /* clock lo */
	66	udelay (100); /* 100us */
	67	out8 (IIC_DIRECTCNTL, 0xC); /* clock hi */
	68	udelay (100); /* 100us */
	69	} else {
	70	break;
	71	}
	72	}
	73	/* send start condition */
	74	out8 (IIC_DIRECTCNTL, 0x4);
	75	udelay (1000); /* 1ms */
	76	/* send stop condition */
	77	out8 (IIC_DIRECTCNTL, 0xC);
	78	udelay (1000); /* 1ms */
	79	/* Unreset controller */
	80	out8 (IIC_XTCNTLSS, (status & ~IIC_XTCNTLSS_SRST));
	81	udelay (1000); /* 1ms */
	82	}
	83
	84	void i2c_init (int speed, int slaveadd)
85	{
86	sys_info_t sysInfo;
87	unsigned long freqOPB;
88	int val, divisor;
89
8bde7f77	90	#ifdef CFG_I2C_INIT_BOARD
47cd00fa WD	91	/* call board specific i2c bus reset routine before accessing the */
	92	/* environment, which might be in a chip on that bus. For details */
	93	/* about this problem see doc/I2C_Edge_Conditions. */
	94	i2c_init_board();
	95	#endif
	96
c609719b	97	/* Handle possible failed I2C state */
47cd00fa	98	/* FIXME: put this into i2c_init_board()? */
c609719b WD	99	_i2c_bus_reset ();
	100
	101	/* clear lo master address */
	102	out8 (IIC_LMADR, 0);
	103
	104	/* clear hi master address */
	105	out8 (IIC_HMADR, 0);
	106
	107	/* clear lo slave address */
	108	out8 (IIC_LSADR, 0);
	109
	110	/* clear hi slave address */
	111	out8 (IIC_HSADR, 0);
	112
	113	/* Clock divide Register */
	114	/* get OPB frequency */
	115	get_sys_info (&sysInfo);
	116	freqOPB = sysInfo.freqPLB / sysInfo.pllOpbDiv;
	117	/* set divisor according to freqOPB */
	118	divisor = (freqOPB - 1) / 10000000;
	119	if (divisor == 0)
	120	divisor = 1;
	121	out8 (IIC_CLKDIV, divisor);
	122
	123	/* no interrupts */
	124	out8 (IIC_INTRMSK, 0);
	125
	126	/* clear transfer count */
	127	out8 (IIC_XFRCNT, 0);
	128
	129	/* clear extended control & stat */
	130	/* write 1 in SRC SRS SWC SWS to clear these fields */
	131	out8 (IIC_XTCNTLSS, 0xF0);
	132
	133	/* Mode Control Register
	134	Flush Slave/Master data buffer */
	135	out8 (IIC_MDCNTL, IIC_MDCNTL_FSDB \| IIC_MDCNTL_FMDB);
	136	__asm__ volatile ("eieio");
	137
	138
8bde7f77 WD	139	val = in8(IIC_MDCNTL);
8bde7f77 WD	140	__asm__ volatile ("eieio");
c609719b	141
8bde7f77 WD	142	/* Ignore General Call, slave transfers are ignored,
	143	disable interrupts, exit unknown bus state, enable hold
	144	SCL
	145	100kHz normaly or FastMode for 400kHz and above
	146	*/
c609719b	147
8bde7f77 WD	148	val \|= IIC_MDCNTL_EUBS\|IIC_MDCNTL_HSCL;
	149	if( speed >= 400000 ){
	150	val \|= IIC_MDCNTL_FSM;
	151	}
c609719b WD	152	out8 (IIC_MDCNTL, val);
	153
	154	/* clear control reg */
	155	out8 (IIC_CNTL, 0x00);
	156	__asm__ volatile ("eieio");
	157
	158	}
	159
	160	/*
	161	This code tries to use the features of the 405GP i2c
	162	controller. It will transfer up to 4 bytes in one pass
	163	on the loop. It only does out8(lbz) to the buffer when it
	164	is possible to do out16(lhz) transfers.
	165
	166	cmd_type is 0 for write 1 for read.
	167
	168	addr_len can take any value from 0-255, it is only limited
	169	by the char, we could make it larger if needed. If it is
	170	0 we skip the address write cycle.
	171
	172	Typical case is a Write of an addr followd by a Read. The
	173	IBM FAQ does not cover this. On the last byte of the write
	174	we don't set the creg CHT bit, and on the first bytes of the
	175	read we set the RPST bit.
	176
	177	It does not support address only transfers, there must be
	178	a data part. If you want to write the address yourself, put
	179	it in the data pointer.
	180
	181	It does not support transfer to/from address 0.
	182
	183	It does not check XFRCNT.
	184	*/
	185	static
	186	int i2c_transfer(unsigned char cmd_type,
8bde7f77 WD	187	unsigned char chip,
	188	unsigned char addr[],
	189	unsigned char addr_len,
	190	unsigned char data[],
c609719b WD	191	unsigned short data_len )
c609719b WD	192	{
8bde7f77 WD	193	unsigned char* ptr;
	194	int reading;
	195	int tran,cnt;
	196	int result;
	197	int status;
	198	int i;
	199	uchar creg;
	200
	201	if( data == 0 \|\| data_len == 0 ){
	202	/Don't support data transfer of no length or to address 0/
	203	printf( "i2c_transfer: bad call\n" );
	204	return IIC_NOK;
	205	}
	206	if( addr && addr_len ){
	207	ptr = addr;
	208	cnt = addr_len;
	209	reading = 0;
	210	}else{
	211	ptr = data;
	212	cnt = data_len;
	213	reading = cmd_type;
	214	}
	215
	216	/Clear Stop Complete Bit/
	217	out8(IIC_STS,IIC_STS_SCMP);
	218	/* Check init */
	219	i=10;
	220	do {
	221	/* Get status */
	222	status = in8(IIC_STS);
	223	__asm__ volatile("eieio");
	224	i--;
	225	} while ((status & IIC_STS_PT) && (i>0));
	226
	227	if (status & IIC_STS_PT) {
	228	result = IIC_NOK_TOUT;
	229	return(result);
	230	}
	231	/flush the Master/Slave Databuffers/
	232	out8(IIC_MDCNTL, ((in8(IIC_MDCNTL))\|IIC_MDCNTL_FMDB\|IIC_MDCNTL_FSDB));
	233	/need to wait 4 OPB clocks? code below should take that long/
	234
	235	/* 7-bit adressing */
	236	out8(IIC_HMADR,0);
	237	out8(IIC_LMADR, chip);
	238	__asm__ volatile("eieio");
	239
	240	tran = 0;
	241	result = IIC_OK;
	242	creg = 0;
	243
	244	while ( tran != cnt && (result == IIC_OK)) {
	245	int bc,j;
	246
	247	/* Control register =
	248	Normal transfer, 7-bits adressing, Transfer up to bc bytes, Normal start,
	249	Transfer is a sequence of transfers
c609719b	250	*/
8bde7f77 WD	251	creg \|= IIC_CNTL_PT;
	252
	253	bc = (cnt - tran) > 4 ? 4 :
	254	cnt - tran;
	255	creg \|= (bc-1)<<4;
	256	/* if the real cmd type is write continue trans*/
	257	if ( (!cmd_type && (ptr == addr)) \|\| ((tran+bc) != cnt) )
	258	creg \|= IIC_CNTL_CHT;
	259
	260	if (reading)
	261	creg \|= IIC_CNTL_READ;
	262	else {
	263	for(j=0; j<bc; j++) {
	264	/* Set buffer */
	265	out8(IIC_MDBUF,ptr[tran+j]);
	266	__asm__ volatile("eieio");
	267	}
	268	}
	269	out8(IIC_CNTL, creg );
	270	__asm__ volatile("eieio");
	271
	272	/* Transfer is in progress
	273	we have to wait for upto 5 bytes of data
	274	1 byte chip address+r/w bit then bc bytes
	275	of data.
	276	udelay(10) is 1 bit time at 100khz
	277	Doubled for slop. 20 is too small.
	278	*/
	279	i=258;
	280	do {
	281	/* Get status */
	282	status = in8(IIC_STS);
	283	__asm__ volatile("eieio");
	284	udelay (10);
	285	i--;
	286	} while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR)
c609719b WD	287	&& (i>0));
c609719b WD	288
8bde7f77 WD	289	if (status & IIC_STS_ERR) {
	290	result = IIC_NOK;
	291	status = in8 (IIC_EXTSTS);
	292	/* Lost arbitration? */
	293	if (status & IIC_EXTSTS_LA)
	294	result = IIC_NOK_LA;
	295	/* Incomplete transfer? */
	296	if (status & IIC_EXTSTS_ICT)
	297	result = IIC_NOK_ICT;
	298	/* Transfer aborted? */
	299	if (status & IIC_EXTSTS_XFRA)
	300	result = IIC_NOK_XFRA;
	301	} else if ( status & IIC_STS_PT) {
	302	result = IIC_NOK_TOUT;
	303	}
	304	/* Command is reading => get buffer */
	305	if ((reading) && (result == IIC_OK)) {
	306	/* Are there data in buffer */
	307	if (status & IIC_STS_MDBS) {
	308	/*
	309	even if we have data we have to wait 4OPB clocks
	310	for it to hit the front of the FIFO, after that
	311	we can just read. We should check XFCNT here and
	312	if the FIFO is full there is no need to wait.
c609719b	313	*/
8bde7f77 WD	314	udelay (1);
	315	for(j=0;j<bc;j++) {
	316	ptr[tran+j] = in8(IIC_MDBUF);
	317	__asm__ volatile("eieio");
	318	}
	319	} else
	320	result = IIC_NOK_DATA;
	321	}
	322	creg = 0;
	323	tran+=bc;
	324	if( ptr == addr && tran == cnt ) {
	325	ptr = data;
	326	cnt = data_len;
	327	tran = 0;
	328	reading = cmd_type;
	329	if( reading )
	330	creg = IIC_CNTL_RPST;
	331	}
	332	}
	333	return (result);
c609719b WD	334	}
	335
	336	int i2c_probe (uchar chip)
	337	{
	338	uchar buf[1];
	339
	340	buf[0] = 0;
	341
8bde7f77 WD	342	/*
	343	* What is needed is to send the chip address and verify that the
	344	* address was <ACK>ed (i.e. there was a chip at that address which
	345	* drove the data line low).
	346	*/
	347	return(i2c_transfer (1, chip << 1, 0,0, buf, 1) != 0);
c609719b WD	348	}
	349
	350
c609719b WD	351	int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
c609719b WD	352	{
8bde7f77 WD	353	uchar xaddr[4];
8bde7f77 WD	354	int ret;
c609719b WD	355
	356	if ( alen > 4 ) {
	357	printf ("I2C read: addr len %d not supported\n", alen);
	358	return 1;
	359	}
	360
8bde7f77 WD	361	if ( alen > 0 ) {
	362	xaddr[0] = (addr >> 24) & 0xFF;
	363	xaddr[1] = (addr >> 16) & 0xFF;
	364	xaddr[2] = (addr >> 8) & 0xFF;
	365	xaddr[3] = addr & 0xFF;
	366	}
c609719b WD	367
	368
	369	#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
	370	/*
8bde7f77 WD	371	* EEPROM chips that implement "address overflow" are ones
	372	* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
	373	* address and the extra bits end up in the "chip address"
	374	* bit slots. This makes a 24WC08 (1Kbyte) chip look like
	375	* four 256 byte chips.
c609719b	376	*
8bde7f77 WD	377	* Note that we consider the length of the address field to
	378	* still be one byte because the extra address bits are
	379	* hidden in the chip address.
c609719b	380	*/
8bde7f77 WD	381	if( alen > 0 )
8bde7f77 WD	382	chip \|= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
c609719b	383	#endif
8bde7f77	384	if( (ret = i2c_transfer( 1, chip<<1, &xaddr[4-alen], alen, buffer, len )) != 0) {
2c96baa2 SR	385	if (gd->have_console)
2c96baa2 SR	386	printf( "I2c read: failed %d\n", ret);
8bde7f77 WD	387	return 1;
	388	}
	389	return 0;
c609719b WD	390	}
	391
	392	int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
	393	{
8bde7f77	394	uchar xaddr[4];
c609719b WD	395
	396	if ( alen > 4 ) {
	397	printf ("I2C write: addr len %d not supported\n", alen);
	398	return 1;
	399
	400	}
8bde7f77 WD	401	if ( alen > 0 ) {
	402	xaddr[0] = (addr >> 24) & 0xFF;
	403	xaddr[1] = (addr >> 16) & 0xFF;
	404	xaddr[2] = (addr >> 8) & 0xFF;
	405	xaddr[3] = addr & 0xFF;
	406	}
c609719b WD	407
	408	#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
	409	/*
8bde7f77 WD	410	* EEPROM chips that implement "address overflow" are ones
	411	* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
	412	* address and the extra bits end up in the "chip address"
	413	* bit slots. This makes a 24WC08 (1Kbyte) chip look like
	414	* four 256 byte chips.
c609719b	415	*
8bde7f77 WD	416	* Note that we consider the length of the address field to
	417	* still be one byte because the extra address bits are
	418	* hidden in the chip address.
c609719b	419	*/
8bde7f77 WD	420	if( alen > 0 )
8bde7f77 WD	421	chip \|= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
c609719b WD	422	#endif
c609719b WD	423
8bde7f77	424	return (i2c_transfer( 0, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0);
c609719b WD	425	}
c609719b WD	426
1cb8e980 WD	427	/*-----------------------------------------------------------------------
	428	* Read a register
	429	*/
	430	uchar i2c_reg_read(uchar i2c_addr, uchar reg)
	431	{
77ddac94	432	uchar buf;
1cb8e980 WD	433
	434	i2c_read(i2c_addr, reg, 1, &buf, 1);
	435
	436	return(buf);
	437	}
	438
	439	/*-----------------------------------------------------------------------
	440	* Write a register
	441	*/
	442	void i2c_reg_write(uchar i2c_addr, uchar reg, uchar val)
	443	{
	444	i2c_write(i2c_addr, reg, 1, &val, 1);
	445	}
c609719b	446	#endif /* CONFIG_HARD_I2C */