[u-boot.git] / cpu / ppc4xx / i2c.c

/*****************************************************************************/
/* I2C Bus interface initialisation and I2C Commands                         */
/* for PPC405GP		                                                     */
/* Author : AS HARNOIS                                                       */
/* Date   : 13.Dec.00                                                        */
/*****************************************************************************/

#include <common.h>
#include <ppc4xx.h>
#if defined(CONFIG_440)
#   include <440_i2c.h>
#else
#   include <405gp_i2c.h>
#endif
#include <i2c.h>

#ifdef CONFIG_HARD_I2C

#define IIC_OK		0
#define IIC_NOK		1
#define IIC_NOK_LA	2		/* Lost arbitration */
#define IIC_NOK_ICT	3		/* Incomplete transfer */
#define IIC_NOK_XFRA	4		/* Transfer aborted */
#define IIC_NOK_DATA	5		/* No data in buffer */
#define IIC_NOK_TOUT	6		/* Transfer timeout */

#define IIC_TIMEOUT 1			/* 1 seconde */


static void _i2c_bus_reset (void)
{
	int i, status;

	/* Reset status register */
	/* write 1 in SCMP and IRQA to clear these fields */
	out8 (IIC_STS, 0x0A);

	/* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */
	out8 (IIC_EXTSTS, 0x8F);
	__asm__ volatile ("eieio");

	/*
	 * Get current state, reset bus
	 * only if no transfers are pending.
	 */
	i = 10;
	do {
		/* Get status */
		status = in8 (IIC_STS);
		udelay (500);			/* 500us */
		i--;
	} while ((status & IIC_STS_PT) && (i > 0));
	/* Soft reset controller */
	status = in8 (IIC_XTCNTLSS);
	out8 (IIC_XTCNTLSS, (status | IIC_XTCNTLSS_SRST));
	__asm__ volatile ("eieio");

	/* make sure where in initial state, data hi, clock hi */
	out8 (IIC_DIRECTCNTL, 0xC);
	for (i = 0; i < 10; i++) {
		if ((in8 (IIC_DIRECTCNTL) & 0x3) != 0x3) {
			/* clock until we get to known state */
			out8 (IIC_DIRECTCNTL, 0x8);	/* clock lo */
			udelay (100);		/* 100us */
			out8 (IIC_DIRECTCNTL, 0xC);	/* clock hi */
			udelay (100);		/* 100us */
		} else {
			break;
		}
	}
	/* send start condition */
	out8 (IIC_DIRECTCNTL, 0x4);
	udelay (1000);				/* 1ms */
	/* send stop condition */
	out8 (IIC_DIRECTCNTL, 0xC);
	udelay (1000);				/* 1ms */
	/* Unreset controller */
	out8 (IIC_XTCNTLSS, (status & ~IIC_XTCNTLSS_SRST));
	udelay (1000);				/* 1ms */
}

void i2c_init (int speed, int slaveadd)
{
	sys_info_t sysInfo;
	unsigned long freqOPB;
	int val, divisor;

	/* Handle possible failed I2C state */
	_i2c_bus_reset ();

	/* clear lo master address */
	out8 (IIC_LMADR, 0);

	/* clear hi master address */
	out8 (IIC_HMADR, 0);

	/* clear lo slave address */
	out8 (IIC_LSADR, 0);

	/* clear hi slave address */
	out8 (IIC_HSADR, 0);

	/* Clock divide Register */
	/* get OPB frequency */
	get_sys_info (&sysInfo);
	freqOPB = sysInfo.freqPLB / sysInfo.pllOpbDiv;
	/* set divisor according to freqOPB */
	divisor = (freqOPB - 1) / 10000000;
	if (divisor == 0)
		divisor = 1;
	out8 (IIC_CLKDIV, divisor);

	/* no interrupts */
	out8 (IIC_INTRMSK, 0);

	/* clear transfer count */
	out8 (IIC_XFRCNT, 0);

	/* clear extended control & stat */
	/* write 1 in SRC SRS SWC SWS to clear these fields */
	out8 (IIC_XTCNTLSS, 0xF0);

	/* Mode Control Register
	   Flush Slave/Master data buffer */
	out8 (IIC_MDCNTL, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB);
	__asm__ volatile ("eieio");


        val = in8(IIC_MDCNTL);
        __asm__ volatile ("eieio");

        /* Ignore General Call, slave transfers are ignored,
           disable interrupts, exit unknown bus state, enable hold
           SCL
           100kHz normaly or FastMode for 400kHz and above
        */

        val |= IIC_MDCNTL_EUBS|IIC_MDCNTL_HSCL;
        if( speed >= 400000 ){
                val |= IIC_MDCNTL_FSM;
        }
	out8 (IIC_MDCNTL, val);

	/* clear control reg */
	out8 (IIC_CNTL, 0x00);
	__asm__ volatile ("eieio");

}

/*
  This code tries to use the features of the 405GP i2c
  controller. It will transfer up to 4 bytes in one pass
  on the loop. It only does out8(lbz) to the buffer when it
  is possible to do out16(lhz) transfers.

  cmd_type is 0 for write 1 for read.

  addr_len can take any value from 0-255, it is only limited
  by the char, we could make it larger if needed. If it is
  0 we skip the address write cycle.

  Typical case is a Write of an addr followd by a Read. The
  IBM FAQ does not cover this. On the last byte of the write
  we don't set the creg CHT bit, and on the first bytes of the
  read we set the RPST bit.

  It does not support address only transfers, there must be
  a data part. If you want to write the address yourself, put
  it in the data pointer.

  It does not support transfer to/from address 0.

  It does not check XFRCNT.
*/
static
int i2c_transfer(unsigned char cmd_type,
                 unsigned char chip,
                 unsigned char addr[],
                 unsigned char addr_len,
                 unsigned char data[],
		 unsigned short data_len )
{
        unsigned char* ptr;
        int reading;
        int tran,cnt;
        int result;
        int status;
        int i;
        uchar creg;

        if( data == 0 || data_len == 0 ){
                /*Don't support data transfer of no length or to address 0*/
                printf( "i2c_transfer: bad call\n" );
                return IIC_NOK;
        }
        if( addr && addr_len ){
                ptr = addr;
                cnt = addr_len;
                reading = 0;
        }else{
                ptr = data;
                cnt = data_len;
                reading = cmd_type;
        }

        /*Clear Stop Complete Bit*/
        out8(IIC_STS,IIC_STS_SCMP);
        /* Check init */
        i=10;
        do {
                /* Get status */
                status = in8(IIC_STS);
                __asm__ volatile("eieio");
                i--;
        } while ((status & IIC_STS_PT) && (i>0));

        if (status & IIC_STS_PT) {
                result = IIC_NOK_TOUT;
                return(result);
        }
        /*flush the Master/Slave Databuffers*/
        out8(IIC_MDCNTL, ((in8(IIC_MDCNTL))|IIC_MDCNTL_FMDB|IIC_MDCNTL_FSDB));
        /*need to wait 4 OPB clocks? code below should take that long*/

        /* 7-bit adressing */
        out8(IIC_HMADR,0);
        out8(IIC_LMADR, chip);
        __asm__ volatile("eieio");

        tran = 0;
        result = IIC_OK;
        creg = 0;

        while ( tran != cnt && (result == IIC_OK)) {
                int  bc,j;

                /* Control register =
                   Normal transfer, 7-bits adressing, Transfer up to bc bytes, Normal start,
                   Transfer is a sequence of transfers
                */
                creg |= IIC_CNTL_PT;

                bc = (cnt - tran) > 4 ? 4 :
                        cnt - tran;
                creg |= (bc-1)<<4;
                /* if the real cmd type is write continue trans*/
                if ( (!cmd_type && (ptr == addr)) || ((tran+bc) != cnt) )
                        creg |= IIC_CNTL_CHT;

                if (reading)
                        creg |= IIC_CNTL_READ;
                else {
                        for(j=0; j<bc; j++) {
                                /* Set buffer */
                                out8(IIC_MDBUF,ptr[tran+j]);
                                __asm__ volatile("eieio");
                        }
                }
                out8(IIC_CNTL, creg );
                __asm__ volatile("eieio");

                /* Transfer is in progress
                   we have to wait for upto 5 bytes of data
                   1 byte chip address+r/w bit then bc bytes
                   of data.
                   udelay(10) is 1 bit time at 100khz
                   Doubled for slop. 20 is too small.
		*/
                i=2*5*8;
                do {
                        /* Get status */
                        status = in8(IIC_STS);
                        __asm__ volatile("eieio");
                        udelay (10);
                        i--;
                } while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR)
			 && (i>0));

                if (status & IIC_STS_ERR) {
                        result = IIC_NOK;
                        status = in8 (IIC_EXTSTS);
                        /* Lost arbitration? */
                        if (status & IIC_EXTSTS_LA)
                                result = IIC_NOK_LA;
                        /* Incomplete transfer? */
                        if (status & IIC_EXTSTS_ICT)
                                result = IIC_NOK_ICT;
                        /* Transfer aborted? */
                        if (status & IIC_EXTSTS_XFRA)
                                result = IIC_NOK_XFRA;
                } else if ( status & IIC_STS_PT) {
                        result = IIC_NOK_TOUT;
                }
                /* Command is reading => get buffer */
                if ((reading) && (result == IIC_OK)) {
                        /* Are there data in buffer */
                        if (status & IIC_STS_MDBS) {
                                /*
                                  even if we have data we have to wait 4OPB clocks
                                  for it to hit the front of the FIFO, after that
                                  we can just read. We should check XFCNT here and
                                  if the FIFO is full there is no need to wait.
				*/
                                udelay (1);
                                for(j=0;j<bc;j++) {
                                        ptr[tran+j] = in8(IIC_MDBUF);
                                        __asm__ volatile("eieio");
                                }
                        } else
                                result = IIC_NOK_DATA;
                }
                creg = 0;
                tran+=bc;
                if( ptr == addr && tran == cnt ) {
                        ptr = data;
                        cnt = data_len;
                        tran = 0;
                        reading = cmd_type;
                        if( reading )
                                creg = IIC_CNTL_RPST;
                }
        }
        return (result);
}

int i2c_probe (uchar chip)
{
	uchar buf[1];

	buf[0] = 0;

        /*
         * What is needed is to send the chip address and verify that the
         * address was <ACK>ed (i.e. there was a chip at that address which
         * drove the data line low).
         */
        return(i2c_transfer (1, chip << 1, 0,0, buf, 1) != 0);
}


int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
{
        uchar xaddr[4];
        int ret;

	if ( alen > 4 ) {
		printf ("I2C read: addr len %d not supported\n", alen);
		return 1;
	}

        if ( alen > 0 ) {
                xaddr[0] = (addr >> 24) & 0xFF;
                xaddr[1] = (addr >> 16) & 0xFF;
                xaddr[2] = (addr >> 8) & 0xFF;
                xaddr[3] = addr & 0xFF;
        }


#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
	/*
         * EEPROM chips that implement "address overflow" are ones
         * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
         * address and the extra bits end up in the "chip address"
         * bit slots. This makes a 24WC08 (1Kbyte) chip look like
         * four 256 byte chips.
	 *
         * Note that we consider the length of the address field to
         * still be one byte because the extra address bits are
         * hidden in the chip address.
	 */
        if( alen > 0 )
                chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
#endif
        if( (ret = i2c_transfer( 1, chip<<1, &xaddr[4-alen], alen, buffer, len )) != 0) {
                printf( "I2c read: failed %d\n", ret);
                return 1;
        }
        return 0;
}

int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
{
        uchar xaddr[4];

	if ( alen > 4 ) {
		printf ("I2C write: addr len %d not supported\n", alen);
		return 1;

	}
        if ( alen > 0 ) {
                xaddr[0] = (addr >> 24) & 0xFF;
                xaddr[1] = (addr >> 16) & 0xFF;
                xaddr[2] = (addr >> 8) & 0xFF;
                xaddr[3] = addr & 0xFF;
        }

#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
	/*
         * EEPROM chips that implement "address overflow" are ones
         * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
         * address and the extra bits end up in the "chip address"
         * bit slots. This makes a 24WC08 (1Kbyte) chip look like
         * four 256 byte chips.
	 *
         * Note that we consider the length of the address field to
         * still be one byte because the extra address bits are
         * hidden in the chip address.
	 */
        if( alen > 0 )
                chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
#endif

        return (i2c_transfer( 0, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0);
}

#endif	/* CONFIG_HARD_I2C */
Commit	Line	Data
c609719b WD	1	/*****************************************************************************/
	2	/* I2C Bus interface initialisation and I2C Commands */
	3	/* for PPC405GP */
	4	/* Author : AS HARNOIS */
	5	/* Date : 13.Dec.00 */
	6	/*****************************************************************************/
	7
	8	#include <common.h>
	9	#include <ppc4xx.h>
	10	#if defined(CONFIG_440)
	11	# include <440_i2c.h>
	12	#else
	13	# include <405gp_i2c.h>
	14	#endif
	15	#include <i2c.h>
	16
	17	#ifdef CONFIG_HARD_I2C
	18
	19	#define IIC_OK 0
	20	#define IIC_NOK 1
	21	#define IIC_NOK_LA 2 /* Lost arbitration */
	22	#define IIC_NOK_ICT 3 /* Incomplete transfer */
	23	#define IIC_NOK_XFRA 4 /* Transfer aborted */
	24	#define IIC_NOK_DATA 5 /* No data in buffer */
	25	#define IIC_NOK_TOUT 6 /* Transfer timeout */
	26
	27	#define IIC_TIMEOUT 1 /* 1 seconde */
	28
	29
	30	static void _i2c_bus_reset (void)
	31	{
	32	int i, status;
	33
	34	/* Reset status register */
	35	/* write 1 in SCMP and IRQA to clear these fields */
	36	out8 (IIC_STS, 0x0A);
	37
	38	/* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */
	39	out8 (IIC_EXTSTS, 0x8F);
	40	__asm__ volatile ("eieio");
	41
	42	/*
	43	* Get current state, reset bus
	44	* only if no transfers are pending.
	45	*/
	46	i = 10;
	47	do {
	48	/* Get status */
	49	status = in8 (IIC_STS);
	50	udelay (500); /* 500us */
	51	i--;
	52	} while ((status & IIC_STS_PT) && (i > 0));
	53	/* Soft reset controller */
	54	status = in8 (IIC_XTCNTLSS);
	55	out8 (IIC_XTCNTLSS, (status \| IIC_XTCNTLSS_SRST));
	56	__asm__ volatile ("eieio");
	57
	58	/* make sure where in initial state, data hi, clock hi */
	59	out8 (IIC_DIRECTCNTL, 0xC);
	60	for (i = 0; i < 10; i++) {
	61	if ((in8 (IIC_DIRECTCNTL) & 0x3) != 0x3) {
	62	/* clock until we get to known state */
	63	out8 (IIC_DIRECTCNTL, 0x8); /* clock lo */
	64	udelay (100); /* 100us */
65	out8 (IIC_DIRECTCNTL, 0xC); /* clock hi */
66	udelay (100); /* 100us */
67	} else {
68	break;
69	}
70	}
71	/* send start condition */
72	out8 (IIC_DIRECTCNTL, 0x4);
73	udelay (1000); /* 1ms */
74	/* send stop condition */
75	out8 (IIC_DIRECTCNTL, 0xC);
76	udelay (1000); /* 1ms */
77	/* Unreset controller */
78	out8 (IIC_XTCNTLSS, (status & ~IIC_XTCNTLSS_SRST));
79	udelay (1000); /* 1ms */
80	}
81
82	void i2c_init (int speed, int slaveadd)
83	{
84	sys_info_t sysInfo;
85	unsigned long freqOPB;
86	int val, divisor;
87
88	/* Handle possible failed I2C state */
89	_i2c_bus_reset ();
90
91	/* clear lo master address */
92	out8 (IIC_LMADR, 0);
93
94	/* clear hi master address */
95	out8 (IIC_HMADR, 0);
96
97	/* clear lo slave address */
98	out8 (IIC_LSADR, 0);
99
100	/* clear hi slave address */
101	out8 (IIC_HSADR, 0);
102
103	/* Clock divide Register */
104	/* get OPB frequency */
105	get_sys_info (&sysInfo);
106	freqOPB = sysInfo.freqPLB / sysInfo.pllOpbDiv;
107	/* set divisor according to freqOPB */
108	divisor = (freqOPB - 1) / 10000000;
109	if (divisor == 0)
110	divisor = 1;
111	out8 (IIC_CLKDIV, divisor);
112
113	/* no interrupts */
114	out8 (IIC_INTRMSK, 0);
115
116	/* clear transfer count */
117	out8 (IIC_XFRCNT, 0);
118
119	/* clear extended control & stat */
120	/* write 1 in SRC SRS SWC SWS to clear these fields */
121	out8 (IIC_XTCNTLSS, 0xF0);
122
123	/* Mode Control Register
124	Flush Slave/Master data buffer */
125	out8 (IIC_MDCNTL, IIC_MDCNTL_FSDB \| IIC_MDCNTL_FMDB);
126	__asm__ volatile ("eieio");
127
128
129	val = in8(IIC_MDCNTL);
130	__asm__ volatile ("eieio");
131
132	/* Ignore General Call, slave transfers are ignored,
133	disable interrupts, exit unknown bus state, enable hold
134	SCL
135	100kHz normaly or FastMode for 400kHz and above
136	*/
137
138	val \|= IIC_MDCNTL_EUBS\|IIC_MDCNTL_HSCL;
139	if( speed >= 400000 ){
140	val \|= IIC_MDCNTL_FSM;
141	}
142	out8 (IIC_MDCNTL, val);
143
144	/* clear control reg */
145	out8 (IIC_CNTL, 0x00);
146	__asm__ volatile ("eieio");
147
148	}
149
150	/*
151	This code tries to use the features of the 405GP i2c
152	controller. It will transfer up to 4 bytes in one pass
153	on the loop. It only does out8(lbz) to the buffer when it
154	is possible to do out16(lhz) transfers.
155
156	cmd_type is 0 for write 1 for read.
157
158	addr_len can take any value from 0-255, it is only limited
159	by the char, we could make it larger if needed. If it is
160	0 we skip the address write cycle.
161
162	Typical case is a Write of an addr followd by a Read. The
163	IBM FAQ does not cover this. On the last byte of the write
164	we don't set the creg CHT bit, and on the first bytes of the
165	read we set the RPST bit.
166
167	It does not support address only transfers, there must be
168	a data part. If you want to write the address yourself, put
169	it in the data pointer.
170
171	It does not support transfer to/from address 0.
172
173	It does not check XFRCNT.
174	*/
175	static
176	int i2c_transfer(unsigned char cmd_type,
177	unsigned char chip,
178	unsigned char addr[],
179	unsigned char addr_len,
180	unsigned char data[],
181	unsigned short data_len )
182	{
183	unsigned char* ptr;
184	int reading;
185	int tran,cnt;
186	int result;
187	int status;
188	int i;
189	uchar creg;
190
191	if( data == 0 \|\| data_len == 0 ){
192	/Don't support data transfer of no length or to address 0/
193	printf( "i2c_transfer: bad call\n" );
194	return IIC_NOK;
195	}
196	if( addr && addr_len ){
197	ptr = addr;
198	cnt = addr_len;
199	reading = 0;
200	}else{
201	ptr = data;
202	cnt = data_len;
203	reading = cmd_type;
204	}
205
206	/Clear Stop Complete Bit/
207	out8(IIC_STS,IIC_STS_SCMP);
208	/* Check init */
209	i=10;
210	do {
211	/* Get status */
212	status = in8(IIC_STS);
213	__asm__ volatile("eieio");
214	i--;
215	} while ((status & IIC_STS_PT) && (i>0));
216
217	if (status & IIC_STS_PT) {
218	result = IIC_NOK_TOUT;
219	return(result);
220	}
221	/flush the Master/Slave Databuffers/
222	out8(IIC_MDCNTL, ((in8(IIC_MDCNTL))\|IIC_MDCNTL_FMDB\|IIC_MDCNTL_FSDB));
223	/need to wait 4 OPB clocks? code below should take that long/
224
225	/* 7-bit adressing */
226	out8(IIC_HMADR,0);
227	out8(IIC_LMADR, chip);
228	__asm__ volatile("eieio");
229
230	tran = 0;
231	result = IIC_OK;
232	creg = 0;
233
234	while ( tran != cnt && (result == IIC_OK)) {
235	int bc,j;
236
237	/* Control register =
238	Normal transfer, 7-bits adressing, Transfer up to bc bytes, Normal start,
239	Transfer is a sequence of transfers
240	*/
241	creg \|= IIC_CNTL_PT;
242
243	bc = (cnt - tran) > 4 ? 4 :
244	cnt - tran;
245	creg \|= (bc-1)<<4;
246	/* if the real cmd type is write continue trans*/
247	if ( (!cmd_type && (ptr == addr)) \|\| ((tran+bc) != cnt) )
248	creg \|= IIC_CNTL_CHT;
249
250	if (reading)
251	creg \|= IIC_CNTL_READ;
252	else {
253	for(j=0; j<bc; j++) {
254	/* Set buffer */
255	out8(IIC_MDBUF,ptr[tran+j]);
256	__asm__ volatile("eieio");
257	}
258	}
259	out8(IIC_CNTL, creg );
260	__asm__ volatile("eieio");
261
262	/* Transfer is in progress
263	we have to wait for upto 5 bytes of data
264	1 byte chip address+r/w bit then bc bytes
265	of data.
266	udelay(10) is 1 bit time at 100khz
267	Doubled for slop. 20 is too small.
268	*/
269	i=258;
270	do {
271	/* Get status */
272	status = in8(IIC_STS);
273	__asm__ volatile("eieio");
274	udelay (10);
275	i--;
276	} while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR)
277	&& (i>0));
278
279	if (status & IIC_STS_ERR) {
280	result = IIC_NOK;
281	status = in8 (IIC_EXTSTS);
282	/* Lost arbitration? */
283	if (status & IIC_EXTSTS_LA)
284	result = IIC_NOK_LA;
285	/* Incomplete transfer? */
286	if (status & IIC_EXTSTS_ICT)
287	result = IIC_NOK_ICT;
288	/* Transfer aborted? */
289	if (status & IIC_EXTSTS_XFRA)
290	result = IIC_NOK_XFRA;
291	} else if ( status & IIC_STS_PT) {
292	result = IIC_NOK_TOUT;
293	}
294	/* Command is reading => get buffer */
295	if ((reading) && (result == IIC_OK)) {
296	/* Are there data in buffer */
297	if (status & IIC_STS_MDBS) {
298	/*
299	even if we have data we have to wait 4OPB clocks
300	for it to hit the front of the FIFO, after that
301	we can just read. We should check XFCNT here and
302	if the FIFO is full there is no need to wait.
303	*/
304	udelay (1);
305	for(j=0;j<bc;j++) {
306	ptr[tran+j] = in8(IIC_MDBUF);
307	__asm__ volatile("eieio");
308	}
309	} else
310	result = IIC_NOK_DATA;
311	}
312	creg = 0;
313	tran+=bc;
314	if( ptr == addr && tran == cnt ) {
315	ptr = data;
316	cnt = data_len;
317	tran = 0;
318	reading = cmd_type;
319	if( reading )
320	creg = IIC_CNTL_RPST;
321	}
322	}
323	return (result);
324	}
325
326	int i2c_probe (uchar chip)
327	{
328	uchar buf[1];
329
330	buf[0] = 0;
331
332	/*
333	* What is needed is to send the chip address and verify that the
334	* address was <ACK>ed (i.e. there was a chip at that address which
335	* drove the data line low).
336	*/
337	return(i2c_transfer (1, chip << 1, 0,0, buf, 1) != 0);
338	}
339
340
341
342	int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
343	{
344	uchar xaddr[4];
345	int ret;
346
347	if ( alen > 4 ) {
348	printf ("I2C read: addr len %d not supported\n", alen);
349	return 1;
350	}
351
352	if ( alen > 0 ) {
353	xaddr[0] = (addr >> 24) & 0xFF;
354	xaddr[1] = (addr >> 16) & 0xFF;
355	xaddr[2] = (addr >> 8) & 0xFF;
356	xaddr[3] = addr & 0xFF;
357	}
358
359
360	#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
361	/*
362	* EEPROM chips that implement "address overflow" are ones
363	* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
364	* address and the extra bits end up in the "chip address"
365	* bit slots. This makes a 24WC08 (1Kbyte) chip look like
366	* four 256 byte chips.
367	*
368	* Note that we consider the length of the address field to
369	* still be one byte because the extra address bits are
370	* hidden in the chip address.
371	*/
372	if( alen > 0 )
373	chip \|= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
374	#endif
375	if( (ret = i2c_transfer( 1, chip<<1, &xaddr[4-alen], alen, buffer, len )) != 0) {
376	printf( "I2c read: failed %d\n", ret);
377	return 1;
378	}
379	return 0;
380	}
381
382	int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
383	{
384	uchar xaddr[4];
385
386	if ( alen > 4 ) {
387	printf ("I2C write: addr len %d not supported\n", alen);
388	return 1;
389
390	}
391	if ( alen > 0 ) {
392	xaddr[0] = (addr >> 24) & 0xFF;
393	xaddr[1] = (addr >> 16) & 0xFF;
394	xaddr[2] = (addr >> 8) & 0xFF;
395	xaddr[3] = addr & 0xFF;
396	}
397
398	#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
399	/*
400	* EEPROM chips that implement "address overflow" are ones
401	* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
402	* address and the extra bits end up in the "chip address"
403	* bit slots. This makes a 24WC08 (1Kbyte) chip look like
404	* four 256 byte chips.
405	*
406	* Note that we consider the length of the address field to
407	* still be one byte because the extra address bits are
408	* hidden in the chip address.
409	*/
410	if( alen > 0 )
411	chip \|= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
412	#endif
413
414	return (i2c_transfer( 0, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0);
415	}
416
417	#endif /* CONFIG_HARD_I2C */