[u-boot.git] / drivers / usb / host / xhci-dwc3.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2015 Freescale Semiconductor, Inc.
 *
 * DWC3 controller driver
 *
 * Author: Ramneek Mehresh<[email protected]>
 */

#include <clk.h>
#include <common.h>
#include <dm.h>
#include <generic-phy.h>
#include <log.h>
#include <reset.h>
#include <usb.h>
#include <dwc3-uboot.h>
#include <linux/delay.h>

#include <usb/xhci.h>
#include <asm/io.h>
#include <linux/usb/dwc3.h>
#include <linux/usb/otg.h>

struct xhci_dwc3_plat {
	struct clk_bulk clks;
	struct phy_bulk phys;
	struct reset_ctl_bulk resets;
};

void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
{
	clrsetbits_le32(&dwc3_reg->g_ctl,
			DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
			DWC3_GCTL_PRTCAPDIR(mode));
}

static void dwc3_phy_reset(struct dwc3 *dwc3_reg)
{
	/* Assert USB3 PHY reset */
	setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);

	/* Assert USB2 PHY reset */
	setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);

	mdelay(100);

	/* Clear USB3 PHY reset */
	clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);

	/* Clear USB2 PHY reset */
	clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
}

void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
{
	/* Before Resetting PHY, put Core in Reset */
	setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);

	/* reset USB3 phy - if required */
	dwc3_phy_reset(dwc3_reg);

	mdelay(100);

	/* After PHYs are stable we can take Core out of reset state */
	clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
}

int dwc3_core_init(struct dwc3 *dwc3_reg)
{
	u32 reg;
	u32 revision;
	unsigned int dwc3_hwparams1;

	revision = readl(&dwc3_reg->g_snpsid);
	/* This should read as U3 followed by revision number */
	if ((revision & DWC3_GSNPSID_MASK) != 0x55330000 &&
	    (revision & DWC3_GSNPSID_MASK) != 0x33310000) {
		puts("this is not a DesignWare USB3 DRD Core\n");
		return -1;
	}

	dwc3_core_soft_reset(dwc3_reg);

	dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1);

	reg = readl(&dwc3_reg->g_ctl);
	reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
	reg &= ~DWC3_GCTL_DISSCRAMBLE;
	switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
	case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
		reg &= ~DWC3_GCTL_DSBLCLKGTNG;
		break;
	default:
		debug("No power optimization available\n");
	}

	/*
	 * WORKAROUND: DWC3 revisions <1.90a have a bug
	 * where the device can fail to connect at SuperSpeed
	 * and falls back to high-speed mode which causes
	 * the device to enter a Connect/Disconnect loop
	 */
	if ((revision & DWC3_REVISION_MASK) < 0x190a)
		reg |= DWC3_GCTL_U2RSTECN;

	writel(reg, &dwc3_reg->g_ctl);

	return 0;
}

void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val)
{
	setbits_le32(&dwc3_reg->g_fladj, GFLADJ_30MHZ_REG_SEL |
			GFLADJ_30MHZ(val));
}

#if CONFIG_IS_ENABLED(DM_USB)
static int xhci_dwc3_reset_init(struct udevice *dev,
				struct xhci_dwc3_plat *plat)
{
	int ret;

	ret = reset_get_bulk(dev, &plat->resets);
	if (ret == -ENOTSUPP || ret == -ENOENT)
		return 0;
	else if (ret)
		return ret;

	ret = reset_deassert_bulk(&plat->resets);
	if (ret) {
		reset_release_bulk(&plat->resets);
		return ret;
	}

	return 0;
}

static int xhci_dwc3_clk_init(struct udevice *dev,
			      struct xhci_dwc3_plat *plat)
{
	int ret;

	ret = clk_get_bulk(dev, &plat->clks);
	if (ret == -ENOSYS || ret == -ENOENT)
		return 0;
	if (ret)
		return ret;

	ret = clk_enable_bulk(&plat->clks);
	if (ret) {
		clk_release_bulk(&plat->clks);
		return ret;
	}

	return 0;
}

static int xhci_dwc3_probe(struct udevice *dev)
{
	struct xhci_hcor *hcor;
	struct xhci_hccr *hccr;
	struct dwc3 *dwc3_reg;
	enum usb_dr_mode dr_mode;
	struct xhci_dwc3_plat *plat = dev_get_plat(dev);
	const char *phy;
	u32 reg;
	int ret;

	ret = xhci_dwc3_reset_init(dev, plat);
	if (ret)
		return ret;

	ret = xhci_dwc3_clk_init(dev, plat);
	if (ret)
		return ret;

	hccr = (struct xhci_hccr *)((uintptr_t)dev_remap_addr(dev));
	hcor = (struct xhci_hcor *)((uintptr_t)hccr +
			HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));

	ret = dwc3_setup_phy(dev, &plat->phys);
	if (ret && (ret != -ENOTSUPP))
		return ret;

	dwc3_reg = (struct dwc3 *)((char *)(hccr) + DWC3_REG_OFFSET);

	dwc3_core_init(dwc3_reg);

	/* Set dwc3 usb2 phy config */
	reg = readl(&dwc3_reg->g_usb2phycfg[0]);

	phy = dev_read_string(dev, "phy_type");
	if (phy && strcmp(phy, "utmi_wide") == 0) {
		reg |= DWC3_GUSB2PHYCFG_PHYIF;
		reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
		reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT;
	}

	if (dev_read_bool(dev, "snps,dis_enblslpm_quirk"))
		reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;

	if (dev_read_bool(dev, "snps,dis-u2-freeclk-exists-quirk"))
		reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;

	if (dev_read_bool(dev, "snps,dis_u2_susphy_quirk"))
		reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;

	writel(reg, &dwc3_reg->g_usb2phycfg[0]);

	dr_mode = usb_get_dr_mode(dev_ofnode(dev));
	if (dr_mode == USB_DR_MODE_OTG &&
	    dev_read_bool(dev, "usb-role-switch")) {
		dr_mode = usb_get_role_switch_default_mode(dev_ofnode(dev));
		if (dr_mode == USB_DR_MODE_UNKNOWN)
			dr_mode = USB_DR_MODE_OTG;
	}
	if (dr_mode == USB_DR_MODE_UNKNOWN)
		/* by default set dual role mode to HOST */
		dr_mode = USB_DR_MODE_HOST;

	dwc3_set_mode(dwc3_reg, dr_mode);

	return xhci_register(dev, hccr, hcor);
}

static int xhci_dwc3_remove(struct udevice *dev)
{
	struct xhci_dwc3_plat *plat = dev_get_plat(dev);

	dwc3_shutdown_phy(dev, &plat->phys);

	clk_release_bulk(&plat->clks);

	reset_release_bulk(&plat->resets);

	return xhci_deregister(dev);
}

static const struct udevice_id xhci_dwc3_ids[] = {
	{ .compatible = "snps,dwc3" },
	{ }
};

U_BOOT_DRIVER(xhci_dwc3) = {
	.name = "xhci-dwc3",
	.id = UCLASS_USB,
	.of_match = xhci_dwc3_ids,
	.probe = xhci_dwc3_probe,
	.remove = xhci_dwc3_remove,
	.ops = &xhci_usb_ops,
	.priv_auto	= sizeof(struct xhci_ctrl),
	.plat_auto	= sizeof(struct xhci_dwc3_plat),
	.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
dc9cdf85 RM	2	/*
	3	* Copyright 2015 Freescale Semiconductor, Inc.
	4	*
	5	* DWC3 controller driver
	6	*
	7	* Author: Ramneek Mehresh<[email protected]>
dc9cdf85 RM	8	*/
dc9cdf85 RM	9
91ce84a5	10	#include <clk.h>
d678a59d	11	#include <common.h>
b7c1c7d2	12	#include <dm.h>
f56db163	13	#include <generic-phy.h>
f7ae49fc	14	#include <log.h>
91ce84a5	15	#include <reset.h>
b7c1c7d2	16	#include <usb.h>
d648a50c	17	#include <dwc3-uboot.h>
c05ed00a	18	#include <linux/delay.h>
b7c1c7d2	19
1708a123	20	#include <usb/xhci.h>
dc9cdf85 RM	21	#include <asm/io.h>
dc9cdf85 RM	22	#include <linux/usb/dwc3.h>
576e3cc7	23	#include <linux/usb/otg.h>
dc9cdf85	24
8a8d24bd	25	struct xhci_dwc3_plat {
91ce84a5	26	struct clk_bulk clks;
58221d7e	27	struct phy_bulk phys;
91ce84a5	28	struct reset_ctl_bulk resets;
f56db163 PC	29	};
f56db163 PC	30
dc9cdf85 RM	31	void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
	32	{
	33	clrsetbits_le32(&dwc3_reg->g_ctl,
	34	DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
	35	DWC3_GCTL_PRTCAPDIR(mode));
	36	}
	37
121a4d13	38	static void dwc3_phy_reset(struct dwc3 *dwc3_reg)
dc9cdf85 RM	39	{
	40	/* Assert USB3 PHY reset */
	41	setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
	42
	43	/* Assert USB2 PHY reset */
	44	setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
	45
	46	mdelay(100);
	47
	48	/* Clear USB3 PHY reset */
	49	clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
	50
	51	/* Clear USB2 PHY reset */
	52	clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
	53	}
	54
	55	void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
	56	{
	57	/* Before Resetting PHY, put Core in Reset */
	58	setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
	59
	60	/* reset USB3 phy - if required */
	61	dwc3_phy_reset(dwc3_reg);
	62
5955bb93 RB	63	mdelay(100);
5955bb93 RB	64
dc9cdf85 RM	65	/* After PHYs are stable we can take Core out of reset state */
	66	clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
	67	}
	68
	69	int dwc3_core_init(struct dwc3 *dwc3_reg)
	70	{
	71	u32 reg;
	72	u32 revision;
	73	unsigned int dwc3_hwparams1;
	74
	75	revision = readl(&dwc3_reg->g_snpsid);
	76	/* This should read as U3 followed by revision number */
53eed9ad MK	77	if ((revision & DWC3_GSNPSID_MASK) != 0x55330000 &&
53eed9ad MK	78	(revision & DWC3_GSNPSID_MASK) != 0x33310000) {
dc9cdf85 RM	79	puts("this is not a DesignWare USB3 DRD Core\n");
	80	return -1;
	81	}
	82
	83	dwc3_core_soft_reset(dwc3_reg);
	84
	85	dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1);
	86
	87	reg = readl(&dwc3_reg->g_ctl);
	88	reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
	89	reg &= ~DWC3_GCTL_DISSCRAMBLE;
	90	switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
	91	case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
	92	reg &= ~DWC3_GCTL_DSBLCLKGTNG;
	93	break;
	94	default:
	95	debug("No power optimization available\n");
	96	}
	97
	98	/*
	99	* WORKAROUND: DWC3 revisions <1.90a have a bug
	100	* where the device can fail to connect at SuperSpeed
	101	* and falls back to high-speed mode which causes
	102	* the device to enter a Connect/Disconnect loop
	103	*/
	104	if ((revision & DWC3_REVISION_MASK) < 0x190a)
	105	reg \|= DWC3_GCTL_U2RSTECN;
	106
	107	writel(reg, &dwc3_reg->g_ctl);
	108
	109	return 0;
	110	}
667f4dd9 NB	111
	112	void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val)
	113	{
	114	setbits_le32(&dwc3_reg->g_fladj, GFLADJ_30MHZ_REG_SEL \|
	115	GFLADJ_30MHZ(val));
	116	}
b7c1c7d2	117
fd09c205	118	#if CONFIG_IS_ENABLED(DM_USB)
91ce84a5 SH	119	static int xhci_dwc3_reset_init(struct udevice *dev,
	120	struct xhci_dwc3_plat *plat)
	121	{
	122	int ret;
	123
	124	ret = reset_get_bulk(dev, &plat->resets);
	125	if (ret == -ENOTSUPP \|\| ret == -ENOENT)
	126	return 0;
	127	else if (ret)
	128	return ret;
	129
	130	ret = reset_deassert_bulk(&plat->resets);
	131	if (ret) {
	132	reset_release_bulk(&plat->resets);
	133	return ret;
	134	}
	135
	136	return 0;
	137	}
	138
	139	static int xhci_dwc3_clk_init(struct udevice *dev,
	140	struct xhci_dwc3_plat *plat)
	141	{
	142	int ret;
	143
	144	ret = clk_get_bulk(dev, &plat->clks);
	145	if (ret == -ENOSYS \|\| ret == -ENOENT)
	146	return 0;
	147	if (ret)
	148	return ret;
	149
	150	ret = clk_enable_bulk(&plat->clks);
	151	if (ret) {
	152	clk_release_bulk(&plat->clks);
	153	return ret;
	154	}
	155
	156	return 0;
	157	}
	158
3fc2635d V	159	static int xhci_dwc3_probe(struct udevice *dev)
3fc2635d V	160	{
3fc2635d V	161	struct xhci_hcor *hcor;
	162	struct xhci_hccr *hccr;
	163	struct dwc3 *dwc3_reg;
	164	enum usb_dr_mode dr_mode;
8a8d24bd	165	struct xhci_dwc3_plat *plat = dev_get_plat(dev);
062790f4 MK	166	const char *phy;
062790f4 MK	167	u32 reg;
3fc2635d V	168	int ret;
3fc2635d V	169
91ce84a5 SH	170	ret = xhci_dwc3_reset_init(dev, plat);
	171	if (ret)
	172	return ret;
	173
	174	ret = xhci_dwc3_clk_init(dev, plat);
	175	if (ret)
	176	return ret;
	177
72a53ac5	178	hccr = (struct xhci_hccr *)((uintptr_t)dev_remap_addr(dev));
3fc2635d V	179	hcor = (struct xhci_hcor *)((uintptr_t)hccr +
	180	HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
	181
58221d7e	182	ret = dwc3_setup_phy(dev, &plat->phys);
d648a50c	183	if (ret && (ret != -ENOTSUPP))
3fc2635d	184	return ret;
2fd4242c	185
b7c1c7d2 PC	186	dwc3_reg = (struct dwc3 )((char )(hccr) + DWC3_REG_OFFSET);
	187
	188	dwc3_core_init(dwc3_reg);
	189
062790f4 MK	190	/* Set dwc3 usb2 phy config */
	191	reg = readl(&dwc3_reg->g_usb2phycfg[0]);
	192
	193	phy = dev_read_string(dev, "phy_type");
	194	if (phy && strcmp(phy, "utmi_wide") == 0) {
	195	reg \|= DWC3_GUSB2PHYCFG_PHYIF;
	196	reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
	197	reg \|= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT;
	198	}
	199
52378ba4	200	if (dev_read_bool(dev, "snps,dis_enblslpm_quirk"))
062790f4 MK	201	reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
	202
	203	if (dev_read_bool(dev, "snps,dis-u2-freeclk-exists-quirk"))
	204	reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
	205
b35b8076 NA	206	if (dev_read_bool(dev, "snps,dis_u2_susphy_quirk"))
	207	reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
	208
062790f4 MK	209	writel(reg, &dwc3_reg->g_usb2phycfg[0]);
062790f4 MK	210
f10643cf	211	dr_mode = usb_get_dr_mode(dev_ofnode(dev));
6a6468f4 MK	212	if (dr_mode == USB_DR_MODE_OTG &&
	213	dev_read_bool(dev, "usb-role-switch")) {
	214	dr_mode = usb_get_role_switch_default_mode(dev_ofnode(dev));
	215	if (dr_mode == USB_DR_MODE_UNKNOWN)
	216	dr_mode = USB_DR_MODE_OTG;
	217	}
576e3cc7 PC	218	if (dr_mode == USB_DR_MODE_UNKNOWN)
	219	/* by default set dual role mode to HOST */
	220	dr_mode = USB_DR_MODE_HOST;
	221
	222	dwc3_set_mode(dwc3_reg, dr_mode);
	223
b7c1c7d2 PC	224	return xhci_register(dev, hccr, hcor);
	225	}
	226
	227	static int xhci_dwc3_remove(struct udevice *dev)
	228	{
8a8d24bd	229	struct xhci_dwc3_plat *plat = dev_get_plat(dev);
d648a50c	230
58221d7e	231	dwc3_shutdown_phy(dev, &plat->phys);
f56db163	232
91ce84a5 SH	233	clk_release_bulk(&plat->clks);
	234
	235	reset_release_bulk(&plat->resets);
	236
b7c1c7d2 PC	237	return xhci_deregister(dev);
	238	}
	239
	240	static const struct udevice_id xhci_dwc3_ids[] = {
	241	{ .compatible = "snps,dwc3" },
	242	{ }
	243	};
	244
	245	U_BOOT_DRIVER(xhci_dwc3) = {
	246	.name = "xhci-dwc3",
	247	.id = UCLASS_USB,
	248	.of_match = xhci_dwc3_ids,
	249	.probe = xhci_dwc3_probe,
	250	.remove = xhci_dwc3_remove,
	251	.ops = &xhci_usb_ops,
41575d8e	252	.priv_auto = sizeof(struct xhci_ctrl),
8a8d24bd	253	.plat_auto = sizeof(struct xhci_dwc3_plat),
b7c1c7d2 PC	254	.flags = DM_FLAG_ALLOC_PRIV_DMA,
b7c1c7d2 PC	255	};
623b7aca	256	#endif