[u-boot.git] / cmd / tsi148.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2009 Reinhard Arlt, [email protected]
 *
 * base on universe.h by
 *
 * (C) Copyright 2003 Stefan Roese, [email protected]
 */

#include <common.h>
#include <command.h>
#include <log.h>
#include <malloc.h>
#include <asm/io.h>
#include <pci.h>

#include <tsi148.h>

#define LPCI_VENDOR PCI_VENDOR_ID_TUNDRA
#define LPCI_DEVICE PCI_DEVICE_ID_TUNDRA_TSI148

typedef struct _TSI148_DEV TSI148_DEV;

struct _TSI148_DEV {
	int           bus;
	pci_dev_t     busdevfn;
	TSI148       *uregs;
	unsigned int  pci_bs;
};

static TSI148_DEV *dev;

/*
 * Most of the TSI148 register are BIGENDIAN
 * This is the reason for the __raw_writel(htonl(x), x) usage!
 */

int tsi148_init(void)
{
	int j, result;
	pci_dev_t busdevfn;
	unsigned int val;

	busdevfn = pci_find_device(LPCI_VENDOR, LPCI_DEVICE, 0);
	if (busdevfn == -1) {
		puts("Tsi148: No Tundra Tsi148 found!\n");
		return -1;
	}

	/* Lets turn Latency off */
	pci_write_config_dword(busdevfn, 0x0c, 0);

	dev = malloc(sizeof(*dev));
	if (NULL == dev) {
		puts("Tsi148: No memory!\n");
		return -1;
	}

	memset(dev, 0, sizeof(*dev));
	dev->busdevfn = busdevfn;

	pci_read_config_dword(busdevfn, PCI_BASE_ADDRESS_0, &val);
	val &= ~0xf;
	dev->uregs = (TSI148 *)val;

	debug("Tsi148: Base    : %p\n", dev->uregs);

	/* check mapping */
	debug("Tsi148: Read via mapping, PCI_ID = %08X\n",
	      readl(&dev->uregs->pci_id));
	if (((LPCI_DEVICE << 16) | LPCI_VENDOR) != readl(&dev->uregs->pci_id)) {
		printf("Tsi148: Cannot read PCI-ID via Mapping: %08x\n",
		       readl(&dev->uregs->pci_id));
		result = -1;
		goto break_30;
	}

	debug("Tsi148: PCI_BS = %08X\n", readl(&dev->uregs->pci_mbarl));

	dev->pci_bs = readl(&dev->uregs->pci_mbarl);

	/* turn off windows */
	for (j = 0; j < 8; j++) {
		__raw_writel(htonl(0x00000000), &dev->uregs->outbound[j].otat);
		__raw_writel(htonl(0x00000000), &dev->uregs->inbound[j].itat);
	}

	/* Tsi148 VME timeout etc */
	__raw_writel(htonl(0x00000084), &dev->uregs->vctrl);

#ifdef DEBUG
	if ((__raw_readl(&dev->uregs->vstat) & 0x00000100) != 0)
		printf("Tsi148: System Controller!\n");
	else
		printf("Tsi148: Not System Controller!\n");
#endif

	/*
	 * Lets turn off interrupts
	 */
	/* Disable interrupts in Tsi148 first */
	__raw_writel(htonl(0x00000000), &dev->uregs->inten);
	/* Disable interrupt out */
	__raw_writel(htonl(0x00000000), &dev->uregs->inteo);
	eieio();
	/* Reset all IRQ's */
	__raw_writel(htonl(0x03ff3f00), &dev->uregs->intc);
	/* Map all ints to 0 */
	__raw_writel(htonl(0x00000000), &dev->uregs->intm1);
	__raw_writel(htonl(0x00000000), &dev->uregs->intm2);
	eieio();

	val = __raw_readl(&dev->uregs->vstat);
	val &= ~(0x00004000);
	__raw_writel(val, &dev->uregs->vstat);
	eieio();

	debug("Tsi148: register struct size %08x\n", sizeof(TSI148));

	return 0;

 break_30:
	free(dev);
	dev = NULL;

	return result;
}

/*
 * Create pci slave window (access: pci -> vme)
 */
int tsi148_pci_slave_window(unsigned int pciAddr, unsigned int vmeAddr,
			    int size, int vam, int vdw)
{
	int result, i;
	unsigned int ctl = 0;

	if (NULL == dev) {
		result = -1;
		goto exit_10;
	}

	for (i = 0; i < 8; i++) {
		if (0x00000000 == readl(&dev->uregs->outbound[i].otat))
			break;
	}

	if (i > 7) {
		printf("Tsi148: No Image available\n");
		result = -1;
		goto exit_10;
	}

	debug("Tsi148: Using image %d\n", i);

	printf("Tsi148: Pci addr %08x\n", pciAddr);

	__raw_writel(htonl(pciAddr), &dev->uregs->outbound[i].otsal);
	__raw_writel(0x00000000, &dev->uregs->outbound[i].otsau);
	__raw_writel(htonl(pciAddr + size), &dev->uregs->outbound[i].oteal);
	__raw_writel(0x00000000, &dev->uregs->outbound[i].oteau);
	__raw_writel(htonl(vmeAddr - pciAddr), &dev->uregs->outbound[i].otofl);
	__raw_writel(0x00000000, &dev->uregs->outbound[i].otofu);

	switch (vam & VME_AM_Axx) {
	case VME_AM_A16:
		ctl = 0x00000000;
		break;
	case VME_AM_A24:
		ctl = 0x00000001;
		break;
	case VME_AM_A32:
		ctl = 0x00000002;
		break;
	}

	switch (vam & VME_AM_Mxx) {
	case VME_AM_DATA:
		ctl |= 0x00000000;
		break;
	case VME_AM_PROG:
		ctl |= 0x00000010;
		break;
	}

	if (vam & VME_AM_SUP)
		ctl |= 0x00000020;

	switch (vdw & VME_FLAG_Dxx) {
	case VME_FLAG_D16:
		ctl |= 0x00000000;
		break;
	case VME_FLAG_D32:
		ctl |= 0x00000040;
		break;
	}

	ctl |= 0x80040000;	/* enable, no prefetch */

	__raw_writel(htonl(ctl), &dev->uregs->outbound[i].otat);

	debug("Tsi148: window-addr                =%p\n",
	      &dev->uregs->outbound[i].otsau);
	debug("Tsi148: pci slave window[%d] attr  =%08x\n",
	      i, ntohl(__raw_readl(&dev->uregs->outbound[i].otat)));
	debug("Tsi148: pci slave window[%d] start =%08x\n",
	      i, ntohl(__raw_readl(&dev->uregs->outbound[i].otsal)));
	debug("Tsi148: pci slave window[%d] end   =%08x\n",
	      i, ntohl(__raw_readl(&dev->uregs->outbound[i].oteal)));
	debug("Tsi148: pci slave window[%d] offset=%08x\n",
	      i, ntohl(__raw_readl(&dev->uregs->outbound[i].otofl)));

	return 0;

 exit_10:
	return -result;
}

unsigned int tsi148_eval_vam(int vam)
{
	unsigned int ctl = 0;

	switch (vam & VME_AM_Axx) {
	case VME_AM_A16:
		ctl = 0x00000000;
		break;
	case VME_AM_A24:
		ctl = 0x00000010;
		break;
	case VME_AM_A32:
		ctl = 0x00000020;
		break;
	}
	switch (vam & VME_AM_Mxx) {
	case VME_AM_DATA:
		ctl |= 0x00000001;
		break;
	case VME_AM_PROG:
		ctl |= 0x00000002;
		break;
	case (VME_AM_PROG | VME_AM_DATA):
		ctl |= 0x00000003;
		break;
	}

	if (vam & VME_AM_SUP)
		ctl |= 0x00000008;
	if (vam & VME_AM_USR)
		ctl |= 0x00000004;

	return ctl;
}

/*
 * Create vme slave window (access: vme -> pci)
 */
int tsi148_vme_slave_window(unsigned int vmeAddr, unsigned int pciAddr,
			    int size, int vam)
{
	int result, i;
	unsigned int ctl = 0;

	if (NULL == dev) {
		result = -1;
		goto exit_10;
	}

	for (i = 0; i < 8; i++) {
		if (0x00000000 == readl(&dev->uregs->inbound[i].itat))
			break;
	}

	if (i > 7) {
		printf("Tsi148: No Image available\n");
		result = -1;
		goto exit_10;
	}

	debug("Tsi148: Using image %d\n", i);

	__raw_writel(htonl(vmeAddr), &dev->uregs->inbound[i].itsal);
	__raw_writel(0x00000000, &dev->uregs->inbound[i].itsau);
	__raw_writel(htonl(vmeAddr + size), &dev->uregs->inbound[i].iteal);
	__raw_writel(0x00000000, &dev->uregs->inbound[i].iteau);
	__raw_writel(htonl(pciAddr - vmeAddr), &dev->uregs->inbound[i].itofl);
	if (vmeAddr > pciAddr)
		__raw_writel(0xffffffff, &dev->uregs->inbound[i].itofu);
	else
		__raw_writel(0x00000000, &dev->uregs->inbound[i].itofu);

	ctl = tsi148_eval_vam(vam);
	ctl |= 0x80000000;	/* enable */
	__raw_writel(htonl(ctl), &dev->uregs->inbound[i].itat);

	debug("Tsi148: window-addr                =%p\n",
	      &dev->uregs->inbound[i].itsau);
	debug("Tsi148: vme slave window[%d] attr  =%08x\n",
	      i, ntohl(__raw_readl(&dev->uregs->inbound[i].itat)));
	debug("Tsi148: vme slave window[%d] start =%08x\n",
	      i, ntohl(__raw_readl(&dev->uregs->inbound[i].itsal)));
	debug("Tsi148: vme slave window[%d] end   =%08x\n",
	      i, ntohl(__raw_readl(&dev->uregs->inbound[i].iteal)));
	debug("Tsi148: vme slave window[%d] offset=%08x\n",
	      i, ntohl(__raw_readl(&dev->uregs->inbound[i].itofl)));

	return 0;

 exit_10:
	return -result;
}

/*
 * Create vme slave window (access: vme -> gcsr)
 */
int tsi148_vme_gcsr_window(unsigned int vmeAddr, int vam)
{
	int result;
	unsigned int ctl;

	result = 0;

	if (NULL == dev) {
		result = 1;
	} else {
		__raw_writel(htonl(vmeAddr), &dev->uregs->gbal);
		__raw_writel(0x00000000, &dev->uregs->gbau);

		ctl = tsi148_eval_vam(vam);
		ctl |= 0x00000080;	/* enable */
		__raw_writel(htonl(ctl), &dev->uregs->gcsrat);
	}

	return result;
}

/*
 * Create vme slave window (access: vme -> crcsr)
 */
int tsi148_vme_crcsr_window(unsigned int vmeAddr)
{
	int result;
	unsigned int ctl;

	result = 0;

	if (NULL == dev) {
		result = 1;
	} else {
		__raw_writel(htonl(vmeAddr), &dev->uregs->crol);
		__raw_writel(0x00000000, &dev->uregs->crou);

		ctl = 0x00000080;	/* enable */
		__raw_writel(htonl(ctl), &dev->uregs->crat);
	}

	return result;
}

/*
 * Create vme slave window (access: vme -> crg)
 */
int tsi148_vme_crg_window(unsigned int vmeAddr, int vam)
{
	int result;
	unsigned int ctl;

	result = 0;

	if (NULL == dev) {
		result = 1;
	} else {
		__raw_writel(htonl(vmeAddr), &dev->uregs->cbal);
		__raw_writel(0x00000000, &dev->uregs->cbau);

		ctl = tsi148_eval_vam(vam);
		ctl |= 0x00000080;	/* enable */
		__raw_writel(htonl(ctl), &dev->uregs->crgat);
	}

	return result;
}

/*
 * Tundra Tsi148 configuration
 */
int do_tsi148(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
	ulong addr1 = 0, addr2 = 0, size = 0, vam = 0, vdw = 0;
	char cmd = 'x';

	/* get parameter */
	if (argc > 1)
		cmd = argv[1][0];
	if (argc > 2)
		addr1 = hextoul(argv[2], NULL);
	if (argc > 3)
		addr2 = hextoul(argv[3], NULL);
	if (argc > 4)
		size = hextoul(argv[4], NULL);
	if (argc > 5)
		vam = hextoul(argv[5], NULL);
	if (argc > 6)
		vdw = hextoul(argv[6], NULL);

	switch (cmd) {
	case 'c':
		if (strcmp(argv[1], "crg") == 0) {
			vam = addr2;
			printf("Tsi148: Configuring VME CRG Window "
			       "(VME->CRG):\n");
			printf("  vme=%08lx vam=%02lx\n", addr1, vam);
			tsi148_vme_crg_window(addr1, vam);
		} else {
			printf("Tsi148: Configuring VME CR/CSR Window "
			       "(VME->CR/CSR):\n");
			printf("  pci=%08lx\n", addr1);
			tsi148_vme_crcsr_window(addr1);
		}
		break;
	case 'i':		/* init */
		tsi148_init();
		break;
	case 'g':
		vam = addr2;
		printf("Tsi148: Configuring VME GCSR Window (VME->GCSR):\n");
		printf("  vme=%08lx vam=%02lx\n", addr1, vam);
		tsi148_vme_gcsr_window(addr1, vam);
		break;
	case 'v':		/* vme */
		printf("Tsi148: Configuring VME Slave Window (VME->PCI):\n");
		printf("  vme=%08lx pci=%08lx size=%08lx vam=%02lx\n",
		       addr1, addr2, size, vam);
		tsi148_vme_slave_window(addr1, addr2, size, vam);
		break;
	case 'p':		/* pci */
		printf("Tsi148: Configuring PCI Slave Window (PCI->VME):\n");
		printf("  pci=%08lx vme=%08lx size=%08lx vam=%02lx vdw=%02lx\n",
		       addr1, addr2, size, vam, vdw);
		tsi148_pci_slave_window(addr1, addr2, size, vam, vdw);
		break;
	default:
		printf("Tsi148: Command %s not supported!\n", argv[1]);
	}

	return 0;
}

U_BOOT_CMD(
	tsi148,	7,	1,	do_tsi148,
	"initialize and configure Turndra Tsi148\n",
	"init\n"
	"    - initialize tsi148\n"
	"tsi148 vme   [vme_addr] [pci_addr] [size] [vam]\n"
	"    - create vme slave window (access: vme->pci)\n"
	"tsi148 pci   [pci_addr] [vme_addr] [size] [vam] [vdw]\n"
	"    - create pci slave window (access: pci->vme)\n"
	"tsi148 crg   [vme_addr] [vam]\n"
	"    - create vme slave window: (access vme->CRG\n"
	"tsi148 crcsr [pci_addr]\n"
	"    - create vme slave window: (access vme->CR/CSR\n"
	"tsi148 gcsr  [vme_addr] [vam]\n"
	"    - create vme slave window: (access vme->GCSR\n"
	"    [vam] = VMEbus Address-Modifier:  01 -> A16 Address Space\n"
	"                                      02 -> A24 Address Space\n"
	"                                      03 -> A32 Address Space\n"
	"                                      04 -> Usr        AM Code\n"
	"                                      08 -> Supervisor AM Code\n"
	"                                      10 -> Data AM Code\n"
	"                                      20 -> Program AM Code\n"
	"    [vdw] = VMEbus Maximum Datawidth: 02 -> D16 Data Width\n"
	"                                      03 -> D32 Data Width\n"
);
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
52a0e2de RA	2	/*
	3	* (C) Copyright 2009 Reinhard Arlt, [email protected]
	4	*
	5	* base on universe.h by
	6	*
	7	* (C) Copyright 2003 Stefan Roese, [email protected]
52a0e2de RA	8	*/
52a0e2de RA	9
d678a59d	10	#include <common.h>
52a0e2de	11	#include <command.h>
f7ae49fc	12	#include <log.h>
52a0e2de RA	13	#include <malloc.h>
	14	#include <asm/io.h>
	15	#include <pci.h>
	16
	17	#include <tsi148.h>
	18
aba92962 SG	19	#define LPCI_VENDOR PCI_VENDOR_ID_TUNDRA
aba92962 SG	20	#define LPCI_DEVICE PCI_DEVICE_ID_TUNDRA_TSI148
52a0e2de RA	21
	22	typedef struct _TSI148_DEV TSI148_DEV;
	23
	24	struct _TSI148_DEV {
2d4a43e2 PT	25	int bus;
	26	pci_dev_t busdevfn;
	27	TSI148 *uregs;
	28	unsigned int pci_bs;
52a0e2de RA	29	};
	30
	31	static TSI148_DEV *dev;
	32
	33	/*
	34	* Most of the TSI148 register are BIGENDIAN
	35	* This is the reason for the __raw_writel(htonl(x), x) usage!
	36	*/
	37
	38	int tsi148_init(void)
	39	{
e1a37f85	40	int j, result;
52a0e2de RA	41	pci_dev_t busdevfn;
	42	unsigned int val;
	43
aba92962	44	busdevfn = pci_find_device(LPCI_VENDOR, LPCI_DEVICE, 0);
52a0e2de RA	45	if (busdevfn == -1) {
	46	puts("Tsi148: No Tundra Tsi148 found!\n");
	47	return -1;
	48	}
	49
	50	/* Lets turn Latency off */
	51	pci_write_config_dword(busdevfn, 0x0c, 0);
	52
	53	dev = malloc(sizeof(*dev));
	54	if (NULL == dev) {
	55	puts("Tsi148: No memory!\n");
e1a37f85	56	return -1;
52a0e2de RA	57	}
	58
	59	memset(dev, 0, sizeof(*dev));
	60	dev->busdevfn = busdevfn;
	61
	62	pci_read_config_dword(busdevfn, PCI_BASE_ADDRESS_0, &val);
	63	val &= ~0xf;
	64	dev->uregs = (TSI148 *)val;
	65
	66	debug("Tsi148: Base : %p\n", dev->uregs);
	67
2d4a43e2 PT	68	/* check mapping */
	69	debug("Tsi148: Read via mapping, PCI_ID = %08X\n",
	70	readl(&dev->uregs->pci_id));
aba92962	71	if (((LPCI_DEVICE << 16) \| LPCI_VENDOR) != readl(&dev->uregs->pci_id)) {
52a0e2de	72	printf("Tsi148: Cannot read PCI-ID via Mapping: %08x\n",
2d4a43e2	73	readl(&dev->uregs->pci_id));
52a0e2de RA	74	result = -1;
	75	goto break_30;
	76	}
	77
	78	debug("Tsi148: PCI_BS = %08X\n", readl(&dev->uregs->pci_mbarl));
	79
	80	dev->pci_bs = readl(&dev->uregs->pci_mbarl);
	81
	82	/* turn off windows */
	83	for (j = 0; j < 8; j++) {
	84	__raw_writel(htonl(0x00000000), &dev->uregs->outbound[j].otat);
	85	__raw_writel(htonl(0x00000000), &dev->uregs->inbound[j].itat);
	86	}
	87
	88	/* Tsi148 VME timeout etc */
	89	__raw_writel(htonl(0x00000084), &dev->uregs->vctrl);
	90
2d4a43e2	91	#ifdef DEBUG
52a0e2de	92	if ((__raw_readl(&dev->uregs->vstat) & 0x00000100) != 0)
2d4a43e2	93	printf("Tsi148: System Controller!\n");
52a0e2de	94	else
2d4a43e2 PT	95	printf("Tsi148: Not System Controller!\n");
2d4a43e2 PT	96	#endif
52a0e2de RA	97
	98	/*
	99	* Lets turn off interrupts
	100	*/
	101	/* Disable interrupts in Tsi148 first */
	102	__raw_writel(htonl(0x00000000), &dev->uregs->inten);
	103	/* Disable interrupt out */
	104	__raw_writel(htonl(0x00000000), &dev->uregs->inteo);
	105	eieio();
	106	/* Reset all IRQ's */
	107	__raw_writel(htonl(0x03ff3f00), &dev->uregs->intc);
	108	/* Map all ints to 0 */
	109	__raw_writel(htonl(0x00000000), &dev->uregs->intm1);
	110	__raw_writel(htonl(0x00000000), &dev->uregs->intm2);
	111	eieio();
	112
2d4a43e2	113	val = __raw_readl(&dev->uregs->vstat);
52a0e2de RA	114	val &= ~(0x00004000);
	115	__raw_writel(val, &dev->uregs->vstat);
	116	eieio();
	117
	118	debug("Tsi148: register struct size %08x\n", sizeof(TSI148));
	119
	120	return 0;
	121
	122	break_30:
	123	free(dev);
	124	dev = NULL;
52a0e2de RA	125
	126	return result;
	127	}
	128
	129	/*
	130	* Create pci slave window (access: pci -> vme)
	131	*/
2d4a43e2 PT	132	int tsi148_pci_slave_window(unsigned int pciAddr, unsigned int vmeAddr,
2d4a43e2 PT	133	int size, int vam, int vdw)
52a0e2de RA	134	{
	135	int result, i;
	136	unsigned int ctl = 0;
	137
	138	if (NULL == dev) {
	139	result = -1;
	140	goto exit_10;
	141	}
	142
	143	for (i = 0; i < 8; i++) {
	144	if (0x00000000 == readl(&dev->uregs->outbound[i].otat))
	145	break;
	146	}
	147
	148	if (i > 7) {
	149	printf("Tsi148: No Image available\n");
	150	result = -1;
	151	goto exit_10;
	152	}
	153
	154	debug("Tsi148: Using image %d\n", i);
	155
	156	printf("Tsi148: Pci addr %08x\n", pciAddr);
	157
2d4a43e2 PT	158	__raw_writel(htonl(pciAddr), &dev->uregs->outbound[i].otsal);
2d4a43e2 PT	159	__raw_writel(0x00000000, &dev->uregs->outbound[i].otsau);
52a0e2de	160	__raw_writel(htonl(pciAddr + size), &dev->uregs->outbound[i].oteal);
2d4a43e2	161	__raw_writel(0x00000000, &dev->uregs->outbound[i].oteau);
52a0e2de	162	__raw_writel(htonl(vmeAddr - pciAddr), &dev->uregs->outbound[i].otofl);
2d4a43e2	163	__raw_writel(0x00000000, &dev->uregs->outbound[i].otofu);
52a0e2de RA	164
	165	switch (vam & VME_AM_Axx) {
	166	case VME_AM_A16:
	167	ctl = 0x00000000;
	168	break;
	169	case VME_AM_A24:
	170	ctl = 0x00000001;
	171	break;
	172	case VME_AM_A32:
	173	ctl = 0x00000002;
	174	break;
	175	}
	176
	177	switch (vam & VME_AM_Mxx) {
	178	case VME_AM_DATA:
	179	ctl \|= 0x00000000;
	180	break;
	181	case VME_AM_PROG:
	182	ctl \|= 0x00000010;
	183	break;
	184	}
	185
	186	if (vam & VME_AM_SUP)
	187	ctl \|= 0x00000020;
	188
	189	switch (vdw & VME_FLAG_Dxx) {
	190	case VME_FLAG_D16:
	191	ctl \|= 0x00000000;
	192	break;
	193	case VME_FLAG_D32:
	194	ctl \|= 0x00000040;
	195	break;
	196	}
	197
2d4a43e2	198	ctl \|= 0x80040000; /* enable, no prefetch */
52a0e2de RA	199
	200	__raw_writel(htonl(ctl), &dev->uregs->outbound[i].otat);
	201
	202	debug("Tsi148: window-addr =%p\n",
	203	&dev->uregs->outbound[i].otsau);
	204	debug("Tsi148: pci slave window[%d] attr =%08x\n",
	205	i, ntohl(__raw_readl(&dev->uregs->outbound[i].otat)));
	206	debug("Tsi148: pci slave window[%d] start =%08x\n",
	207	i, ntohl(__raw_readl(&dev->uregs->outbound[i].otsal)));
	208	debug("Tsi148: pci slave window[%d] end =%08x\n",
	209	i, ntohl(__raw_readl(&dev->uregs->outbound[i].oteal)));
	210	debug("Tsi148: pci slave window[%d] offset=%08x\n",
	211	i, ntohl(__raw_readl(&dev->uregs->outbound[i].otofl)));
	212
	213	return 0;
	214
	215	exit_10:
	216	return -result;
	217	}
	218
	219	unsigned int tsi148_eval_vam(int vam)
	220	{
	221	unsigned int ctl = 0;
	222
	223	switch (vam & VME_AM_Axx) {
	224	case VME_AM_A16:
	225	ctl = 0x00000000;
	226	break;
	227	case VME_AM_A24:
	228	ctl = 0x00000010;
	229	break;
	230	case VME_AM_A32:
	231	ctl = 0x00000020;
	232	break;
	233	}
	234	switch (vam & VME_AM_Mxx) {
	235	case VME_AM_DATA:
	236	ctl \|= 0x00000001;
	237	break;
	238	case VME_AM_PROG:
	239	ctl \|= 0x00000002;
	240	break;
	241	case (VME_AM_PROG \| VME_AM_DATA):
	242	ctl \|= 0x00000003;
	243	break;
	244	}
	245
	246	if (vam & VME_AM_SUP)
	247	ctl \|= 0x00000008;
	248	if (vam & VME_AM_USR)
	249	ctl \|= 0x00000004;
	250
	251	return ctl;
	252	}
	253
	254	/*
	255	* Create vme slave window (access: vme -> pci)
	256	*/
2d4a43e2 PT	257	int tsi148_vme_slave_window(unsigned int vmeAddr, unsigned int pciAddr,
2d4a43e2 PT	258	int size, int vam)
52a0e2de RA	259	{
	260	int result, i;
	261	unsigned int ctl = 0;
	262
	263	if (NULL == dev) {
	264	result = -1;
	265	goto exit_10;
	266	}
	267
	268	for (i = 0; i < 8; i++) {
	269	if (0x00000000 == readl(&dev->uregs->inbound[i].itat))
	270	break;
	271	}
	272
	273	if (i > 7) {
	274	printf("Tsi148: No Image available\n");
	275	result = -1;
	276	goto exit_10;
	277	}
	278
	279	debug("Tsi148: Using image %d\n", i);
	280
	281	__raw_writel(htonl(vmeAddr), &dev->uregs->inbound[i].itsal);
	282	__raw_writel(0x00000000, &dev->uregs->inbound[i].itsau);
	283	__raw_writel(htonl(vmeAddr + size), &dev->uregs->inbound[i].iteal);
	284	__raw_writel(0x00000000, &dev->uregs->inbound[i].iteau);
	285	__raw_writel(htonl(pciAddr - vmeAddr), &dev->uregs->inbound[i].itofl);
	286	if (vmeAddr > pciAddr)
	287	__raw_writel(0xffffffff, &dev->uregs->inbound[i].itofu);
	288	else
	289	__raw_writel(0x00000000, &dev->uregs->inbound[i].itofu);
	290
	291	ctl = tsi148_eval_vam(vam);
2d4a43e2	292	ctl \|= 0x80000000; /* enable */
52a0e2de RA	293	__raw_writel(htonl(ctl), &dev->uregs->inbound[i].itat);
	294
	295	debug("Tsi148: window-addr =%p\n",
	296	&dev->uregs->inbound[i].itsau);
	297	debug("Tsi148: vme slave window[%d] attr =%08x\n",
2d4a43e2	298	i, ntohl(__raw_readl(&dev->uregs->inbound[i].itat)));
52a0e2de RA	299	debug("Tsi148: vme slave window[%d] start =%08x\n",
	300	i, ntohl(__raw_readl(&dev->uregs->inbound[i].itsal)));
	301	debug("Tsi148: vme slave window[%d] end =%08x\n",
	302	i, ntohl(__raw_readl(&dev->uregs->inbound[i].iteal)));
	303	debug("Tsi148: vme slave window[%d] offset=%08x\n",
	304	i, ntohl(__raw_readl(&dev->uregs->inbound[i].itofl)));
	305
	306	return 0;
	307
	308	exit_10:
	309	return -result;
	310	}
	311
	312	/*
	313	* Create vme slave window (access: vme -> gcsr)
	314	*/
	315	int tsi148_vme_gcsr_window(unsigned int vmeAddr, int vam)
	316	{
	317	int result;
	318	unsigned int ctl;
	319
	320	result = 0;
	321
	322	if (NULL == dev) {
	323	result = 1;
	324	} else {
2d4a43e2 PT	325	__raw_writel(htonl(vmeAddr), &dev->uregs->gbal);
2d4a43e2 PT	326	__raw_writel(0x00000000, &dev->uregs->gbau);
52a0e2de	327
2d4a43e2 PT	328	ctl = tsi148_eval_vam(vam);
	329	ctl \|= 0x00000080; /* enable */
	330	__raw_writel(htonl(ctl), &dev->uregs->gcsrat);
52a0e2de RA	331	}
	332
	333	return result;
	334	}
	335
	336	/*
	337	* Create vme slave window (access: vme -> crcsr)
	338	*/
	339	int tsi148_vme_crcsr_window(unsigned int vmeAddr)
	340	{
	341	int result;
	342	unsigned int ctl;
	343
	344	result = 0;
	345
	346	if (NULL == dev) {
	347	result = 1;
	348	} else {
2d4a43e2 PT	349	__raw_writel(htonl(vmeAddr), &dev->uregs->crol);
2d4a43e2 PT	350	__raw_writel(0x00000000, &dev->uregs->crou);
52a0e2de	351
2d4a43e2 PT	352	ctl = 0x00000080; /* enable */
2d4a43e2 PT	353	__raw_writel(htonl(ctl), &dev->uregs->crat);
52a0e2de RA	354	}
	355
	356	return result;
	357	}
	358
52a0e2de RA	359	/*
	360	* Create vme slave window (access: vme -> crg)
	361	*/
	362	int tsi148_vme_crg_window(unsigned int vmeAddr, int vam)
	363	{
	364	int result;
	365	unsigned int ctl;
	366
	367	result = 0;
	368
	369	if (NULL == dev) {
	370	result = 1;
	371	} else {
2d4a43e2 PT	372	__raw_writel(htonl(vmeAddr), &dev->uregs->cbal);
2d4a43e2 PT	373	__raw_writel(0x00000000, &dev->uregs->cbau);
52a0e2de	374
2d4a43e2 PT	375	ctl = tsi148_eval_vam(vam);
	376	ctl \|= 0x00000080; /* enable */
	377	__raw_writel(htonl(ctl), &dev->uregs->crgat);
52a0e2de RA	378	}
	379
	380	return result;
	381	}
	382
	383	/*
	384	* Tundra Tsi148 configuration
	385	*/
09140113	386	int do_tsi148(struct cmd_tbl cmdtp, int flag, int argc, char const argv[])
52a0e2de RA	387	{
	388	ulong addr1 = 0, addr2 = 0, size = 0, vam = 0, vdw = 0;
	389	char cmd = 'x';
	390
	391	/* get parameter */
	392	if (argc > 1)
	393	cmd = argv[1][0];
	394	if (argc > 2)
7e5f460e	395	addr1 = hextoul(argv[2], NULL);
52a0e2de	396	if (argc > 3)
7e5f460e	397	addr2 = hextoul(argv[3], NULL);
52a0e2de	398	if (argc > 4)
7e5f460e	399	size = hextoul(argv[4], NULL);
52a0e2de	400	if (argc > 5)
7e5f460e	401	vam = hextoul(argv[5], NULL);
52a0e2de	402	if (argc > 6)
7e5f460e	403	vdw = hextoul(argv[6], NULL);
52a0e2de RA	404
	405	switch (cmd) {
	406	case 'c':
	407	if (strcmp(argv[1], "crg") == 0) {
	408	vam = addr2;
2d4a43e2 PT	409	printf("Tsi148: Configuring VME CRG Window "
2d4a43e2 PT	410	"(VME->CRG):\n");
52a0e2de RA	411	printf(" vme=%08lx vam=%02lx\n", addr1, vam);
	412	tsi148_vme_crg_window(addr1, vam);
	413	} else {
2d4a43e2 PT	414	printf("Tsi148: Configuring VME CR/CSR Window "
2d4a43e2 PT	415	"(VME->CR/CSR):\n");
52a0e2de RA	416	printf(" pci=%08lx\n", addr1);
	417	tsi148_vme_crcsr_window(addr1);
	418	}
	419	break;
	420	case 'i': /* init */
	421	tsi148_init();
	422	break;
	423	case 'g':
	424	vam = addr2;
	425	printf("Tsi148: Configuring VME GCSR Window (VME->GCSR):\n");
	426	printf(" vme=%08lx vam=%02lx\n", addr1, vam);
	427	tsi148_vme_gcsr_window(addr1, vam);
	428	break;
	429	case 'v': /* vme */
	430	printf("Tsi148: Configuring VME Slave Window (VME->PCI):\n");
	431	printf(" vme=%08lx pci=%08lx size=%08lx vam=%02lx\n",
	432	addr1, addr2, size, vam);
	433	tsi148_vme_slave_window(addr1, addr2, size, vam);
	434	break;
	435	case 'p': /* pci */
	436	printf("Tsi148: Configuring PCI Slave Window (PCI->VME):\n");
	437	printf(" pci=%08lx vme=%08lx size=%08lx vam=%02lx vdw=%02lx\n",
	438	addr1, addr2, size, vam, vdw);
	439	tsi148_pci_slave_window(addr1, addr2, size, vam, vdw);
	440	break;
	441	default:
	442	printf("Tsi148: Command %s not supported!\n", argv[1]);
	443	}
	444
	445	return 0;
	446	}
	447
	448	U_BOOT_CMD(
076f1be8	449	tsi148, 7, 1, do_tsi148,
2d4a43e2	450	"initialize and configure Turndra Tsi148\n",
52a0e2de RA	451	"init\n"
	452	" - initialize tsi148\n"
	453	"tsi148 vme [vme_addr] [pci_addr] [size] [vam]\n"
	454	" - create vme slave window (access: vme->pci)\n"
	455	"tsi148 pci [pci_addr] [vme_addr] [size] [vam] [vdw]\n"
	456	" - create pci slave window (access: pci->vme)\n"
	457	"tsi148 crg [vme_addr] [vam]\n"
	458	" - create vme slave window: (access vme->CRG\n"
	459	"tsi148 crcsr [pci_addr]\n"
	460	" - create vme slave window: (access vme->CR/CSR\n"
	461	"tsi148 gcsr [vme_addr] [vam]\n"
	462	" - create vme slave window: (access vme->GCSR\n"
	463	" [vam] = VMEbus Address-Modifier: 01 -> A16 Address Space\n"
	464	" 02 -> A24 Address Space\n"
	465	" 03 -> A32 Address Space\n"
	466	" 04 -> Usr AM Code\n"
	467	" 08 -> Supervisor AM Code\n"
	468	" 10 -> Data AM Code\n"
	469	" 20 -> Program AM Code\n"
	470	" [vdw] = VMEbus Maximum Datawidth: 02 -> D16 Data Width\n"
	471	" 03 -> D32 Data Width\n"
	472	);