[u-boot.git] / drivers / net / bfin_mac.c

/*
 * Driver for Blackfin On-Chip MAC device
 *
 * Copyright (c) 2005-2008 Analog Device, Inc.
 *
 * Licensed under the GPL-2 or later.
 */

#include <common.h>
#include <config.h>
#include <net.h>
#include <netdev.h>
#include <command.h>
#include <malloc.h>
#include <miiphy.h>
#include <linux/mii.h>

#include <asm/blackfin.h>
#include <asm/clock.h>
#include <asm/portmux.h>
#include <asm/mach-common/bits/dma.h>
#include <asm/mach-common/bits/emac.h>
#include <asm/mach-common/bits/pll.h>

#include "bfin_mac.h"

#ifndef CONFIG_PHY_ADDR
# define CONFIG_PHY_ADDR 1
#endif
#ifndef CONFIG_PHY_CLOCK_FREQ
# define CONFIG_PHY_CLOCK_FREQ 2500000
#endif

#ifdef CONFIG_POST
#include <post.h>
#endif

#define RXBUF_BASE_ADDR		0xFF900000
#define TXBUF_BASE_ADDR		0xFF800000
#define TX_BUF_CNT		1

#define TOUT_LOOP		1000000

static ADI_ETHER_BUFFER *txbuf[TX_BUF_CNT];
static ADI_ETHER_BUFFER *rxbuf[PKTBUFSRX];
static u16 txIdx;		/* index of the current RX buffer */
static u16 rxIdx;		/* index of the current TX buffer */

/* DMAx_CONFIG values at DMA Restart */
static const union {
	u16 data;
	ADI_DMA_CONFIG_REG reg;
} txdmacfg = {
	.reg = {
		.b_DMA_EN  = 1,	/* enabled */
		.b_WNR     = 0,	/* read from memory */
		.b_WDSIZE  = 2,	/* wordsize is 32 bits */
		.b_DMA2D   = 0,
		.b_RESTART = 0,
		.b_DI_SEL  = 0,
		.b_DI_EN   = 0,	/* no interrupt */
		.b_NDSIZE  = 5,	/* 5 half words is desc size */
		.b_FLOW    = 7	/* large desc flow */
	},
};

static int bfin_miiphy_wait(void)
{
	/* poll the STABUSY bit */
	while (bfin_read_EMAC_STAADD() & STABUSY)
		continue;
	return 0;
}

static int bfin_miiphy_read(const char *devname, uchar addr, uchar reg, ushort *val)
{
	if (bfin_miiphy_wait())
		return 1;
	bfin_write_EMAC_STAADD(SET_PHYAD(addr) | SET_REGAD(reg) | STABUSY);
	if (bfin_miiphy_wait())
		return 1;
	*val = bfin_read_EMAC_STADAT();
	return 0;
}

static int bfin_miiphy_write(const char *devname, uchar addr, uchar reg, ushort val)
{
	if (bfin_miiphy_wait())
		return 1;
	bfin_write_EMAC_STADAT(val);
	bfin_write_EMAC_STAADD(SET_PHYAD(addr) | SET_REGAD(reg) | STAOP | STABUSY);
	return 0;
}

int bfin_EMAC_initialize(bd_t *bis)
{
	struct eth_device *dev;
	dev = malloc(sizeof(*dev));
	if (dev == NULL)
		hang();

	memset(dev, 0, sizeof(*dev));
	strcpy(dev->name, "bfin_mac");

	dev->iobase = 0;
	dev->priv = 0;
	dev->init = bfin_EMAC_init;
	dev->halt = bfin_EMAC_halt;
	dev->send = bfin_EMAC_send;
	dev->recv = bfin_EMAC_recv;
	dev->write_hwaddr = bfin_EMAC_setup_addr;

	eth_register(dev);

#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
	miiphy_register(dev->name, bfin_miiphy_read, bfin_miiphy_write);
#endif

	return 0;
}

static int bfin_EMAC_send(struct eth_device *dev, void *packet, int length)
{
	int i;
	int result = 0;

	if (length <= 0) {
		printf("Ethernet: bad packet size: %d\n", length);
		goto out;
	}

	if (bfin_read_DMA2_IRQ_STATUS() & DMA_ERR) {
		printf("Ethernet: tx DMA error\n");
		goto out;
	}

	for (i = 0; (bfin_read_DMA2_IRQ_STATUS() & DMA_RUN); ++i) {
		if (i > TOUT_LOOP) {
			puts("Ethernet: tx time out\n");
			goto out;
		}
	}
	txbuf[txIdx]->FrmData->NoBytes = length;
	memcpy(txbuf[txIdx]->FrmData->Dest, (void *)packet, length);
	txbuf[txIdx]->Dma[0].START_ADDR = (u32) txbuf[txIdx]->FrmData;
	bfin_write_DMA2_NEXT_DESC_PTR(txbuf[txIdx]->Dma);
	bfin_write_DMA2_CONFIG(txdmacfg.data);
	bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE);

	for (i = 0; (txbuf[txIdx]->StatusWord & TX_COMP) == 0; i++) {
		if (i > TOUT_LOOP) {
			puts("Ethernet: tx error\n");
			goto out;
		}
	}
	result = txbuf[txIdx]->StatusWord;
	txbuf[txIdx]->StatusWord = 0;
	if ((txIdx + 1) >= TX_BUF_CNT)
		txIdx = 0;
	else
		txIdx++;
 out:
	debug("BFIN EMAC send: length = %d\n", length);
	return result;
}

static int bfin_EMAC_recv(struct eth_device *dev)
{
	int length = 0;

	for (;;) {
		if ((rxbuf[rxIdx]->StatusWord & RX_COMP) == 0) {
			length = -1;
			break;
		}
		if ((rxbuf[rxIdx]->StatusWord & RX_DMAO) != 0) {
			printf("Ethernet: rx dma overrun\n");
			break;
		}
		if ((rxbuf[rxIdx]->StatusWord & RX_OK) == 0) {
			printf("Ethernet: rx error\n");
			break;
		}
		length = rxbuf[rxIdx]->StatusWord & 0x000007FF;
		if (length <= 4) {
			printf("Ethernet: bad frame\n");
			break;
		}

		debug("%s: len = %d\n", __func__, length - 4);

		net_rx_packets[rxIdx] = rxbuf[rxIdx]->FrmData->Dest;
		net_process_received_packet(net_rx_packets[rxIdx], length - 4);
		bfin_write_DMA1_IRQ_STATUS(DMA_DONE | DMA_ERR);
		rxbuf[rxIdx]->StatusWord = 0x00000000;
		if ((rxIdx + 1) >= PKTBUFSRX)
			rxIdx = 0;
		else
			rxIdx++;
	}

	return length;
}

/**************************************************************
 *
 * Ethernet Initialization Routine
 *
 *************************************************************/

/* MDC = SCLK / MDC_freq / 2 - 1 */
#define MDC_FREQ_TO_DIV(mdc_freq) (get_sclk() / (mdc_freq) / 2 - 1)

#ifndef CONFIG_BFIN_MAC_PINS
# ifdef CONFIG_RMII
#  define CONFIG_BFIN_MAC_PINS P_RMII0
# else
#  define CONFIG_BFIN_MAC_PINS P_MII0
# endif
#endif

static int bfin_miiphy_init(struct eth_device *dev, int *opmode)
{
	const unsigned short pins[] = CONFIG_BFIN_MAC_PINS;
	u16 phydat;
	size_t count;

	/* Enable PHY output */
	bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);

	/* Set all the pins to peripheral mode */
	peripheral_request_list(pins, "bfin_mac");

	/* Odd word alignment for Receive Frame DMA word */
	/* Configure checksum support and rcve frame word alignment */
	bfin_write_EMAC_SYSCTL(RXDWA | RXCKS | SET_MDCDIV(MDC_FREQ_TO_DIV(CONFIG_PHY_CLOCK_FREQ)));

	/* turn on auto-negotiation and wait for link to come up */
	bfin_miiphy_write(dev->name, CONFIG_PHY_ADDR, MII_BMCR, BMCR_ANENABLE);
	count = 0;
	while (1) {
		++count;
		if (bfin_miiphy_read(dev->name, CONFIG_PHY_ADDR, MII_BMSR, &phydat))
			return -1;
		if (phydat & BMSR_LSTATUS)
			break;
		if (count > 30000) {
			printf("%s: link down, check cable\n", dev->name);
			return -1;
		}
		udelay(100);
	}

	/* see what kind of link we have */
	if (bfin_miiphy_read(dev->name, CONFIG_PHY_ADDR, MII_LPA, &phydat))
		return -1;
	if (phydat & LPA_DUPLEX)
		*opmode = FDMODE;
	else
		*opmode = 0;

	bfin_write_EMAC_MMC_CTL(RSTC | CROLL);
	bfin_write_EMAC_VLAN1(EMAC_VLANX_DEF_VAL);
	bfin_write_EMAC_VLAN2(EMAC_VLANX_DEF_VAL);

	/* Initialize the TX DMA channel registers */
	bfin_write_DMA2_X_COUNT(0);
	bfin_write_DMA2_X_MODIFY(4);
	bfin_write_DMA2_Y_COUNT(0);
	bfin_write_DMA2_Y_MODIFY(0);

	/* Initialize the RX DMA channel registers */
	bfin_write_DMA1_X_COUNT(0);
	bfin_write_DMA1_X_MODIFY(4);
	bfin_write_DMA1_Y_COUNT(0);
	bfin_write_DMA1_Y_MODIFY(0);

	return 0;
}

static int bfin_EMAC_setup_addr(struct eth_device *dev)
{
	bfin_write_EMAC_ADDRLO(
		dev->enetaddr[0] |
		dev->enetaddr[1] << 8 |
		dev->enetaddr[2] << 16 |
		dev->enetaddr[3] << 24
	);
	bfin_write_EMAC_ADDRHI(
		dev->enetaddr[4] |
		dev->enetaddr[5] << 8
	);
	return 0;
}

static int bfin_EMAC_init(struct eth_device *dev, bd_t *bd)
{
	u32 opmode;
	int dat;
	int i;
	debug("Eth_init: ......\n");

	txIdx = 0;
	rxIdx = 0;

	/* Initialize System Register */
	if (bfin_miiphy_init(dev, &dat) < 0)
		return -1;

	/* Initialize EMAC address */
	bfin_EMAC_setup_addr(dev);

	/* Initialize TX and RX buffer */
	for (i = 0; i < PKTBUFSRX; i++) {
		rxbuf[i] = SetupRxBuffer(i);
		if (i > 0) {
			rxbuf[i - 1]->Dma[1].NEXT_DESC_PTR = rxbuf[i]->Dma;
			if (i == (PKTBUFSRX - 1))
				rxbuf[i]->Dma[1].NEXT_DESC_PTR = rxbuf[0]->Dma;
		}
	}
	for (i = 0; i < TX_BUF_CNT; i++) {
		txbuf[i] = SetupTxBuffer(i);
		if (i > 0) {
			txbuf[i - 1]->Dma[1].NEXT_DESC_PTR = txbuf[i]->Dma;
			if (i == (TX_BUF_CNT - 1))
				txbuf[i]->Dma[1].NEXT_DESC_PTR = txbuf[0]->Dma;
		}
	}

	/* Set RX DMA */
	bfin_write_DMA1_NEXT_DESC_PTR(rxbuf[0]->Dma);
	bfin_write_DMA1_CONFIG(rxbuf[0]->Dma[0].CONFIG_DATA);

	/* Wait MII done */
	bfin_miiphy_wait();

	/* We enable only RX here */
	/* ASTP   : Enable Automatic Pad Stripping
	   PR     : Promiscuous Mode for test
	   PSF    : Receive frames with total length less than 64 bytes.
	   FDMODE : Full Duplex Mode
	   LB	  : Internal Loopback for test
	   RE     : Receiver Enable */
	if (dat == FDMODE)
		opmode = ASTP | FDMODE | PSF;
	else
		opmode = ASTP | PSF;
	opmode |= RE;
#ifdef CONFIG_RMII
	opmode |= TE | RMII;
#endif
	/* Turn on the EMAC */
	bfin_write_EMAC_OPMODE(opmode);
	return 0;
}

static void bfin_EMAC_halt(struct eth_device *dev)
{
	debug("Eth_halt: ......\n");
	/* Turn off the EMAC */
	bfin_write_EMAC_OPMODE(0);
	/* Turn off the EMAC RX DMA */
	bfin_write_DMA1_CONFIG(0);
	bfin_write_DMA2_CONFIG(0);
}

ADI_ETHER_BUFFER *SetupRxBuffer(int no)
{
	ADI_ETHER_FRAME_BUFFER *frmbuf;
	ADI_ETHER_BUFFER *buf;
	int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2;	/* ensure a multi. of 4 */
	int total_size = nobytes_buffer + RECV_BUFSIZE;

	buf = (void *) (RXBUF_BASE_ADDR + no * total_size);
	frmbuf = (void *) (RXBUF_BASE_ADDR + no * total_size + nobytes_buffer);

	memset(buf, 0x00, nobytes_buffer);
	buf->FrmData = frmbuf;
	memset(frmbuf, 0xfe, RECV_BUFSIZE);

	/* set up first desc to point to receive frame buffer */
	buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
	buf->Dma[0].START_ADDR = (u32) buf->FrmData;
	buf->Dma[0].CONFIG.b_DMA_EN = 1;	/* enabled */
	buf->Dma[0].CONFIG.b_WNR = 1;	/* Write to memory */
	buf->Dma[0].CONFIG.b_WDSIZE = 2;	/* wordsize is 32 bits */
	buf->Dma[0].CONFIG.b_NDSIZE = 5;	/* 5 half words is desc size. */
	buf->Dma[0].CONFIG.b_FLOW = 7;	/* large desc flow */

	/* set up second desc to point to status word */
	buf->Dma[1].NEXT_DESC_PTR = buf->Dma;
	buf->Dma[1].START_ADDR = (u32) & buf->IPHdrChksum;
	buf->Dma[1].CONFIG.b_DMA_EN = 1;	/* enabled */
	buf->Dma[1].CONFIG.b_WNR = 1;	/* Write to memory */
	buf->Dma[1].CONFIG.b_WDSIZE = 2;	/* wordsize is 32 bits */
	buf->Dma[1].CONFIG.b_DI_EN = 1;	/* enable interrupt */
	buf->Dma[1].CONFIG.b_NDSIZE = 5;	/* must be 0 when FLOW is 0 */
	buf->Dma[1].CONFIG.b_FLOW = 7;	/* stop */

	return buf;
}

ADI_ETHER_BUFFER *SetupTxBuffer(int no)
{
	ADI_ETHER_FRAME_BUFFER *frmbuf;
	ADI_ETHER_BUFFER *buf;
	int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2;	/* ensure a multi. of 4 */
	int total_size = nobytes_buffer + RECV_BUFSIZE;

	buf = (void *) (TXBUF_BASE_ADDR + no * total_size);
	frmbuf = (void *) (TXBUF_BASE_ADDR + no * total_size + nobytes_buffer);

	memset(buf, 0x00, nobytes_buffer);
	buf->FrmData = frmbuf;
	memset(frmbuf, 0x00, RECV_BUFSIZE);

	/* set up first desc to point to receive frame buffer */
	buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
	buf->Dma[0].START_ADDR = (u32) buf->FrmData;
	buf->Dma[0].CONFIG.b_DMA_EN = 1;	/* enabled */
	buf->Dma[0].CONFIG.b_WNR = 0;	/* Read to memory */
	buf->Dma[0].CONFIG.b_WDSIZE = 2;	/* wordsize is 32 bits */
	buf->Dma[0].CONFIG.b_NDSIZE = 5;	/* 5 half words is desc size. */
	buf->Dma[0].CONFIG.b_FLOW = 7;	/* large desc flow */

	/* set up second desc to point to status word */
	buf->Dma[1].NEXT_DESC_PTR = &(buf->Dma[0]);
	buf->Dma[1].START_ADDR = (u32) & buf->StatusWord;
	buf->Dma[1].CONFIG.b_DMA_EN = 1;	/* enabled */
	buf->Dma[1].CONFIG.b_WNR = 1;	/* Write to memory */
	buf->Dma[1].CONFIG.b_WDSIZE = 2;	/* wordsize is 32 bits */
	buf->Dma[1].CONFIG.b_DI_EN = 1;	/* enable interrupt */
	buf->Dma[1].CONFIG.b_NDSIZE = 0;	/* must be 0 when FLOW is 0 */
	buf->Dma[1].CONFIG.b_FLOW = 0;	/* stop */

	return buf;
}

#if defined(CONFIG_POST) && defined(CONFIG_SYS_POST_ETHER)
int ether_post_test(int flags)
{
	uchar buf[64];
	int i, value = 0;
	int length;
	uint addr;

	printf("\n--------");
	bfin_EMAC_init(NULL, NULL);
	/* construct the package */
	addr = bfin_read_EMAC_ADDRLO();
	buf[0] = buf[6] = addr;
	buf[1] = buf[7] = addr >> 8;
	buf[2] = buf[8] = addr >> 16;
	buf[3] = buf[9] = addr >> 24;
	addr = bfin_read_EMAC_ADDRHI();
	buf[4] = buf[10] = addr;
	buf[5] = buf[11] = addr >> 8;
	buf[12] = 0x08;		/* Type: ARP */
	buf[13] = 0x06;
	buf[14] = 0x00;		/* Hardware type: Ethernet */
	buf[15] = 0x01;
	buf[16] = 0x08;		/* Protocal type: IP */
	buf[17] = 0x00;
	buf[18] = 0x06;		/* Hardware size    */
	buf[19] = 0x04;		/* Protocol size    */
	buf[20] = 0x00;		/* Opcode: request  */
	buf[21] = 0x01;

	for (i = 0; i < 42; i++)
		buf[i + 22] = i;
	printf("--------Send 64 bytes......\n");
	bfin_EMAC_send(NULL, buf, 64);
	for (i = 0; i < 100; i++) {
		udelay(10000);
		if ((rxbuf[rxIdx]->StatusWord & RX_COMP) != 0) {
			value = 1;
			break;
		}
	}
	if (value == 0) {
		printf("--------EMAC can't receive any data\n");
		eth_halt();
		return -1;
	}
	length = rxbuf[rxIdx]->StatusWord & 0x000007FF - 4;
	for (i = 0; i < length; i++) {
		if (rxbuf[rxIdx]->FrmData->Dest[i] != buf[i]) {
			printf("--------EMAC receive error data!\n");
			eth_halt();
			return -1;
		}
	}
	printf("--------receive %d bytes, matched\n", length);
	bfin_EMAC_halt(NULL);
	return 0;
}
#endif
Commit	Line	Data
26bf7dec	1	/*
395bce4f	2	* Driver for Blackfin On-Chip MAC device
26bf7dec	3	*
395bce4f	4	* Copyright (c) 2005-2008 Analog Device, Inc.
26bf7dec	5	*
395bce4f	6	* Licensed under the GPL-2 or later.
26bf7dec AL	7	*/
	8
	9	#include <common.h>
	10	#include <config.h>
26bf7dec	11	#include <net.h>
89973f8a	12	#include <netdev.h>
26bf7dec AL	13	#include <command.h>
26bf7dec AL	14	#include <malloc.h>
ac45af4e MF	15	#include <miiphy.h>
ac45af4e MF	16	#include <linux/mii.h>
26bf7dec	17
395bce4f	18	#include <asm/blackfin.h>
130fbeb1	19	#include <asm/clock.h>
8339ad73	20	#include <asm/portmux.h>
d4d77308 MF	21	#include <asm/mach-common/bits/dma.h>
	22	#include <asm/mach-common/bits/emac.h>
	23	#include <asm/mach-common/bits/pll.h>
	24
395bce4f MF	25	#include "bfin_mac.h"
395bce4f MF	26
a7ec6ac8 MF	27	#ifndef CONFIG_PHY_ADDR
	28	# define CONFIG_PHY_ADDR 1
	29	#endif
	30	#ifndef CONFIG_PHY_CLOCK_FREQ
	31	# define CONFIG_PHY_CLOCK_FREQ 2500000
	32	#endif
	33
26bf7dec AL	34	#ifdef CONFIG_POST
	35	#include <post.h>
	36	#endif
	37
26bf7dec AL	38	#define RXBUF_BASE_ADDR 0xFF900000
	39	#define TXBUF_BASE_ADDR 0xFF800000
	40	#define TX_BUF_CNT 1
	41
53677ef1	42	#define TOUT_LOOP 1000000
26bf7dec	43
6d7d4803 MF	44	static ADI_ETHER_BUFFER *txbuf[TX_BUF_CNT];
6d7d4803 MF	45	static ADI_ETHER_BUFFER *rxbuf[PKTBUFSRX];
26bf7dec AL	46	static u16 txIdx; /* index of the current RX buffer */
	47	static u16 rxIdx; /* index of the current TX buffer */
	48
26bf7dec	49	/* DMAx_CONFIG values at DMA Restart */
6d7d4803 MF	50	static const union {
	51	u16 data;
	52	ADI_DMA_CONFIG_REG reg;
	53	} txdmacfg = {
	54	.reg = {
	55	.b_DMA_EN = 1, /* enabled */
	56	.b_WNR = 0, /* read from memory */
	57	.b_WDSIZE = 2, /* wordsize is 32 bits */
	58	.b_DMA2D = 0,
	59	.b_RESTART = 0,
	60	.b_DI_SEL = 0,
	61	.b_DI_EN = 0, /* no interrupt */
	62	.b_NDSIZE = 5, /* 5 half words is desc size */
	63	.b_FLOW = 7 /* large desc flow */
	64	},
395bce4f MF	65	};
395bce4f MF	66
ac45af4e MF	67	static int bfin_miiphy_wait(void)
	68	{
	69	/* poll the STABUSY bit */
	70	while (bfin_read_EMAC_STAADD() & STABUSY)
	71	continue;
	72	return 0;
	73	}
	74
5700bb63	75	static int bfin_miiphy_read(const char devname, uchar addr, uchar reg, ushort val)
ac45af4e MF	76	{
	77	if (bfin_miiphy_wait())
	78	return 1;
	79	bfin_write_EMAC_STAADD(SET_PHYAD(addr) \| SET_REGAD(reg) \| STABUSY);
	80	if (bfin_miiphy_wait())
	81	return 1;
	82	*val = bfin_read_EMAC_STADAT();
	83	return 0;
	84	}
	85
5700bb63	86	static int bfin_miiphy_write(const char *devname, uchar addr, uchar reg, ushort val)
ac45af4e MF	87	{
	88	if (bfin_miiphy_wait())
	89	return 1;
	90	bfin_write_EMAC_STADAT(val);
	91	bfin_write_EMAC_STAADD(SET_PHYAD(addr) \| SET_REGAD(reg) \| STAOP \| STABUSY);
	92	return 0;
	93	}
	94
395bce4f	95	int bfin_EMAC_initialize(bd_t *bis)
26bf7dec AL	96	{
26bf7dec AL	97	struct eth_device *dev;
ac45af4e	98	dev = malloc(sizeof(*dev));
26bf7dec AL	99	if (dev == NULL)
	100	hang();
	101
	102	memset(dev, 0, sizeof(*dev));
94060a15	103	strcpy(dev->name, "bfin_mac");
26bf7dec AL	104
	105	dev->iobase = 0;
	106	dev->priv = 0;
	107	dev->init = bfin_EMAC_init;
	108	dev->halt = bfin_EMAC_halt;
	109	dev->send = bfin_EMAC_send;
	110	dev->recv = bfin_EMAC_recv;
4324dc72	111	dev->write_hwaddr = bfin_EMAC_setup_addr;
26bf7dec AL	112
	113	eth_register(dev);
	114
ac45af4e MF	115	#if defined(CONFIG_MII) \|\| defined(CONFIG_CMD_MII)
	116	miiphy_register(dev->name, bfin_miiphy_read, bfin_miiphy_write);
	117	#endif
	118
91494731	119	return 0;
26bf7dec AL	120	}
26bf7dec AL	121
10cbe3b6	122	static int bfin_EMAC_send(struct eth_device dev, void packet, int length)
26bf7dec AL	123	{
	124	int i;
	125	int result = 0;
26bf7dec AL	126
	127	if (length <= 0) {
	128	printf("Ethernet: bad packet size: %d\n", length);
	129	goto out;
	130	}
	131
0c714817	132	if (bfin_read_DMA2_IRQ_STATUS() & DMA_ERR) {
26bf7dec AL	133	printf("Ethernet: tx DMA error\n");
	134	goto out;
	135	}
	136
0c714817	137	for (i = 0; (bfin_read_DMA2_IRQ_STATUS() & DMA_RUN); ++i) {
26bf7dec AL	138	if (i > TOUT_LOOP) {
	139	puts("Ethernet: tx time out\n");
	140	goto out;
	141	}
	142	}
	143	txbuf[txIdx]->FrmData->NoBytes = length;
	144	memcpy(txbuf[txIdx]->FrmData->Dest, (void *)packet, length);
	145	txbuf[txIdx]->Dma[0].START_ADDR = (u32) txbuf[txIdx]->FrmData;
0c714817 MF	146	bfin_write_DMA2_NEXT_DESC_PTR(txbuf[txIdx]->Dma);
	147	bfin_write_DMA2_CONFIG(txdmacfg.data);
	148	bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() \| TE);
26bf7dec AL	149
	150	for (i = 0; (txbuf[txIdx]->StatusWord & TX_COMP) == 0; i++) {
	151	if (i > TOUT_LOOP) {
	152	puts("Ethernet: tx error\n");
	153	goto out;
	154	}
	155	}
	156	result = txbuf[txIdx]->StatusWord;
	157	txbuf[txIdx]->StatusWord = 0;
	158	if ((txIdx + 1) >= TX_BUF_CNT)
	159	txIdx = 0;
	160	else
	161	txIdx++;
395bce4f	162	out:
8eed6ca5	163	debug("BFIN EMAC send: length = %d\n", length);
26bf7dec AL	164	return result;
	165	}
	166
	167	static int bfin_EMAC_recv(struct eth_device *dev)
	168	{
	169	int length = 0;
	170
	171	for (;;) {
	172	if ((rxbuf[rxIdx]->StatusWord & RX_COMP) == 0) {
	173	length = -1;
	174	break;
	175	}
	176	if ((rxbuf[rxIdx]->StatusWord & RX_DMAO) != 0) {
	177	printf("Ethernet: rx dma overrun\n");
	178	break;
	179	}
	180	if ((rxbuf[rxIdx]->StatusWord & RX_OK) == 0) {
	181	printf("Ethernet: rx error\n");
	182	break;
	183	}
	184	length = rxbuf[rxIdx]->StatusWord & 0x000007FF;
	185	if (length <= 4) {
	186	printf("Ethernet: bad frame\n");
	187	break;
	188	}
488feef8 RG	189
	190	debug("%s: len = %d\n", __func__, length - 4);
	191
1fd92db8 JH	192	net_rx_packets[rxIdx] = rxbuf[rxIdx]->FrmData->Dest;
1fd92db8 JH	193	net_process_received_packet(net_rx_packets[rxIdx], length - 4);
0c714817	194	bfin_write_DMA1_IRQ_STATUS(DMA_DONE \| DMA_ERR);
26bf7dec AL	195	rxbuf[rxIdx]->StatusWord = 0x00000000;
	196	if ((rxIdx + 1) >= PKTBUFSRX)
	197	rxIdx = 0;
	198	else
	199	rxIdx++;
	200	}
	201
	202	return length;
	203	}
	204
	205	/**************************************************************
	206	*
	207	* Ethernet Initialization Routine
	208	*
	209	*************************************************************/
	210
ac45af4e MF	211	/* MDC = SCLK / MDC_freq / 2 - 1 */
	212	#define MDC_FREQ_TO_DIV(mdc_freq) (get_sclk() / (mdc_freq) / 2 - 1)
	213
8339ad73 MF	214	#ifndef CONFIG_BFIN_MAC_PINS
	215	# ifdef CONFIG_RMII
	216	# define CONFIG_BFIN_MAC_PINS P_RMII0
	217	# else
	218	# define CONFIG_BFIN_MAC_PINS P_MII0
	219	# endif
	220	#endif
	221
ac45af4e MF	222	static int bfin_miiphy_init(struct eth_device dev, int opmode)
ac45af4e MF	223	{
8339ad73	224	const unsigned short pins[] = CONFIG_BFIN_MAC_PINS;
ac45af4e MF	225	u16 phydat;
	226	size_t count;
	227
	228	/* Enable PHY output */
0c714817	229	bfin_write_VR_CTL(bfin_read_VR_CTL() \| CLKBUFOE);
ac45af4e MF	230
ac45af4e MF	231	/* Set all the pins to peripheral mode */
8339ad73	232	peripheral_request_list(pins, "bfin_mac");
ac45af4e MF	233
	234	/* Odd word alignment for Receive Frame DMA word */
	235	/* Configure checksum support and rcve frame word alignment */
a7ec6ac8	236	bfin_write_EMAC_SYSCTL(RXDWA \| RXCKS \| SET_MDCDIV(MDC_FREQ_TO_DIV(CONFIG_PHY_CLOCK_FREQ)));
ac45af4e MF	237
ac45af4e MF	238	/* turn on auto-negotiation and wait for link to come up */
a7ec6ac8	239	bfin_miiphy_write(dev->name, CONFIG_PHY_ADDR, MII_BMCR, BMCR_ANENABLE);
ac45af4e MF	240	count = 0;
	241	while (1) {
	242	++count;
a7ec6ac8	243	if (bfin_miiphy_read(dev->name, CONFIG_PHY_ADDR, MII_BMSR, &phydat))
ac45af4e MF	244	return -1;
	245	if (phydat & BMSR_LSTATUS)
	246	break;
	247	if (count > 30000) {
	248	printf("%s: link down, check cable\n", dev->name);
	249	return -1;
	250	}
	251	udelay(100);
	252	}
	253
	254	/* see what kind of link we have */
a7ec6ac8	255	if (bfin_miiphy_read(dev->name, CONFIG_PHY_ADDR, MII_LPA, &phydat))
ac45af4e MF	256	return -1;
	257	if (phydat & LPA_DUPLEX)
	258	*opmode = FDMODE;
	259	else
	260	*opmode = 0;
	261
	262	bfin_write_EMAC_MMC_CTL(RSTC \| CROLL);
819ca38f AW	263	bfin_write_EMAC_VLAN1(EMAC_VLANX_DEF_VAL);
819ca38f AW	264	bfin_write_EMAC_VLAN2(EMAC_VLANX_DEF_VAL);
ac45af4e MF	265
ac45af4e MF	266	/* Initialize the TX DMA channel registers */
0c714817 MF	267	bfin_write_DMA2_X_COUNT(0);
	268	bfin_write_DMA2_X_MODIFY(4);
	269	bfin_write_DMA2_Y_COUNT(0);
	270	bfin_write_DMA2_Y_MODIFY(0);
ac45af4e MF	271
ac45af4e MF	272	/* Initialize the RX DMA channel registers */
0c714817 MF	273	bfin_write_DMA1_X_COUNT(0);
	274	bfin_write_DMA1_X_MODIFY(4);
	275	bfin_write_DMA1_Y_COUNT(0);
	276	bfin_write_DMA1_Y_MODIFY(0);
ac45af4e MF	277
	278	return 0;
	279	}
	280
4324dc72 MF	281	static int bfin_EMAC_setup_addr(struct eth_device *dev)
4324dc72 MF	282	{
0c714817	283	bfin_write_EMAC_ADDRLO(
4324dc72 MF	284	dev->enetaddr[0] \|
	285	dev->enetaddr[1] << 8 \|
	286	dev->enetaddr[2] << 16 \|
0c714817 MF	287	dev->enetaddr[3] << 24
	288	);
	289	bfin_write_EMAC_ADDRHI(
4324dc72	290	dev->enetaddr[4] \|
0c714817 MF	291	dev->enetaddr[5] << 8
0c714817 MF	292	);
4324dc72 MF	293	return 0;
	294	}
	295
395bce4f	296	static int bfin_EMAC_init(struct eth_device dev, bd_t bd)
26bf7dec AL	297	{
	298	u32 opmode;
	299	int dat;
	300	int i;
8eed6ca5	301	debug("Eth_init: ......\n");
26bf7dec AL	302
	303	txIdx = 0;
	304	rxIdx = 0;
	305
ac45af4e MF	306	/* Initialize System Register */
ac45af4e MF	307	if (bfin_miiphy_init(dev, &dat) < 0)
26bf7dec AL	308	return -1;
26bf7dec AL	309
ac45af4e	310	/* Initialize EMAC address */
4324dc72	311	bfin_EMAC_setup_addr(dev);
26bf7dec	312
ac45af4e	313	/* Initialize TX and RX buffer */
26bf7dec AL	314	for (i = 0; i < PKTBUFSRX; i++) {
	315	rxbuf[i] = SetupRxBuffer(i);
	316	if (i > 0) {
6d7d4803	317	rxbuf[i - 1]->Dma[1].NEXT_DESC_PTR = rxbuf[i]->Dma;
26bf7dec	318	if (i == (PKTBUFSRX - 1))
6d7d4803	319	rxbuf[i]->Dma[1].NEXT_DESC_PTR = rxbuf[0]->Dma;
26bf7dec AL	320	}
	321	}
	322	for (i = 0; i < TX_BUF_CNT; i++) {
	323	txbuf[i] = SetupTxBuffer(i);
	324	if (i > 0) {
6d7d4803	325	txbuf[i - 1]->Dma[1].NEXT_DESC_PTR = txbuf[i]->Dma;
26bf7dec	326	if (i == (TX_BUF_CNT - 1))
6d7d4803	327	txbuf[i]->Dma[1].NEXT_DESC_PTR = txbuf[0]->Dma;
26bf7dec AL	328	}
	329	}
	330
	331	/* Set RX DMA */
0c714817 MF	332	bfin_write_DMA1_NEXT_DESC_PTR(rxbuf[0]->Dma);
0c714817 MF	333	bfin_write_DMA1_CONFIG(rxbuf[0]->Dma[0].CONFIG_DATA);
26bf7dec AL	334
26bf7dec AL	335	/* Wait MII done */
ac45af4e	336	bfin_miiphy_wait();
26bf7dec AL	337
	338	/* We enable only RX here */
	339	/* ASTP : Enable Automatic Pad Stripping
	340	PR : Promiscuous Mode for test
	341	PSF : Receive frames with total length less than 64 bytes.
	342	FDMODE : Full Duplex Mode
	343	LB : Internal Loopback for test
	344	RE : Receiver Enable */
	345	if (dat == FDMODE)
	346	opmode = ASTP \| FDMODE \| PSF;
	347	else
	348	opmode = ASTP \| PSF;
	349	opmode \|= RE;
092d2487	350	#ifdef CONFIG_RMII
26bf7dec AL	351	opmode \|= TE \| RMII;
	352	#endif
	353	/* Turn on the EMAC */
0c714817	354	bfin_write_EMAC_OPMODE(opmode);
26bf7dec AL	355	return 0;
	356	}
	357
	358	static void bfin_EMAC_halt(struct eth_device *dev)
	359	{
8eed6ca5	360	debug("Eth_halt: ......\n");
26bf7dec	361	/* Turn off the EMAC */
0c714817	362	bfin_write_EMAC_OPMODE(0);
26bf7dec	363	/* Turn off the EMAC RX DMA */
0c714817 MF	364	bfin_write_DMA1_CONFIG(0);
0c714817 MF	365	bfin_write_DMA2_CONFIG(0);
26bf7dec AL	366	}
26bf7dec AL	367
26bf7dec AL	368	ADI_ETHER_BUFFER *SetupRxBuffer(int no)
	369	{
	370	ADI_ETHER_FRAME_BUFFER *frmbuf;
	371	ADI_ETHER_BUFFER *buf;
	372	int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2; /* ensure a multi. of 4 */
	373	int total_size = nobytes_buffer + RECV_BUFSIZE;
	374
6d7d4803 MF	375	buf = (void ) (RXBUF_BASE_ADDR + no total_size);
6d7d4803 MF	376	frmbuf = (void ) (RXBUF_BASE_ADDR + no total_size + nobytes_buffer);
26bf7dec AL	377
	378	memset(buf, 0x00, nobytes_buffer);
	379	buf->FrmData = frmbuf;
	380	memset(frmbuf, 0xfe, RECV_BUFSIZE);
	381
	382	/* set up first desc to point to receive frame buffer */
	383	buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
	384	buf->Dma[0].START_ADDR = (u32) buf->FrmData;
	385	buf->Dma[0].CONFIG.b_DMA_EN = 1; /* enabled */
	386	buf->Dma[0].CONFIG.b_WNR = 1; /* Write to memory */
	387	buf->Dma[0].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
	388	buf->Dma[0].CONFIG.b_NDSIZE = 5; /* 5 half words is desc size. */
	389	buf->Dma[0].CONFIG.b_FLOW = 7; /* large desc flow */
	390
	391	/* set up second desc to point to status word */
6d7d4803	392	buf->Dma[1].NEXT_DESC_PTR = buf->Dma;
26bf7dec AL	393	buf->Dma[1].START_ADDR = (u32) & buf->IPHdrChksum;
	394	buf->Dma[1].CONFIG.b_DMA_EN = 1; /* enabled */
	395	buf->Dma[1].CONFIG.b_WNR = 1; /* Write to memory */
	396	buf->Dma[1].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
	397	buf->Dma[1].CONFIG.b_DI_EN = 1; /* enable interrupt */
	398	buf->Dma[1].CONFIG.b_NDSIZE = 5; /* must be 0 when FLOW is 0 */
	399	buf->Dma[1].CONFIG.b_FLOW = 7; /* stop */
	400
	401	return buf;
	402	}
	403
	404	ADI_ETHER_BUFFER *SetupTxBuffer(int no)
	405	{
	406	ADI_ETHER_FRAME_BUFFER *frmbuf;
	407	ADI_ETHER_BUFFER *buf;
	408	int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2; /* ensure a multi. of 4 */
	409	int total_size = nobytes_buffer + RECV_BUFSIZE;
	410
6d7d4803 MF	411	buf = (void ) (TXBUF_BASE_ADDR + no total_size);
6d7d4803 MF	412	frmbuf = (void ) (TXBUF_BASE_ADDR + no total_size + nobytes_buffer);
26bf7dec AL	413
	414	memset(buf, 0x00, nobytes_buffer);
	415	buf->FrmData = frmbuf;
	416	memset(frmbuf, 0x00, RECV_BUFSIZE);
	417
	418	/* set up first desc to point to receive frame buffer */
	419	buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
	420	buf->Dma[0].START_ADDR = (u32) buf->FrmData;
	421	buf->Dma[0].CONFIG.b_DMA_EN = 1; /* enabled */
	422	buf->Dma[0].CONFIG.b_WNR = 0; /* Read to memory */
	423	buf->Dma[0].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
	424	buf->Dma[0].CONFIG.b_NDSIZE = 5; /* 5 half words is desc size. */
	425	buf->Dma[0].CONFIG.b_FLOW = 7; /* large desc flow */
	426
	427	/* set up second desc to point to status word */
	428	buf->Dma[1].NEXT_DESC_PTR = &(buf->Dma[0]);
	429	buf->Dma[1].START_ADDR = (u32) & buf->StatusWord;
	430	buf->Dma[1].CONFIG.b_DMA_EN = 1; /* enabled */
	431	buf->Dma[1].CONFIG.b_WNR = 1; /* Write to memory */
	432	buf->Dma[1].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
	433	buf->Dma[1].CONFIG.b_DI_EN = 1; /* enable interrupt */
	434	buf->Dma[1].CONFIG.b_NDSIZE = 0; /* must be 0 when FLOW is 0 */
	435	buf->Dma[1].CONFIG.b_FLOW = 0; /* stop */
	436
	437	return buf;
	438	}
	439
6d0f6bcf	440	#if defined(CONFIG_POST) && defined(CONFIG_SYS_POST_ETHER)
26bf7dec AL	441	int ether_post_test(int flags)
	442	{
	443	uchar buf[64];
	444	int i, value = 0;
	445	int length;
0c714817	446	uint addr;
26bf7dec AL	447
	448	printf("\n--------");
	449	bfin_EMAC_init(NULL, NULL);
	450	/* construct the package */
0c714817 MF	451	addr = bfin_read_EMAC_ADDRLO();
	452	buf[0] = buf[6] = addr;
	453	buf[1] = buf[7] = addr >> 8;
	454	buf[2] = buf[8] = addr >> 16;
	455	buf[3] = buf[9] = addr >> 24;
	456	addr = bfin_read_EMAC_ADDRHI();
	457	buf[4] = buf[10] = addr;
	458	buf[5] = buf[11] = addr >> 8;
26bf7dec AL	459	buf[12] = 0x08; /* Type: ARP */
	460	buf[13] = 0x06;
	461	buf[14] = 0x00; /* Hardware type: Ethernet */
	462	buf[15] = 0x01;
	463	buf[16] = 0x08; /* Protocal type: IP */
	464	buf[17] = 0x00;
	465	buf[18] = 0x06; /* Hardware size */
	466	buf[19] = 0x04; /* Protocol size */
	467	buf[20] = 0x00; /* Opcode: request */
	468	buf[21] = 0x01;
	469
	470	for (i = 0; i < 42; i++)
	471	buf[i + 22] = i;
	472	printf("--------Send 64 bytes......\n");
10cbe3b6	473	bfin_EMAC_send(NULL, buf, 64);
26bf7dec AL	474	for (i = 0; i < 100; i++) {
	475	udelay(10000);
	476	if ((rxbuf[rxIdx]->StatusWord & RX_COMP) != 0) {
	477	value = 1;
	478	break;
	479	}
	480	}
	481	if (value == 0) {
	482	printf("--------EMAC can't receive any data\n");
	483	eth_halt();
	484	return -1;
	485	}
	486	length = rxbuf[rxIdx]->StatusWord & 0x000007FF - 4;
	487	for (i = 0; i < length; i++) {
	488	if (rxbuf[rxIdx]->FrmData->Dest[i] != buf[i]) {
	489	printf("--------EMAC receive error data!\n");
	490	eth_halt();
	491	return -1;
	492	}
	493	}
	494	printf("--------receive %d bytes, matched\n", length);
	495	bfin_EMAC_halt(NULL);
	496	return 0;
	497	}
	498	#endif