[u-boot.git] / drivers / net / bfin_mac.c

/*
 * Driver for Blackfin On-Chip MAC device
 *
 * Copyright (c) 2005-2008 Analog Device, Inc.
 *
 * Licensed under the GPL-2 or later.
 */

#include <common.h>
#include <config.h>
#include <net.h>
#include <netdev.h>
#include <command.h>
#include <malloc.h>
#include <miiphy.h>
#include <linux/mii.h>

#include <asm/blackfin.h>
#include <asm/mach-common/bits/dma.h>
#include <asm/mach-common/bits/emac.h>
#include <asm/mach-common/bits/pll.h>

#include "bfin_mac.h"

#ifndef CONFIG_PHY_ADDR
# define CONFIG_PHY_ADDR 1
#endif
#ifndef CONFIG_PHY_CLOCK_FREQ
# define CONFIG_PHY_CLOCK_FREQ 2500000
#endif

#ifdef CONFIG_POST
#include <post.h>
#endif

#define RXBUF_BASE_ADDR		0xFF900000
#define TXBUF_BASE_ADDR		0xFF800000
#define TX_BUF_CNT		1

#define TOUT_LOOP		1000000

ADI_ETHER_BUFFER *txbuf[TX_BUF_CNT];
ADI_ETHER_BUFFER *rxbuf[PKTBUFSRX];
static u16 txIdx;		/* index of the current RX buffer */
static u16 rxIdx;		/* index of the current TX buffer */

/* DMAx_CONFIG values at DMA Restart */
const ADI_DMA_CONFIG_REG rxdmacfg = {
	.b_DMA_EN  = 1,	/* enabled */
	.b_WNR     = 1,	/* write to memory */
	.b_WDSIZE  = 2,	/* wordsize is 32 bits */
	.b_DMA2D   = 0,
	.b_RESTART = 0,
	.b_DI_SEL  = 0,
	.b_DI_EN   = 0,	/* no interrupt */
	.b_NDSIZE  = 5,	/* 5 half words is desc size */
	.b_FLOW    = 7	/* large desc flow */
};

const ADI_DMA_CONFIG_REG txdmacfg = {
	.b_DMA_EN  = 1,	/* enabled */
	.b_WNR     = 0,	/* read from memory */
	.b_WDSIZE  = 2,	/* wordsize is 32 bits */
	.b_DMA2D   = 0,
	.b_RESTART = 0,
	.b_DI_SEL  = 0,
	.b_DI_EN   = 0,	/* no interrupt */
	.b_NDSIZE  = 5,	/* 5 half words is desc size */
	.b_FLOW    = 7	/* large desc flow */
};

static int bfin_miiphy_wait(void)
{
	/* poll the STABUSY bit */
	while (bfin_read_EMAC_STAADD() & STABUSY)
		continue;
	return 0;
}

static int bfin_miiphy_read(char *devname, uchar addr, uchar reg, ushort *val)
{
	if (bfin_miiphy_wait())
		return 1;
	bfin_write_EMAC_STAADD(SET_PHYAD(addr) | SET_REGAD(reg) | STABUSY);
	if (bfin_miiphy_wait())
		return 1;
	*val = bfin_read_EMAC_STADAT();
	return 0;
}

static int bfin_miiphy_write(char *devname, uchar addr, uchar reg, ushort val)
{
	if (bfin_miiphy_wait())
		return 1;
	bfin_write_EMAC_STADAT(val);
	bfin_write_EMAC_STAADD(SET_PHYAD(addr) | SET_REGAD(reg) | STAOP | STABUSY);
	return 0;
}

int bfin_EMAC_initialize(bd_t *bis)
{
	struct eth_device *dev;
	dev = malloc(sizeof(*dev));
	if (dev == NULL)
		hang();

	memset(dev, 0, sizeof(*dev));
	sprintf(dev->name, "Blackfin EMAC");

	dev->iobase = 0;
	dev->priv = 0;
	dev->init = bfin_EMAC_init;
	dev->halt = bfin_EMAC_halt;
	dev->send = bfin_EMAC_send;
	dev->recv = bfin_EMAC_recv;

	eth_register(dev);

#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
	miiphy_register(dev->name, bfin_miiphy_read, bfin_miiphy_write);
#endif

	return 0;
}

static int bfin_EMAC_send(struct eth_device *dev, volatile void *packet,
			  int length)
{
	int i;
	int result = 0;
	unsigned int *buf;
	buf = (unsigned int *)packet;

	if (length <= 0) {
		printf("Ethernet: bad packet size: %d\n", length);
		goto out;
	}

	if ((*pDMA2_IRQ_STATUS & DMA_ERR) != 0) {
		printf("Ethernet: tx DMA error\n");
		goto out;
	}

	for (i = 0; (*pDMA2_IRQ_STATUS & DMA_RUN) != 0; i++) {
		if (i > TOUT_LOOP) {
			puts("Ethernet: tx time out\n");
			goto out;
		}
	}
	txbuf[txIdx]->FrmData->NoBytes = length;
	memcpy(txbuf[txIdx]->FrmData->Dest, (void *)packet, length);
	txbuf[txIdx]->Dma[0].START_ADDR = (u32) txbuf[txIdx]->FrmData;
	*pDMA2_NEXT_DESC_PTR = &txbuf[txIdx]->Dma[0];
	*pDMA2_CONFIG = *(u16 *) (void *)(&txdmacfg);
	*pEMAC_OPMODE |= TE;

	for (i = 0; (txbuf[txIdx]->StatusWord & TX_COMP) == 0; i++) {
		if (i > TOUT_LOOP) {
			puts("Ethernet: tx error\n");
			goto out;
		}
	}
	result = txbuf[txIdx]->StatusWord;
	txbuf[txIdx]->StatusWord = 0;
	if ((txIdx + 1) >= TX_BUF_CNT)
		txIdx = 0;
	else
		txIdx++;
 out:
	debug("BFIN EMAC send: length = %d\n", length);
	return result;
}

static int bfin_EMAC_recv(struct eth_device *dev)
{
	int length = 0;

	for (;;) {
		if ((rxbuf[rxIdx]->StatusWord & RX_COMP) == 0) {
			length = -1;
			break;
		}
		if ((rxbuf[rxIdx]->StatusWord & RX_DMAO) != 0) {
			printf("Ethernet: rx dma overrun\n");
			break;
		}
		if ((rxbuf[rxIdx]->StatusWord & RX_OK) == 0) {
			printf("Ethernet: rx error\n");
			break;
		}
		length = rxbuf[rxIdx]->StatusWord & 0x000007FF;
		if (length <= 4) {
			printf("Ethernet: bad frame\n");
			break;
		}
		NetRxPackets[rxIdx] =
		    (volatile uchar *)(rxbuf[rxIdx]->FrmData->Dest);
		NetReceive(NetRxPackets[rxIdx], length - 4);
		*pDMA1_IRQ_STATUS |= DMA_DONE | DMA_ERR;
		rxbuf[rxIdx]->StatusWord = 0x00000000;
		if ((rxIdx + 1) >= PKTBUFSRX)
			rxIdx = 0;
		else
			rxIdx++;
	}

	return length;
}

/**************************************************************
 *
 * Ethernet Initialization Routine
 *
 *************************************************************/

/* MDC = SCLK / MDC_freq / 2 - 1 */
#define MDC_FREQ_TO_DIV(mdc_freq) (get_sclk() / (mdc_freq) / 2 - 1)

static int bfin_miiphy_init(struct eth_device *dev, int *opmode)
{
	u16 phydat;
	size_t count;

	/* Enable PHY output */
	*pVR_CTL |= CLKBUFOE;

	/* Set all the pins to peripheral mode */
#ifdef CONFIG_BFIN_MAC_RMII
	/* grab RMII pins */
# if defined(__ADSPBF51x__)
	*pPORTF_MUX = (*pPORTF_MUX & \
		~(PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK | PORT_x_MUX_5_MASK)) | \
		PORT_x_MUX_3_FUNC_1 | PORT_x_MUX_4_FUNC_1 | PORT_x_MUX_5_FUNC_1;
	*pPORTF_FER |= PF8 | PF9 | PF10 | PF11 | PF12 | PF13 | PF14 | PF15;
	*pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_0_MASK) | PORT_x_MUX_0_FUNC_1;
	*pPORTG_FER |= PG0 | PG1 | PG2;
# elif defined(__ADSPBF52x__)
	*pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_6_MASK) | PORT_x_MUX_6_FUNC_2;
	*pPORTG_FER |= PG14 | PG15;
	*pPORTH_MUX = (*pPORTH_MUX & ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK)) | \
		PORT_x_MUX_0_FUNC_2 | PORT_x_MUX_1_FUNC_2;
	*pPORTH_FER |= PH0 | PH1 | PH2 | PH3 | PH4 | PH5 | PH6 | PH7 | PH8;
# else
	*pPORTH_FER |= PH0 | PH1 | PH4 | PH5 | PH6 | PH8 | PH9 | PH14 | PH15;
# endif
#else
	/* grab MII & RMII pins */
# if defined(__ADSPBF51x__)
	*pPORTF_MUX = (*pPORTF_MUX & \
		~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK | PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK | PORT_x_MUX_5_MASK)) | \
		PORT_x_MUX_0_FUNC_1 | PORT_x_MUX_1_FUNC_1 | PORT_x_MUX_3_FUNC_1 | PORT_x_MUX_4_FUNC_1 | PORT_x_MUX_5_FUNC_1;
	*pPORTF_FER |= PF0 | PF1 | PF2 | PF3 | PF4 | PF5 | PF6 | PF8 | PF9 | PF10 | PF11 | PF12 | PF13 | PF14 | PF15;
	*pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_0_MASK) | PORT_x_MUX_0_FUNC_1;
	*pPORTG_FER |= PG0 | PG1 | PG2;
# elif defined(__ADSPBF52x__)
	*pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_6_MASK) | PORT_x_MUX_6_FUNC_2;
	*pPORTG_FER |= PG14 | PG15;
	*pPORTH_MUX = PORT_x_MUX_0_FUNC_2 | PORT_x_MUX_1_FUNC_2 | PORT_x_MUX_2_FUNC_2;
	*pPORTH_FER = -1; /* all pins */
# else
	*pPORTH_FER = -1; /* all pins */
# endif
#endif

	/* Odd word alignment for Receive Frame DMA word */
	/* Configure checksum support and rcve frame word alignment */
	bfin_write_EMAC_SYSCTL(RXDWA | RXCKS | SET_MDCDIV(MDC_FREQ_TO_DIV(CONFIG_PHY_CLOCK_FREQ)));

	/* turn on auto-negotiation and wait for link to come up */
	bfin_miiphy_write(dev->name, CONFIG_PHY_ADDR, MII_BMCR, BMCR_ANENABLE);
	count = 0;
	while (1) {
		++count;
		if (bfin_miiphy_read(dev->name, CONFIG_PHY_ADDR, MII_BMSR, &phydat))
			return -1;
		if (phydat & BMSR_LSTATUS)
			break;
		if (count > 30000) {
			printf("%s: link down, check cable\n", dev->name);
			return -1;
		}
		udelay(100);
	}

	/* see what kind of link we have */
	if (bfin_miiphy_read(dev->name, CONFIG_PHY_ADDR, MII_LPA, &phydat))
		return -1;
	if (phydat & LPA_DUPLEX)
		*opmode = FDMODE;
	else
		*opmode = 0;

	bfin_write_EMAC_MMC_CTL(RSTC | CROLL);

	/* Initialize the TX DMA channel registers */
	*pDMA2_X_COUNT = 0;
	*pDMA2_X_MODIFY = 4;
	*pDMA2_Y_COUNT = 0;
	*pDMA2_Y_MODIFY = 0;

	/* Initialize the RX DMA channel registers */
	*pDMA1_X_COUNT = 0;
	*pDMA1_X_MODIFY = 4;
	*pDMA1_Y_COUNT = 0;
	*pDMA1_Y_MODIFY = 0;

	return 0;
}

static int bfin_EMAC_init(struct eth_device *dev, bd_t *bd)
{
	u32 opmode;
	int dat;
	int i;
	debug("Eth_init: ......\n");

	txIdx = 0;
	rxIdx = 0;

	/* Initialize System Register */
	if (bfin_miiphy_init(dev, &dat) < 0)
		return -1;

	/* Initialize EMAC address */
	bfin_EMAC_setup_addr(bd);

	/* Initialize TX and RX buffer */
	for (i = 0; i < PKTBUFSRX; i++) {
		rxbuf[i] = SetupRxBuffer(i);
		if (i > 0) {
			rxbuf[i - 1]->Dma[1].NEXT_DESC_PTR =
			    &(rxbuf[i]->Dma[0]);
			if (i == (PKTBUFSRX - 1))
				rxbuf[i]->Dma[1].NEXT_DESC_PTR =
				    &(rxbuf[0]->Dma[0]);
		}
	}
	for (i = 0; i < TX_BUF_CNT; i++) {
		txbuf[i] = SetupTxBuffer(i);
		if (i > 0) {
			txbuf[i - 1]->Dma[1].NEXT_DESC_PTR =
			    &(txbuf[i]->Dma[0]);
			if (i == (TX_BUF_CNT - 1))
				txbuf[i]->Dma[1].NEXT_DESC_PTR =
				    &(txbuf[0]->Dma[0]);
		}
	}

	/* Set RX DMA */
	*pDMA1_NEXT_DESC_PTR = &rxbuf[0]->Dma[0];
	*pDMA1_CONFIG = *((u16 *) (void *)&rxbuf[0]->Dma[0].CONFIG);

	/* Wait MII done */
	bfin_miiphy_wait();

	/* We enable only RX here */
	/* ASTP   : Enable Automatic Pad Stripping
	   PR     : Promiscuous Mode for test
	   PSF    : Receive frames with total length less than 64 bytes.
	   FDMODE : Full Duplex Mode
	   LB	  : Internal Loopback for test
	   RE     : Receiver Enable */
	if (dat == FDMODE)
		opmode = ASTP | FDMODE | PSF;
	else
		opmode = ASTP | PSF;
	opmode |= RE;
#ifdef CONFIG_BFIN_MAC_RMII
	opmode |= TE | RMII;
#endif
	/* Turn on the EMAC */
	*pEMAC_OPMODE = opmode;
	return 0;
}

static void bfin_EMAC_halt(struct eth_device *dev)
{
	debug("Eth_halt: ......\n");
	/* Turn off the EMAC */
	*pEMAC_OPMODE = 0x00000000;
	/* Turn off the EMAC RX DMA */
	*pDMA1_CONFIG = 0x0000;
	*pDMA2_CONFIG = 0x0000;

}

void bfin_EMAC_setup_addr(bd_t *bd)
{
	*pEMAC_ADDRLO =
		bd->bi_enetaddr[0] |
		bd->bi_enetaddr[1] << 8 |
		bd->bi_enetaddr[2] << 16 |
		bd->bi_enetaddr[3] << 24;
	*pEMAC_ADDRHI =
		bd->bi_enetaddr[4] |
		bd->bi_enetaddr[5] << 8;
}

ADI_ETHER_BUFFER *SetupRxBuffer(int no)
{
	ADI_ETHER_FRAME_BUFFER *frmbuf;
	ADI_ETHER_BUFFER *buf;
	int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2;	/* ensure a multi. of 4 */
	int total_size = nobytes_buffer + RECV_BUFSIZE;

	buf = (ADI_ETHER_BUFFER *) (RXBUF_BASE_ADDR + no * total_size);
	frmbuf =
	    (ADI_ETHER_FRAME_BUFFER *) (RXBUF_BASE_ADDR + no * total_size +
					nobytes_buffer);

	memset(buf, 0x00, nobytes_buffer);
	buf->FrmData = frmbuf;
	memset(frmbuf, 0xfe, RECV_BUFSIZE);

	/* set up first desc to point to receive frame buffer */
	buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
	buf->Dma[0].START_ADDR = (u32) buf->FrmData;
	buf->Dma[0].CONFIG.b_DMA_EN = 1;	/* enabled */
	buf->Dma[0].CONFIG.b_WNR = 1;	/* Write to memory */
	buf->Dma[0].CONFIG.b_WDSIZE = 2;	/* wordsize is 32 bits */
	buf->Dma[0].CONFIG.b_NDSIZE = 5;	/* 5 half words is desc size. */
	buf->Dma[0].CONFIG.b_FLOW = 7;	/* large desc flow */

	/* set up second desc to point to status word */
	buf->Dma[1].NEXT_DESC_PTR = &(buf->Dma[0]);
	buf->Dma[1].START_ADDR = (u32) & buf->IPHdrChksum;
	buf->Dma[1].CONFIG.b_DMA_EN = 1;	/* enabled */
	buf->Dma[1].CONFIG.b_WNR = 1;	/* Write to memory */
	buf->Dma[1].CONFIG.b_WDSIZE = 2;	/* wordsize is 32 bits */
	buf->Dma[1].CONFIG.b_DI_EN = 1;	/* enable interrupt */
	buf->Dma[1].CONFIG.b_NDSIZE = 5;	/* must be 0 when FLOW is 0 */
	buf->Dma[1].CONFIG.b_FLOW = 7;	/* stop */

	return buf;
}

ADI_ETHER_BUFFER *SetupTxBuffer(int no)
{
	ADI_ETHER_FRAME_BUFFER *frmbuf;
	ADI_ETHER_BUFFER *buf;
	int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2;	/* ensure a multi. of 4 */
	int total_size = nobytes_buffer + RECV_BUFSIZE;

	buf = (ADI_ETHER_BUFFER *) (TXBUF_BASE_ADDR + no * total_size);
	frmbuf =
	    (ADI_ETHER_FRAME_BUFFER *) (TXBUF_BASE_ADDR + no * total_size +
					nobytes_buffer);

	memset(buf, 0x00, nobytes_buffer);
	buf->FrmData = frmbuf;
	memset(frmbuf, 0x00, RECV_BUFSIZE);

	/* set up first desc to point to receive frame buffer */
	buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
	buf->Dma[0].START_ADDR = (u32) buf->FrmData;
	buf->Dma[0].CONFIG.b_DMA_EN = 1;	/* enabled */
	buf->Dma[0].CONFIG.b_WNR = 0;	/* Read to memory */
	buf->Dma[0].CONFIG.b_WDSIZE = 2;	/* wordsize is 32 bits */
	buf->Dma[0].CONFIG.b_NDSIZE = 5;	/* 5 half words is desc size. */
	buf->Dma[0].CONFIG.b_FLOW = 7;	/* large desc flow */

	/* set up second desc to point to status word */
	buf->Dma[1].NEXT_DESC_PTR = &(buf->Dma[0]);
	buf->Dma[1].START_ADDR = (u32) & buf->StatusWord;
	buf->Dma[1].CONFIG.b_DMA_EN = 1;	/* enabled */
	buf->Dma[1].CONFIG.b_WNR = 1;	/* Write to memory */
	buf->Dma[1].CONFIG.b_WDSIZE = 2;	/* wordsize is 32 bits */
	buf->Dma[1].CONFIG.b_DI_EN = 1;	/* enable interrupt */
	buf->Dma[1].CONFIG.b_NDSIZE = 0;	/* must be 0 when FLOW is 0 */
	buf->Dma[1].CONFIG.b_FLOW = 0;	/* stop */

	return buf;
}

#if defined(CONFIG_POST) && defined(CONFIG_SYS_POST_ETHER)
int ether_post_test(int flags)
{
	uchar buf[64];
	int i, value = 0;
	int length;

	printf("\n--------");
	bfin_EMAC_init(NULL, NULL);
	/* construct the package */
	buf[0] = buf[6] = (unsigned char)(*pEMAC_ADDRLO & 0xFF);
	buf[1] = buf[7] = (unsigned char)((*pEMAC_ADDRLO & 0xFF00) >> 8);
	buf[2] = buf[8] = (unsigned char)((*pEMAC_ADDRLO & 0xFF0000) >> 16);
	buf[3] = buf[9] = (unsigned char)((*pEMAC_ADDRLO & 0xFF000000) >> 24);
	buf[4] = buf[10] = (unsigned char)(*pEMAC_ADDRHI & 0xFF);
	buf[5] = buf[11] = (unsigned char)((*pEMAC_ADDRHI & 0xFF00) >> 8);
	buf[12] = 0x08;		/* Type: ARP */
	buf[13] = 0x06;
	buf[14] = 0x00;		/* Hardware type: Ethernet */
	buf[15] = 0x01;
	buf[16] = 0x08;		/* Protocal type: IP */
	buf[17] = 0x00;
	buf[18] = 0x06;		/* Hardware size    */
	buf[19] = 0x04;		/* Protocol size    */
	buf[20] = 0x00;		/* Opcode: request  */
	buf[21] = 0x01;

	for (i = 0; i < 42; i++)
		buf[i + 22] = i;
	printf("--------Send 64 bytes......\n");
	bfin_EMAC_send(NULL, (volatile void *)buf, 64);
	for (i = 0; i < 100; i++) {
		udelay(10000);
		if ((rxbuf[rxIdx]->StatusWord & RX_COMP) != 0) {
			value = 1;
			break;
		}
	}
	if (value == 0) {
		printf("--------EMAC can't receive any data\n");
		eth_halt();
		return -1;
	}
	length = rxbuf[rxIdx]->StatusWord & 0x000007FF - 4;
	for (i = 0; i < length; i++) {
		if (rxbuf[rxIdx]->FrmData->Dest[i] != buf[i]) {
			printf("--------EMAC receive error data!\n");
			eth_halt();
			return -1;
		}
	}
	printf("--------receive %d bytes, matched\n", length);
	bfin_EMAC_halt(NULL);
	return 0;
}
#endif
Commit	Line	Data
26bf7dec	1	/*
395bce4f	2	* Driver for Blackfin On-Chip MAC device
26bf7dec	3	*
395bce4f	4	* Copyright (c) 2005-2008 Analog Device, Inc.
26bf7dec	5	*
395bce4f	6	* Licensed under the GPL-2 or later.
26bf7dec AL	7	*/
	8
	9	#include <common.h>
	10	#include <config.h>
26bf7dec	11	#include <net.h>
89973f8a	12	#include <netdev.h>
26bf7dec AL	13	#include <command.h>
26bf7dec AL	14	#include <malloc.h>
ac45af4e MF	15	#include <miiphy.h>
ac45af4e MF	16	#include <linux/mii.h>
26bf7dec	17
395bce4f	18	#include <asm/blackfin.h>
d4d77308 MF	19	#include <asm/mach-common/bits/dma.h>
	20	#include <asm/mach-common/bits/emac.h>
	21	#include <asm/mach-common/bits/pll.h>
	22
395bce4f MF	23	#include "bfin_mac.h"
395bce4f MF	24
a7ec6ac8 MF	25	#ifndef CONFIG_PHY_ADDR
	26	# define CONFIG_PHY_ADDR 1
	27	#endif
	28	#ifndef CONFIG_PHY_CLOCK_FREQ
	29	# define CONFIG_PHY_CLOCK_FREQ 2500000
	30	#endif
	31
26bf7dec AL	32	#ifdef CONFIG_POST
	33	#include <post.h>
	34	#endif
	35
26bf7dec AL	36	#define RXBUF_BASE_ADDR 0xFF900000
	37	#define TXBUF_BASE_ADDR 0xFF800000
	38	#define TX_BUF_CNT 1
	39
53677ef1	40	#define TOUT_LOOP 1000000
26bf7dec AL	41
	42	ADI_ETHER_BUFFER *txbuf[TX_BUF_CNT];
	43	ADI_ETHER_BUFFER *rxbuf[PKTBUFSRX];
	44	static u16 txIdx; /* index of the current RX buffer */
	45	static u16 rxIdx; /* index of the current TX buffer */
	46
26bf7dec	47	/* DMAx_CONFIG values at DMA Restart */
395bce4f MF	48	const ADI_DMA_CONFIG_REG rxdmacfg = {
	49	.b_DMA_EN = 1, /* enabled */
	50	.b_WNR = 1, /* write to memory */
	51	.b_WDSIZE = 2, /* wordsize is 32 bits */
	52	.b_DMA2D = 0,
	53	.b_RESTART = 0,
	54	.b_DI_SEL = 0,
	55	.b_DI_EN = 0, /* no interrupt */
	56	.b_NDSIZE = 5, /* 5 half words is desc size */
	57	.b_FLOW = 7 /* large desc flow */
	58	};
	59
	60	const ADI_DMA_CONFIG_REG txdmacfg = {
	61	.b_DMA_EN = 1, /* enabled */
	62	.b_WNR = 0, /* read from memory */
	63	.b_WDSIZE = 2, /* wordsize is 32 bits */
	64	.b_DMA2D = 0,
	65	.b_RESTART = 0,
	66	.b_DI_SEL = 0,
	67	.b_DI_EN = 0, /* no interrupt */
	68	.b_NDSIZE = 5, /* 5 half words is desc size */
	69	.b_FLOW = 7 /* large desc flow */
	70	};
	71
ac45af4e MF	72	static int bfin_miiphy_wait(void)
	73	{
	74	/* poll the STABUSY bit */
	75	while (bfin_read_EMAC_STAADD() & STABUSY)
	76	continue;
	77	return 0;
	78	}
	79
	80	static int bfin_miiphy_read(char devname, uchar addr, uchar reg, ushort val)
	81	{
	82	if (bfin_miiphy_wait())
	83	return 1;
	84	bfin_write_EMAC_STAADD(SET_PHYAD(addr) \| SET_REGAD(reg) \| STABUSY);
	85	if (bfin_miiphy_wait())
	86	return 1;
	87	*val = bfin_read_EMAC_STADAT();
	88	return 0;
	89	}
	90
	91	static int bfin_miiphy_write(char *devname, uchar addr, uchar reg, ushort val)
	92	{
	93	if (bfin_miiphy_wait())
	94	return 1;
	95	bfin_write_EMAC_STADAT(val);
	96	bfin_write_EMAC_STAADD(SET_PHYAD(addr) \| SET_REGAD(reg) \| STAOP \| STABUSY);
	97	return 0;
	98	}
	99
395bce4f	100	int bfin_EMAC_initialize(bd_t *bis)
26bf7dec AL	101	{
26bf7dec AL	102	struct eth_device *dev;
ac45af4e	103	dev = malloc(sizeof(*dev));
26bf7dec AL	104	if (dev == NULL)
	105	hang();
	106
	107	memset(dev, 0, sizeof(*dev));
395bce4f	108	sprintf(dev->name, "Blackfin EMAC");
26bf7dec AL	109
	110	dev->iobase = 0;
	111	dev->priv = 0;
	112	dev->init = bfin_EMAC_init;
	113	dev->halt = bfin_EMAC_halt;
	114	dev->send = bfin_EMAC_send;
	115	dev->recv = bfin_EMAC_recv;
	116
	117	eth_register(dev);
	118
ac45af4e MF	119	#if defined(CONFIG_MII) \|\| defined(CONFIG_CMD_MII)
	120	miiphy_register(dev->name, bfin_miiphy_read, bfin_miiphy_write);
	121	#endif
	122
91494731	123	return 0;
26bf7dec AL	124	}
	125
	126	static int bfin_EMAC_send(struct eth_device dev, volatile void packet,
	127	int length)
	128	{
	129	int i;
	130	int result = 0;
	131	unsigned int *buf;
	132	buf = (unsigned int *)packet;
	133
	134	if (length <= 0) {
	135	printf("Ethernet: bad packet size: %d\n", length);
	136	goto out;
	137	}
	138
	139	if ((*pDMA2_IRQ_STATUS & DMA_ERR) != 0) {
	140	printf("Ethernet: tx DMA error\n");
	141	goto out;
	142	}
	143
	144	for (i = 0; (*pDMA2_IRQ_STATUS & DMA_RUN) != 0; i++) {
	145	if (i > TOUT_LOOP) {
	146	puts("Ethernet: tx time out\n");
	147	goto out;
	148	}
	149	}
	150	txbuf[txIdx]->FrmData->NoBytes = length;
	151	memcpy(txbuf[txIdx]->FrmData->Dest, (void *)packet, length);
	152	txbuf[txIdx]->Dma[0].START_ADDR = (u32) txbuf[txIdx]->FrmData;
	153	*pDMA2_NEXT_DESC_PTR = &txbuf[txIdx]->Dma[0];
	154	pDMA2_CONFIG = (u16 ) (void )(&txdmacfg);
	155	*pEMAC_OPMODE \|= TE;
	156
	157	for (i = 0; (txbuf[txIdx]->StatusWord & TX_COMP) == 0; i++) {
	158	if (i > TOUT_LOOP) {
	159	puts("Ethernet: tx error\n");
	160	goto out;
	161	}
	162	}
	163	result = txbuf[txIdx]->StatusWord;
	164	txbuf[txIdx]->StatusWord = 0;
	165	if ((txIdx + 1) >= TX_BUF_CNT)
	166	txIdx = 0;
	167	else
	168	txIdx++;
395bce4f	169	out:
8eed6ca5	170	debug("BFIN EMAC send: length = %d\n", length);
26bf7dec AL	171	return result;
	172	}
	173
	174	static int bfin_EMAC_recv(struct eth_device *dev)
	175	{
	176	int length = 0;
	177
	178	for (;;) {
	179	if ((rxbuf[rxIdx]->StatusWord & RX_COMP) == 0) {
	180	length = -1;
	181	break;
	182	}
	183	if ((rxbuf[rxIdx]->StatusWord & RX_DMAO) != 0) {
	184	printf("Ethernet: rx dma overrun\n");
	185	break;
	186	}
	187	if ((rxbuf[rxIdx]->StatusWord & RX_OK) == 0) {
	188	printf("Ethernet: rx error\n");
	189	break;
	190	}
	191	length = rxbuf[rxIdx]->StatusWord & 0x000007FF;
	192	if (length <= 4) {
	193	printf("Ethernet: bad frame\n");
	194	break;
	195	}
	196	NetRxPackets[rxIdx] =
	197	(volatile uchar *)(rxbuf[rxIdx]->FrmData->Dest);
	198	NetReceive(NetRxPackets[rxIdx], length - 4);
	199	*pDMA1_IRQ_STATUS \|= DMA_DONE \| DMA_ERR;
	200	rxbuf[rxIdx]->StatusWord = 0x00000000;
	201	if ((rxIdx + 1) >= PKTBUFSRX)
	202	rxIdx = 0;
	203	else
	204	rxIdx++;
	205	}
	206
	207	return length;
	208	}
	209
	210	/**************************************************************
	211	*
	212	* Ethernet Initialization Routine
	213	*
	214	*************************************************************/
	215
ac45af4e MF	216	/* MDC = SCLK / MDC_freq / 2 - 1 */
	217	#define MDC_FREQ_TO_DIV(mdc_freq) (get_sclk() / (mdc_freq) / 2 - 1)
	218
	219	static int bfin_miiphy_init(struct eth_device dev, int opmode)
	220	{
	221	u16 phydat;
	222	size_t count;
	223
	224	/* Enable PHY output */
	225	*pVR_CTL \|= CLKBUFOE;
	226
	227	/* Set all the pins to peripheral mode */
	228	#ifdef CONFIG_BFIN_MAC_RMII
	229	/* grab RMII pins */
	230	# if defined(__ADSPBF51x__)
	231	pPORTF_MUX = (pPORTF_MUX & \
	232	~(PORT_x_MUX_3_MASK \| PORT_x_MUX_4_MASK \| PORT_x_MUX_5_MASK)) \| \
	233	PORT_x_MUX_3_FUNC_1 \| PORT_x_MUX_4_FUNC_1 \| PORT_x_MUX_5_FUNC_1;
	234	*pPORTF_FER \|= PF8 \| PF9 \| PF10 \| PF11 \| PF12 \| PF13 \| PF14 \| PF15;
	235	pPORTG_MUX = (pPORTG_MUX & ~PORT_x_MUX_0_MASK) \| PORT_x_MUX_0_FUNC_1;
	236	*pPORTG_FER \|= PG0 \| PG1 \| PG2;
	237	# elif defined(__ADSPBF52x__)
	238	pPORTG_MUX = (pPORTG_MUX & ~PORT_x_MUX_6_MASK) \| PORT_x_MUX_6_FUNC_2;
	239	*pPORTG_FER \|= PG14 \| PG15;
	240	pPORTH_MUX = (pPORTH_MUX & ~(PORT_x_MUX_0_MASK \| PORT_x_MUX_1_MASK)) \| \
	241	PORT_x_MUX_0_FUNC_2 \| PORT_x_MUX_1_FUNC_2;
	242	*pPORTH_FER \|= PH0 \| PH1 \| PH2 \| PH3 \| PH4 \| PH5 \| PH6 \| PH7 \| PH8;
	243	# else
	244	*pPORTH_FER \|= PH0 \| PH1 \| PH4 \| PH5 \| PH6 \| PH8 \| PH9 \| PH14 \| PH15;
	245	# endif
	246	#else
	247	/* grab MII & RMII pins */
	248	# if defined(__ADSPBF51x__)
	249	pPORTF_MUX = (pPORTF_MUX & \
	250	~(PORT_x_MUX_0_MASK \| PORT_x_MUX_1_MASK \| PORT_x_MUX_3_MASK \| PORT_x_MUX_4_MASK \| PORT_x_MUX_5_MASK)) \| \
	251	PORT_x_MUX_0_FUNC_1 \| PORT_x_MUX_1_FUNC_1 \| PORT_x_MUX_3_FUNC_1 \| PORT_x_MUX_4_FUNC_1 \| PORT_x_MUX_5_FUNC_1;
	252	*pPORTF_FER \|= PF0 \| PF1 \| PF2 \| PF3 \| PF4 \| PF5 \| PF6 \| PF8 \| PF9 \| PF10 \| PF11 \| PF12 \| PF13 \| PF14 \| PF15;
	253	pPORTG_MUX = (pPORTG_MUX & ~PORT_x_MUX_0_MASK) \| PORT_x_MUX_0_FUNC_1;
	254	*pPORTG_FER \|= PG0 \| PG1 \| PG2;
	255	# elif defined(__ADSPBF52x__)
	256	pPORTG_MUX = (pPORTG_MUX & ~PORT_x_MUX_6_MASK) \| PORT_x_MUX_6_FUNC_2;
	257	*pPORTG_FER \|= PG14 \| PG15;
	258	*pPORTH_MUX = PORT_x_MUX_0_FUNC_2 \| PORT_x_MUX_1_FUNC_2 \| PORT_x_MUX_2_FUNC_2;
	259	pPORTH_FER = -1; / all pins */
	260	# else
	261	pPORTH_FER = -1; / all pins */
	262	# endif
	263	#endif
	264
	265	/* Odd word alignment for Receive Frame DMA word */
	266	/* Configure checksum support and rcve frame word alignment */
a7ec6ac8	267	bfin_write_EMAC_SYSCTL(RXDWA \| RXCKS \| SET_MDCDIV(MDC_FREQ_TO_DIV(CONFIG_PHY_CLOCK_FREQ)));
ac45af4e MF	268
ac45af4e MF	269	/* turn on auto-negotiation and wait for link to come up */
a7ec6ac8	270	bfin_miiphy_write(dev->name, CONFIG_PHY_ADDR, MII_BMCR, BMCR_ANENABLE);
ac45af4e MF	271	count = 0;
	272	while (1) {
	273	++count;
a7ec6ac8	274	if (bfin_miiphy_read(dev->name, CONFIG_PHY_ADDR, MII_BMSR, &phydat))
ac45af4e MF	275	return -1;
	276	if (phydat & BMSR_LSTATUS)
	277	break;
	278	if (count > 30000) {
	279	printf("%s: link down, check cable\n", dev->name);
	280	return -1;
	281	}
	282	udelay(100);
	283	}
	284
	285	/* see what kind of link we have */
a7ec6ac8	286	if (bfin_miiphy_read(dev->name, CONFIG_PHY_ADDR, MII_LPA, &phydat))
ac45af4e MF	287	return -1;
	288	if (phydat & LPA_DUPLEX)
	289	*opmode = FDMODE;
	290	else
	291	*opmode = 0;
	292
	293	bfin_write_EMAC_MMC_CTL(RSTC \| CROLL);
	294
	295	/* Initialize the TX DMA channel registers */
	296	*pDMA2_X_COUNT = 0;
	297	*pDMA2_X_MODIFY = 4;
	298	*pDMA2_Y_COUNT = 0;
	299	*pDMA2_Y_MODIFY = 0;
	300
	301	/* Initialize the RX DMA channel registers */
	302	*pDMA1_X_COUNT = 0;
	303	*pDMA1_X_MODIFY = 4;
	304	*pDMA1_Y_COUNT = 0;
	305	*pDMA1_Y_MODIFY = 0;
	306
	307	return 0;
	308	}
	309
395bce4f	310	static int bfin_EMAC_init(struct eth_device dev, bd_t bd)
26bf7dec AL	311	{
	312	u32 opmode;
	313	int dat;
	314	int i;
8eed6ca5	315	debug("Eth_init: ......\n");
26bf7dec AL	316
	317	txIdx = 0;
	318	rxIdx = 0;
	319
ac45af4e MF	320	/* Initialize System Register */
ac45af4e MF	321	if (bfin_miiphy_init(dev, &dat) < 0)
26bf7dec AL	322	return -1;
26bf7dec AL	323
ac45af4e	324	/* Initialize EMAC address */
395bce4f	325	bfin_EMAC_setup_addr(bd);
26bf7dec	326
ac45af4e	327	/* Initialize TX and RX buffer */
26bf7dec AL	328	for (i = 0; i < PKTBUFSRX; i++) {
	329	rxbuf[i] = SetupRxBuffer(i);
	330	if (i > 0) {
	331	rxbuf[i - 1]->Dma[1].NEXT_DESC_PTR =
	332	&(rxbuf[i]->Dma[0]);
	333	if (i == (PKTBUFSRX - 1))
	334	rxbuf[i]->Dma[1].NEXT_DESC_PTR =
	335	&(rxbuf[0]->Dma[0]);
	336	}
	337	}
	338	for (i = 0; i < TX_BUF_CNT; i++) {
	339	txbuf[i] = SetupTxBuffer(i);
	340	if (i > 0) {
	341	txbuf[i - 1]->Dma[1].NEXT_DESC_PTR =
	342	&(txbuf[i]->Dma[0]);
	343	if (i == (TX_BUF_CNT - 1))
	344	txbuf[i]->Dma[1].NEXT_DESC_PTR =
	345	&(txbuf[0]->Dma[0]);
	346	}
	347	}
	348
	349	/* Set RX DMA */
	350	*pDMA1_NEXT_DESC_PTR = &rxbuf[0]->Dma[0];
	351	pDMA1_CONFIG = ((u16 ) (void )&rxbuf[0]->Dma[0].CONFIG);
	352
	353	/* Wait MII done */
ac45af4e	354	bfin_miiphy_wait();
26bf7dec AL	355
	356	/* We enable only RX here */
	357	/* ASTP : Enable Automatic Pad Stripping
	358	PR : Promiscuous Mode for test
	359	PSF : Receive frames with total length less than 64 bytes.
	360	FDMODE : Full Duplex Mode
	361	LB : Internal Loopback for test
	362	RE : Receiver Enable */
	363	if (dat == FDMODE)
	364	opmode = ASTP \| FDMODE \| PSF;
	365	else
	366	opmode = ASTP \| PSF;
	367	opmode \|= RE;
	368	#ifdef CONFIG_BFIN_MAC_RMII
	369	opmode \|= TE \| RMII;
	370	#endif
	371	/* Turn on the EMAC */
	372	*pEMAC_OPMODE = opmode;
	373	return 0;
	374	}
	375
	376	static void bfin_EMAC_halt(struct eth_device *dev)
	377	{
8eed6ca5	378	debug("Eth_halt: ......\n");
26bf7dec AL	379	/* Turn off the EMAC */
	380	*pEMAC_OPMODE = 0x00000000;
	381	/* Turn off the EMAC RX DMA */
	382	*pDMA1_CONFIG = 0x0000;
	383	*pDMA2_CONFIG = 0x0000;
	384
	385	}
	386
395bce4f	387	void bfin_EMAC_setup_addr(bd_t *bd)
26bf7dec	388	{
395bce4f MF	389	*pEMAC_ADDRLO =
	390	bd->bi_enetaddr[0] \|
	391	bd->bi_enetaddr[1] << 8 \|
	392	bd->bi_enetaddr[2] << 16 \|
	393	bd->bi_enetaddr[3] << 24;
	394	*pEMAC_ADDRHI =
	395	bd->bi_enetaddr[4] \|
	396	bd->bi_enetaddr[5] << 8;
26bf7dec AL	397	}
26bf7dec AL	398
26bf7dec AL	399	ADI_ETHER_BUFFER *SetupRxBuffer(int no)
	400	{
	401	ADI_ETHER_FRAME_BUFFER *frmbuf;
	402	ADI_ETHER_BUFFER *buf;
	403	int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2; /* ensure a multi. of 4 */
	404	int total_size = nobytes_buffer + RECV_BUFSIZE;
	405
	406	buf = (ADI_ETHER_BUFFER ) (RXBUF_BASE_ADDR + no total_size);
	407	frmbuf =
	408	(ADI_ETHER_FRAME_BUFFER ) (RXBUF_BASE_ADDR + no total_size +
	409	nobytes_buffer);
	410
	411	memset(buf, 0x00, nobytes_buffer);
	412	buf->FrmData = frmbuf;
	413	memset(frmbuf, 0xfe, RECV_BUFSIZE);
	414
	415	/* set up first desc to point to receive frame buffer */
	416	buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
	417	buf->Dma[0].START_ADDR = (u32) buf->FrmData;
	418	buf->Dma[0].CONFIG.b_DMA_EN = 1; /* enabled */
	419	buf->Dma[0].CONFIG.b_WNR = 1; /* Write to memory */
	420	buf->Dma[0].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
	421	buf->Dma[0].CONFIG.b_NDSIZE = 5; /* 5 half words is desc size. */
	422	buf->Dma[0].CONFIG.b_FLOW = 7; /* large desc flow */
	423
	424	/* set up second desc to point to status word */
	425	buf->Dma[1].NEXT_DESC_PTR = &(buf->Dma[0]);
	426	buf->Dma[1].START_ADDR = (u32) & buf->IPHdrChksum;
	427	buf->Dma[1].CONFIG.b_DMA_EN = 1; /* enabled */
	428	buf->Dma[1].CONFIG.b_WNR = 1; /* Write to memory */
	429	buf->Dma[1].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
	430	buf->Dma[1].CONFIG.b_DI_EN = 1; /* enable interrupt */
	431	buf->Dma[1].CONFIG.b_NDSIZE = 5; /* must be 0 when FLOW is 0 */
	432	buf->Dma[1].CONFIG.b_FLOW = 7; /* stop */
	433
	434	return buf;
	435	}
	436
	437	ADI_ETHER_BUFFER *SetupTxBuffer(int no)
	438	{
	439	ADI_ETHER_FRAME_BUFFER *frmbuf;
	440	ADI_ETHER_BUFFER *buf;
	441	int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2; /* ensure a multi. of 4 */
	442	int total_size = nobytes_buffer + RECV_BUFSIZE;
	443
	444	buf = (ADI_ETHER_BUFFER ) (TXBUF_BASE_ADDR + no total_size);
	445	frmbuf =
	446	(ADI_ETHER_FRAME_BUFFER ) (TXBUF_BASE_ADDR + no total_size +
	447	nobytes_buffer);
	448
	449	memset(buf, 0x00, nobytes_buffer);
	450	buf->FrmData = frmbuf;
	451	memset(frmbuf, 0x00, RECV_BUFSIZE);
	452
	453	/* set up first desc to point to receive frame buffer */
	454	buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
	455	buf->Dma[0].START_ADDR = (u32) buf->FrmData;
	456	buf->Dma[0].CONFIG.b_DMA_EN = 1; /* enabled */
	457	buf->Dma[0].CONFIG.b_WNR = 0; /* Read to memory */
	458	buf->Dma[0].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
	459	buf->Dma[0].CONFIG.b_NDSIZE = 5; /* 5 half words is desc size. */
	460	buf->Dma[0].CONFIG.b_FLOW = 7; /* large desc flow */
	461
	462	/* set up second desc to point to status word */
463	buf->Dma[1].NEXT_DESC_PTR = &(buf->Dma[0]);
464	buf->Dma[1].START_ADDR = (u32) & buf->StatusWord;
465	buf->Dma[1].CONFIG.b_DMA_EN = 1; /* enabled */
466	buf->Dma[1].CONFIG.b_WNR = 1; /* Write to memory */
467	buf->Dma[1].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
468	buf->Dma[1].CONFIG.b_DI_EN = 1; /* enable interrupt */
469	buf->Dma[1].CONFIG.b_NDSIZE = 0; /* must be 0 when FLOW is 0 */
470	buf->Dma[1].CONFIG.b_FLOW = 0; /* stop */
471
472	return buf;
473	}
474
6d0f6bcf	475	#if defined(CONFIG_POST) && defined(CONFIG_SYS_POST_ETHER)
26bf7dec AL	476	int ether_post_test(int flags)
	477	{
	478	uchar buf[64];
	479	int i, value = 0;
	480	int length;
	481
	482	printf("\n--------");
	483	bfin_EMAC_init(NULL, NULL);
	484	/* construct the package */
	485	buf[0] = buf[6] = (unsigned char)(*pEMAC_ADDRLO & 0xFF);
	486	buf[1] = buf[7] = (unsigned char)((*pEMAC_ADDRLO & 0xFF00) >> 8);
	487	buf[2] = buf[8] = (unsigned char)((*pEMAC_ADDRLO & 0xFF0000) >> 16);
	488	buf[3] = buf[9] = (unsigned char)((*pEMAC_ADDRLO & 0xFF000000) >> 24);
	489	buf[4] = buf[10] = (unsigned char)(*pEMAC_ADDRHI & 0xFF);
	490	buf[5] = buf[11] = (unsigned char)((*pEMAC_ADDRHI & 0xFF00) >> 8);
	491	buf[12] = 0x08; /* Type: ARP */
	492	buf[13] = 0x06;
	493	buf[14] = 0x00; /* Hardware type: Ethernet */
	494	buf[15] = 0x01;
	495	buf[16] = 0x08; /* Protocal type: IP */
	496	buf[17] = 0x00;
	497	buf[18] = 0x06; /* Hardware size */
	498	buf[19] = 0x04; /* Protocol size */
	499	buf[20] = 0x00; /* Opcode: request */
	500	buf[21] = 0x01;
	501
	502	for (i = 0; i < 42; i++)
	503	buf[i + 22] = i;
	504	printf("--------Send 64 bytes......\n");
	505	bfin_EMAC_send(NULL, (volatile void *)buf, 64);
	506	for (i = 0; i < 100; i++) {
	507	udelay(10000);
	508	if ((rxbuf[rxIdx]->StatusWord & RX_COMP) != 0) {
	509	value = 1;
	510	break;
	511	}
	512	}
	513	if (value == 0) {
	514	printf("--------EMAC can't receive any data\n");
	515	eth_halt();
	516	return -1;
	517	}
	518	length = rxbuf[rxIdx]->StatusWord & 0x000007FF - 4;
	519	for (i = 0; i < length; i++) {
	520	if (rxbuf[rxIdx]->FrmData->Dest[i] != buf[i]) {
	521	printf("--------EMAC receive error data!\n");
	522	eth_halt();
	523	return -1;
	524	}
	525	}
	526	printf("--------receive %d bytes, matched\n", length);
	527	bfin_EMAC_halt(NULL);
	528	return 0;
	529	}
	530	#endif