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warp7: Set u-boot serial# based on OTP value
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ed09a554 1/*
2 * (C) Copyright 2015
66562414 3 * Kamil Lulko, <[email protected]>
ed09a554 4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
089fddfd 11#define CONFIG_MISC_INIT_R
ed09a554 12
13#define CONFIG_SYS_FLASH_BASE 0x08000000
14
15#define CONFIG_SYS_INIT_SP_ADDR 0x10010000
ed09a554 16
17#define CONFIG_SYS_ICACHE_OFF
18#define CONFIG_SYS_DCACHE_OFF
19
20/*
21 * Configuration of the external SDRAM memory
22 */
23#define CONFIG_NR_DRAM_BANKS 1
ed09a554 24#define CONFIG_SYS_RAM_CS 1
25#define CONFIG_SYS_RAM_FREQ_DIV 2
26#define CONFIG_SYS_RAM_BASE 0xD0000000
27#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_RAM_BASE
28#define CONFIG_SYS_LOAD_ADDR 0xD0400000
29#define CONFIG_LOADADDR 0xD0400000
30
31#define CONFIG_SYS_MAX_FLASH_SECT 12
32#define CONFIG_SYS_MAX_FLASH_BANKS 2
33
ed09a554 34#define CONFIG_ENV_OFFSET (256 << 10)
35#define CONFIG_ENV_SECT_SIZE (128 << 10)
36#define CONFIG_ENV_SIZE (8 << 10)
37
ed09a554 38#define CONFIG_RED_LED 110
39#define CONFIG_GREEN_LED 109
40
9ecb0c41 41#define CONFIG_STM32_FLASH
ed09a554 42
f9fa4a25
AB
43#define CONFIG_SYS_CLK_FREQ 180000000 /* 180 MHz */
44
ed09a554 45#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */
46
47#define CONFIG_CMDLINE_TAG
48#define CONFIG_SETUP_MEMORY_TAGS
49#define CONFIG_INITRD_TAG
50#define CONFIG_REVISION_TAG
51
52#define CONFIG_SYS_CBSIZE 1024
ed09a554 53
ed09a554 54#define CONFIG_SYS_MALLOC_LEN (2 << 20)
55
ed09a554 56#define CONFIG_BOOTCOMMAND \
57 "run bootcmd_romfs"
58
59#define CONFIG_EXTRA_ENV_SETTINGS \
60 "bootargs_romfs=uclinux.physaddr=0x08180000 root=/dev/mtdblock0\0" \
61 "bootcmd_romfs=setenv bootargs ${bootargs} ${bootargs_romfs};" \
62 "bootm 0x08044000 - 0x08042000\0"
63
ed09a554 64/*
65 * Command line configuration.
66 */
ed09a554 67
ed09a554 68#endif /* __CONFIG_H */
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