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Commit | Line | Data |
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ed09a554 | 1 | /* |
2 | * (C) Copyright 2015 | |
3 | * Kamil Lulko, <[email protected]> | |
4 | * | |
5 | * SPDX-License-Identifier: GPL-2.0+ | |
6 | */ | |
7 | ||
8 | #ifndef __CONFIG_H | |
9 | #define __CONFIG_H | |
10 | ||
11 | #define CONFIG_STM32F4 | |
bf104ffa | 12 | #define CONFIG_SYS_THUMB_BUILD |
ed09a554 | 13 | #define CONFIG_STM32F4DISCOVERY |
ed09a554 | 14 | |
15 | #define CONFIG_OF_LIBFDT | |
16 | ||
17 | #define CONFIG_BOARD_EARLY_INIT_F | |
089fddfd | 18 | #define CONFIG_MISC_INIT_R |
ed09a554 | 19 | |
20 | #define CONFIG_SYS_FLASH_BASE 0x08000000 | |
21 | ||
22 | #define CONFIG_SYS_INIT_SP_ADDR 0x10010000 | |
23 | #define CONFIG_SYS_TEXT_BASE 0x08000000 | |
24 | ||
25 | #define CONFIG_SYS_ICACHE_OFF | |
26 | #define CONFIG_SYS_DCACHE_OFF | |
27 | ||
28 | /* | |
29 | * Configuration of the external SDRAM memory | |
30 | */ | |
31 | #define CONFIG_NR_DRAM_BANKS 1 | |
32 | #define CONFIG_SYS_RAM_SIZE (8 << 20) | |
33 | #define CONFIG_SYS_RAM_CS 1 | |
34 | #define CONFIG_SYS_RAM_FREQ_DIV 2 | |
35 | #define CONFIG_SYS_RAM_BASE 0xD0000000 | |
36 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_RAM_BASE | |
37 | #define CONFIG_SYS_LOAD_ADDR 0xD0400000 | |
38 | #define CONFIG_LOADADDR 0xD0400000 | |
39 | ||
40 | #define CONFIG_SYS_MAX_FLASH_SECT 12 | |
41 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 | |
42 | ||
43 | #define CONFIG_ENV_IS_IN_FLASH | |
44 | #define CONFIG_ENV_OFFSET (256 << 10) | |
45 | #define CONFIG_ENV_SECT_SIZE (128 << 10) | |
46 | #define CONFIG_ENV_SIZE (8 << 10) | |
47 | ||
48 | #define CONFIG_BOARD_SPECIFIC_LED | |
49 | #define CONFIG_RED_LED 110 | |
50 | #define CONFIG_GREEN_LED 109 | |
51 | ||
52 | #define CONFIG_STM32_GPIO | |
53 | #define CONFIG_STM32_SERIAL | |
60570df1 | 54 | /* |
55 | * Configuration of the USART | |
6f921ecc | 56 | * 1: TX:PA9 RX:PA10 |
60570df1 | 57 | * 2: TX:PD5 RX:PD6 |
58 | * 3: TX:PC10 RX:PC11 | |
03514739 | 59 | * 6: TX:PG14 RX:PG9 |
60570df1 | 60 | */ |
61 | #define CONFIG_STM32_USART 1 | |
ed09a554 | 62 | |
63 | #define CONFIG_STM32_HSE_HZ 8000000 | |
64 | ||
f9fa4a25 AB |
65 | #define CONFIG_SYS_CLK_FREQ 180000000 /* 180 MHz */ |
66 | ||
ed09a554 | 67 | #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ |
68 | ||
69 | #define CONFIG_CMDLINE_TAG | |
70 | #define CONFIG_SETUP_MEMORY_TAGS | |
71 | #define CONFIG_INITRD_TAG | |
72 | #define CONFIG_REVISION_TAG | |
73 | ||
74 | #define CONFIG_SYS_CBSIZE 1024 | |
75 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ | |
76 | + sizeof(CONFIG_SYS_PROMPT) + 16) | |
77 | ||
78 | #define CONFIG_SYS_MAXARGS 16 | |
79 | ||
80 | #define CONFIG_SYS_MALLOC_LEN (2 << 20) | |
81 | ||
82 | #define CONFIG_STACKSIZE (64 << 10) | |
83 | ||
84 | #define CONFIG_BAUDRATE 115200 | |
85 | #define CONFIG_BOOTARGS \ | |
6b330568 | 86 | "console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel" |
ed09a554 | 87 | #define CONFIG_BOOTCOMMAND \ |
88 | "run bootcmd_romfs" | |
89 | ||
90 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
91 | "bootargs_romfs=uclinux.physaddr=0x08180000 root=/dev/mtdblock0\0" \ | |
92 | "bootcmd_romfs=setenv bootargs ${bootargs} ${bootargs_romfs};" \ | |
93 | "bootm 0x08044000 - 0x08042000\0" | |
94 | ||
95 | #define CONFIG_BOOTDELAY 3 | |
96 | #define CONFIG_AUTOBOOT | |
97 | ||
98 | /* | |
99 | * Command line configuration. | |
100 | */ | |
ed09a554 | 101 | #define CONFIG_SYS_LONGHELP |
102 | #define CONFIG_SYS_HUSH_PARSER | |
ed09a554 | 103 | #define CONFIG_AUTO_COMPLETE |
104 | #define CONFIG_CMDLINE_EDITING | |
105 | ||
ed09a554 | 106 | #define CONFIG_CMD_MEM |
ed09a554 | 107 | #define CONFIG_CMD_TIMER |
108 | ||
109 | #endif /* __CONFIG_H */ |