[u-boot.git] / include / configs / MPC8555CDS.h

/*
 * Copyright 2004, 2011 Freescale Semiconductor.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * mpc8555cds board configuration file
 *
 * Please refer to doc/README.mpc85xxcds for more info.
 *
 */
#ifndef __CONFIG_H
#define __CONFIG_H

/* High Level Configuration Options */
#define CONFIG_BOOKE		1	/* BOOKE */
#define CONFIG_E500		1	/* BOOKE e500 family */
#define CONFIG_CPM2		1	/* has CPM2 */
#define CONFIG_MPC8555		1	/* MPC8555 specific */
#define CONFIG_MPC8555CDS	1	/* MPC8555CDS board specific */

#define	CONFIG_SYS_TEXT_BASE	0xfff80000

#define CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
#define CONFIG_TSEC_ENET		/* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_FSL_LAW		1	/* Use common FSL init code */

#define CONFIG_FSL_VIA

#ifndef __ASSEMBLY__
extern unsigned long get_clock_freq(void);
#endif
#define CONFIG_SYS_CLK_FREQ	get_clock_freq() /* sysclk for MPC85xx */

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE			    /* toggle L2 cache	*/
#define CONFIG_BTB			    /* toggle branch predition */

#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x00400000

#define CONFIG_SYS_CCSRBAR		0xe0000000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR

/* DDR Setup */
#define CONFIG_SYS_FSL_DDR1
#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
#undef CONFIG_FSL_DDR_INTERACTIVE

#define CONFIG_MEM_INIT_VALUE		0xDeadBeef

#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE

#define CONFIG_NUM_DDR_CONTROLLERS	1
#define CONFIG_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)

/* I2C addresses of SPD EEPROMs */
#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */

/* Make sure required options are set */
#ifndef CONFIG_SPD_EEPROM
#error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
#endif

#undef CONFIG_CLOCKS_IN_MHZ

/*
 * Local Bus Definitions
 */

/*
 * FLASH on the Local Bus
 * Two banks, 8M each, using the CFI driver.
 * Boot from BR0/OR0 bank at 0xff00_0000
 * Alternate BR1/OR1 bank at 0xff80_0000
 *
 * BR0, BR1:
 *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
 *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
 *    Port Size = 16 bits = BRx[19:20] = 10
 *    Use GPCM = BRx[24:26] = 000
 *    Valid = BRx[31] = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001    BR0
 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001    BR1
 *
 * OR0, OR1:
 *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
 *    Reserved ORx[17:18] = 11, confusion here?
 *    CSNT = ORx[20] = 1
 *    ACS = half cycle delay = ORx[21:22] = 11
 *    SCY = 6 = ORx[24:27] = 0110
 *    TRLX = use relaxed timing = ORx[29] = 1
 *    EAD = use external address latch delay = OR[31] = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    ORx
 */

#define CONFIG_SYS_FLASH_BASE		0xff000000	/* start of FLASH 8M */

#define CONFIG_SYS_BR0_PRELIM		0xff801001
#define CONFIG_SYS_BR1_PRELIM		0xff001001

#define	CONFIG_SYS_OR0_PRELIM		0xff806e65
#define	CONFIG_SYS_OR1_PRELIM		0xff806e65

#define CONFIG_SYS_FLASH_BANKS_LIST	{0xff800000, CONFIG_SYS_FLASH_BASE}
#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	128		/* sectors per device */
#undef	CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */

#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO

/*
 * SDRAM on the Local Bus
 */
#define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */

/*
 * Base Register 2 and Option Register 2 configure SDRAM.
 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 *
 * For BR2, need:
 *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 *    port-size = 32-bits = BR2[19:20] = 11
 *    no parity checking = BR2[21:22] = 00
 *    SDRAM for MSEL = BR2[24:26] = 011
 *    Valid = BR[31] = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 *
 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
 * FIXME: the top 17 bits of BR2.
 */

#define CONFIG_SYS_BR2_PRELIM          0xf0001861

/*
 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 *
 * For OR2, need:
 *    64MB mask for AM, OR2[0:7] = 1111 1100
 *		   XAM, OR2[17:18] = 11
 *    9 columns OR2[19-21] = 010
 *    13 rows   OR2[23-25] = 100
 *    EAD set for extra time OR[31] = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 */

#define CONFIG_SYS_OR2_PRELIM		0xfc006901

#define CONFIG_SYS_LBC_LCRR		0x00030004    /* LB clock ratio reg */
#define CONFIG_SYS_LBC_LBCR		0x00000000    /* LB config reg */
#define CONFIG_SYS_LBC_LSRT		0x20000000  /* LB sdram refresh timer */
#define CONFIG_SYS_LBC_MRTPR		0x00000000  /* LB refresh timer prescal*/

/*
 * Common settings for all Local Bus SDRAM commands.
 * At run time, either BSMA1516 (for CPU 1.1)
 *                  or BSMA1617 (for CPU 1.0) (old)
 * is OR'ed in too.
 */
#define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_RFCR16		\
				| LSDMR_PRETOACT7	\
				| LSDMR_ACTTORW7	\
				| LSDMR_BL8		\
				| LSDMR_WRC4		\
				| LSDMR_CL3		\
				| LSDMR_RFEN		\
				)

/*
 * The CADMUS registers are connected to CS3 on CDS.
 * The new memory map places CADMUS at 0xf8000000.
 *
 * For BR3, need:
 *    Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
 *    port-size = 8-bits  = BR[19:20] = 01
 *    no parity checking  = BR[21:22] = 00
 *    GPMC for MSEL       = BR[24:26] = 000
 *    Valid               = BR[31]    = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
 *
 * For OR3, need:
 *    1 MB mask for AM,   OR[0:16]  = 1111 1111 1111 0000 0
 *    disable buffer ctrl OR[19]    = 0
 *    CSNT                OR[20]    = 1
 *    ACS                 OR[21:22] = 11
 *    XACS                OR[23]    = 1
 *    SCY 15 wait states  OR[24:27] = 1111	max is suboptimal but safe
 *    SETA                OR[28]    = 0
 *    TRLX                OR[29]    = 1
 *    EHTR                OR[30]    = 1
 *    EAD extra time      OR[31]    = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
 */

#define CONFIG_FSL_CADMUS

#define CADMUS_BASE_ADDR 0xf8000000
#define CONFIG_SYS_BR3_PRELIM   0xf8000801
#define CONFIG_SYS_OR3_PRELIM   0xfff00ff7

#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE	0x4000	    /* Size of used area in RAM */

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */

/* Serial Port */
#define CONFIG_CONS_INDEX     2
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE    1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE  \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}

#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)

/*
 * I2C
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }

/* EEPROM */
#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_CCID
#define CONFIG_SYS_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2

/*
 * General PCI
 * Addresses are mapped 1-1.
 */
#define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
#define CONFIG_SYS_PCI1_MEM_BUS	0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCI1_IO_VIRT	0xe2000000
#define CONFIG_SYS_PCI1_IO_BUS	0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
#define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */

#define CONFIG_SYS_PCI2_MEM_VIRT	0xa0000000
#define CONFIG_SYS_PCI2_MEM_BUS	0xa0000000
#define CONFIG_SYS_PCI2_MEM_PHYS	0xa0000000
#define CONFIG_SYS_PCI2_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCI2_IO_VIRT	0xe2100000
#define CONFIG_SYS_PCI2_IO_BUS	0x00000000
#define CONFIG_SYS_PCI2_IO_PHYS	0xe2100000
#define CONFIG_SYS_PCI2_IO_SIZE	0x00100000	/* 1M */

#ifdef CONFIG_LEGACY
#define BRIDGE_ID 17
#define VIA_ID 2
#else
#define BRIDGE_ID 28
#define VIA_ID 4
#endif

#if defined(CONFIG_PCI)

#define CONFIG_PCI_PNP			/* do pci plug-and-play */
#define CONFIG_MPC85XX_PCI2

#undef CONFIG_EEPRO100
#undef CONFIG_TULIP

#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */

#endif	/* CONFIG_PCI */

#if defined(CONFIG_TSEC_ENET)

#define CONFIG_MII		1	/* MII PHY management */
#define CONFIG_TSEC1	1
#define CONFIG_TSEC1_NAME	"TSEC0"
#define CONFIG_TSEC2	1
#define CONFIG_TSEC2_NAME	"TSEC1"
#define TSEC1_PHY_ADDR		0
#define TSEC2_PHY_ADDR		1
#define TSEC1_PHYIDX		0
#define TSEC2_PHYIDX		0
#define TSEC1_FLAGS		TSEC_GIGABIT
#define TSEC2_FLAGS		TSEC_GIGABIT

/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME		"TSEC0"

#endif	/* CONFIG_TSEC_ENET */

/*
 * Environment
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
#define CONFIG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
#define CONFIG_ENV_SIZE		0x2000

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_REGINFO

#if defined(CONFIG_PCI)
    #define CONFIG_CMD_PCI
#endif

#undef CONFIG_WATCHDOG			/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 64 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#endif

/*
 * Environment Configuration
 */
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
#endif

#define CONFIG_IPADDR    192.168.1.253

#define CONFIG_HOSTNAME  unknown
#define CONFIG_ROOTPATH  "/nfsroot"
#define CONFIG_BOOTFILE  "your.uImage"

#define CONFIG_SERVERIP  192.168.1.1
#define CONFIG_GATEWAYIP 192.168.1.1
#define CONFIG_NETMASK   255.255.255.0

#define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/

#undef  CONFIG_BOOTARGS           /* the boot command will set bootargs*/

#define CONFIG_BAUDRATE	115200

#define	CONFIG_EXTRA_ENV_SETTINGS				        \
   "netdev=eth0\0"                                                      \
   "consoledev=ttyS1\0"                                                 \
   "ramdiskaddr=600000\0"                                               \
   "ramdiskfile=your.ramdisk.u-boot\0"					\
   "fdtaddr=400000\0"							\
   "fdtfile=your.fdt.dtb\0"

#define CONFIG_NFSBOOTCOMMAND	                                        \
   "setenv bootargs root=/dev/nfs rw "                                  \
      "nfsroot=$serverip:$rootpath "                                    \
      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
      "console=$consoledev,$baudrate $othbootargs;"                     \
   "tftp $loadaddr $bootfile;"                                          \
   "tftp $fdtaddr $fdtfile;"						\
   "bootm $loadaddr - $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND \
   "setenv bootargs root=/dev/ram rw "                                  \
      "console=$consoledev,$baudrate $othbootargs;"                     \
   "tftp $ramdiskaddr $ramdiskfile;"                                    \
   "tftp $loadaddr $bootfile;"                                          \
   "bootm $loadaddr $ramdiskaddr"

#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND

#endif	/* __CONFIG_H */
Commit	Line	Data
03f5c550	1	/*
7c57f3e8	2	* Copyright 2004, 2011 Freescale Semiconductor.
03f5c550	3	*
3765b3e7	4	* SPDX-License-Identifier: GPL-2.0+
03f5c550 WD	5	*/
	6
	7	/*
	8	* mpc8555cds board configuration file
	9	*
	10	* Please refer to doc/README.mpc85xxcds for more info.
	11	*
	12	*/
03f5c550 WD	13	#ifndef __CONFIG_H
	14	#define __CONFIG_H
	15
	16	/* High Level Configuration Options */
	17	#define CONFIG_BOOKE 1 /* BOOKE */
	18	#define CONFIG_E500 1 /* BOOKE e500 family */
9c4c5ae3	19	#define CONFIG_CPM2 1 /* has CPM2 */
03f5c550 WD	20	#define CONFIG_MPC8555 1 /* MPC8555 specific */
	21	#define CONFIG_MPC8555CDS 1 /* MPC8555CDS board specific */
	22
2ae18241 WD	23	#define CONFIG_SYS_TEXT_BASE 0xfff80000
2ae18241 WD	24
03f5c550	25	#define CONFIG_PCI
842033e6	26	#define CONFIG_PCI_INDIRECT_BRIDGE
0151cbac	27	#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
53677ef1	28	#define CONFIG_TSEC_ENET /* tsec ethernet support */
03f5c550	29	#define CONFIG_ENV_OVERWRITE
2cfaa1aa	30	#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
03f5c550	31
25eedb2c	32	#define CONFIG_FSL_VIA
e8d18541	33
03f5c550 WD	34	#ifndef __ASSEMBLY__
	35	extern unsigned long get_clock_freq(void);
	36	#endif
	37	#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
	38
	39	/*
	40	* These can be toggled for performance analysis, otherwise use default.
	41	*/
53677ef1	42	#define CONFIG_L2_CACHE /* toggle L2 cache */
03f5c550	43	#define CONFIG_BTB /* toggle branch predition */
03f5c550	44
6d0f6bcf JCPV	45	#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
6d0f6bcf JCPV	46	#define CONFIG_SYS_MEMTEST_END 0x00400000
03f5c550	47
e46fedfe TT	48	#define CONFIG_SYS_CCSRBAR 0xe0000000
e46fedfe TT	49	#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
03f5c550	50
2b40edb1	51	/* DDR Setup */
5614e71b	52	#define CONFIG_SYS_FSL_DDR1
2b40edb1 JL	53	#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
	54	#define CONFIG_DDR_SPD
	55	#undef CONFIG_FSL_DDR_INTERACTIVE
	56
	57	#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
	58
6d0f6bcf JCPV	59	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
6d0f6bcf JCPV	60	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
03f5c550	61
2b40edb1 JL	62	#define CONFIG_NUM_DDR_CONTROLLERS 1
	63	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
	64	#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
03f5c550	65
2b40edb1 JL	66	/* I2C addresses of SPD EEPROMs */
	67	#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
	68
	69	/* Make sure required options are set */
03f5c550 WD	70	#ifndef CONFIG_SPD_EEPROM
	71	#error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
	72	#endif
	73
7202d43d JL	74	#undef CONFIG_CLOCKS_IN_MHZ
7202d43d JL	75
03f5c550	76	/*
7202d43d	77	* Local Bus Definitions
03f5c550	78	*/
7202d43d JL	79
	80	/*
	81	* FLASH on the Local Bus
	82	* Two banks, 8M each, using the CFI driver.
	83	* Boot from BR0/OR0 bank at 0xff00_0000
	84	* Alternate BR1/OR1 bank at 0xff80_0000
	85	*
	86	* BR0, BR1:
	87	* Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
	88	* Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
	89	* Port Size = 16 bits = BRx[19:20] = 10
	90	* Use GPCM = BRx[24:26] = 000
	91	* Valid = BRx[31] = 1
	92	*
	93	* 0 4 8 12 16 20 24 28
	94	* 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
	95	* 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
	96	*
	97	* OR0, OR1:
	98	* Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
	99	* Reserved ORx[17:18] = 11, confusion here?
	100	* CSNT = ORx[20] = 1
	101	* ACS = half cycle delay = ORx[21:22] = 11
	102	* SCY = 6 = ORx[24:27] = 0110
	103	* TRLX = use relaxed timing = ORx[29] = 1
	104	* EAD = use external address latch delay = OR[31] = 1
	105	*
	106	* 0 4 8 12 16 20 24 28
	107	* 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
	108	*/
	109
6d0f6bcf	110	#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 8M */
03f5c550	111
6d0f6bcf JCPV	112	#define CONFIG_SYS_BR0_PRELIM 0xff801001
6d0f6bcf JCPV	113	#define CONFIG_SYS_BR1_PRELIM 0xff001001
03f5c550	114
6d0f6bcf JCPV	115	#define CONFIG_SYS_OR0_PRELIM 0xff806e65
6d0f6bcf JCPV	116	#define CONFIG_SYS_OR1_PRELIM 0xff806e65
03f5c550	117
6d0f6bcf JCPV	118	#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE}
	119	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
	120	#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
	121	#undef CONFIG_SYS_FLASH_CHECKSUM
	122	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	123	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
03f5c550	124
14d0a02a	125	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
03f5c550	126
00b1883a	127	#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf JCPV	128	#define CONFIG_SYS_FLASH_CFI
6d0f6bcf JCPV	129	#define CONFIG_SYS_FLASH_EMPTY_INFO
03f5c550	130
03f5c550	131	/*
7202d43d	132	* SDRAM on the Local Bus
03f5c550	133	*/
6d0f6bcf JCPV	134	#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
6d0f6bcf JCPV	135	#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
03f5c550 WD	136
	137	/*
	138	* Base Register 2 and Option Register 2 configure SDRAM.
6d0f6bcf	139	* The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
03f5c550 WD	140	*
	141	* For BR2, need:
	142	* Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
	143	* port-size = 32-bits = BR2[19:20] = 11
	144	* no parity checking = BR2[21:22] = 00
	145	* SDRAM for MSEL = BR2[24:26] = 011
	146	* Valid = BR[31] = 1
	147	*
	148	* 0 4 8 12 16 20 24 28
	149	* 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
	150	*
6d0f6bcf	151	* FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
03f5c550 WD	152	* FIXME: the top 17 bits of BR2.
	153	*/
	154
6d0f6bcf	155	#define CONFIG_SYS_BR2_PRELIM 0xf0001861
03f5c550 WD	156
03f5c550 WD	157	/*
6d0f6bcf	158	* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
03f5c550 WD	159	*
	160	* For OR2, need:
	161	* 64MB mask for AM, OR2[0:7] = 1111 1100
	162	* XAM, OR2[17:18] = 11
	163	* 9 columns OR2[19-21] = 010
	164	* 13 rows OR2[23-25] = 100
	165	* EAD set for extra time OR[31] = 1
	166	*
	167	* 0 4 8 12 16 20 24 28
	168	* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
	169	*/
	170
6d0f6bcf	171	#define CONFIG_SYS_OR2_PRELIM 0xfc006901
03f5c550	172
6d0f6bcf JCPV	173	#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
	174	#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
	175	#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
	176	#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
03f5c550	177
03f5c550 WD	178	/*
	179	* Common settings for all Local Bus SDRAM commands.
	180	* At run time, either BSMA1516 (for CPU 1.1)
	181	* or BSMA1617 (for CPU 1.0) (old)
	182	* is OR'ed in too.
	183	*/
b0fe93ed KG	184	#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
	185	\| LSDMR_PRETOACT7 \
	186	\| LSDMR_ACTTORW7 \
	187	\| LSDMR_BL8 \
	188	\| LSDMR_WRC4 \
	189	\| LSDMR_CL3 \
	190	\| LSDMR_RFEN \
03f5c550 WD	191	)
	192
	193	/*
	194	* The CADMUS registers are connected to CS3 on CDS.
	195	* The new memory map places CADMUS at 0xf8000000.
	196	*
	197	* For BR3, need:
	198	* Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
	199	* port-size = 8-bits = BR[19:20] = 01
	200	* no parity checking = BR[21:22] = 00
	201	* GPMC for MSEL = BR[24:26] = 000
	202	* Valid = BR[31] = 1
	203	*
	204	* 0 4 8 12 16 20 24 28
	205	* 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
	206	*
	207	* For OR3, need:
	208	* 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
	209	* disable buffer ctrl OR[19] = 0
	210	* CSNT OR[20] = 1
	211	* ACS OR[21:22] = 11
	212	* XACS OR[23] = 1
	213	* SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
	214	* SETA OR[28] = 0
	215	* TRLX OR[29] = 1
	216	* EHTR OR[30] = 1
	217	* EAD extra time OR[31] = 1
	218	*
	219	* 0 4 8 12 16 20 24 28
	220	* 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
	221	*/
	222
25eedb2c JL	223	#define CONFIG_FSL_CADMUS
25eedb2c JL	224
03f5c550	225	#define CADMUS_BASE_ADDR 0xf8000000
6d0f6bcf JCPV	226	#define CONFIG_SYS_BR3_PRELIM 0xf8000801
6d0f6bcf JCPV	227	#define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
03f5c550	228
6d0f6bcf JCPV	229	#define CONFIG_SYS_INIT_RAM_LOCK 1
6d0f6bcf JCPV	230	#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
553f0982	231	#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
03f5c550	232
25ddd1fb	233	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	234	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
03f5c550	235
6d0f6bcf JCPV	236	#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
6d0f6bcf JCPV	237	#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
03f5c550 WD	238
	239	/* Serial Port */
	240	#define CONFIG_CONS_INDEX 2
6d0f6bcf JCPV	241	#define CONFIG_SYS_NS16550_SERIAL
	242	#define CONFIG_SYS_NS16550_REG_SIZE 1
	243	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
03f5c550	244
6d0f6bcf	245	#define CONFIG_SYS_BAUDRATE_TABLE \
03f5c550 WD	246	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
03f5c550 WD	247
6d0f6bcf JCPV	248	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
6d0f6bcf JCPV	249	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
03f5c550	250
20476726 JL	251	/*
	252	* I2C
	253	*/
00f792e0 HS	254	#define CONFIG_SYS_I2C
	255	#define CONFIG_SYS_I2C_FSL
	256	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	257	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	258	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	259	#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
03f5c550	260
e8d18541 TT	261	/* EEPROM */
e8d18541 TT	262	#define CONFIG_ID_EEPROM
6d0f6bcf JCPV	263	#define CONFIG_SYS_I2C_EEPROM_CCID
	264	#define CONFIG_SYS_ID_EEPROM
	265	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
	266	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
e8d18541	267
03f5c550 WD	268	/*
	269	* General PCI
	270	* Addresses are mapped 1-1.
	271	*/
5af0fdd8	272	#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
10795f42	273	#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
5af0fdd8	274	#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
6d0f6bcf	275	#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
aca5f018	276	#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
5f91ef6a	277	#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
6d0f6bcf JCPV	278	#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
	279	#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
	280
5af0fdd8	281	#define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000
10795f42	282	#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
5af0fdd8	283	#define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000
6d0f6bcf	284	#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
aca5f018	285	#define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000
5f91ef6a	286	#define CONFIG_SYS_PCI2_IO_BUS 0x00000000
6d0f6bcf JCPV	287	#define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000
6d0f6bcf JCPV	288	#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
03f5c550	289
7f3f2bd2 RV	290	#ifdef CONFIG_LEGACY
	291	#define BRIDGE_ID 17
	292	#define VIA_ID 2
	293	#else
	294	#define BRIDGE_ID 28
	295	#define VIA_ID 4
	296	#endif
03f5c550 WD	297
	298	#if defined(CONFIG_PCI)
	299
53677ef1	300	#define CONFIG_PCI_PNP /* do pci plug-and-play */
bf1dfffd	301	#define CONFIG_MPC85XX_PCI2
03f5c550 WD	302
	303	#undef CONFIG_EEPRO100
	304	#undef CONFIG_TULIP
	305
bf1dfffd	306	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
6d0f6bcf	307	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
03f5c550 WD	308
	309	#endif /* CONFIG_PCI */
	310
03f5c550 WD	311	#if defined(CONFIG_TSEC_ENET)
03f5c550 WD	312
03f5c550	313	#define CONFIG_MII 1 /* MII PHY management */
255a3577 KP	314	#define CONFIG_TSEC1 1
	315	#define CONFIG_TSEC1_NAME "TSEC0"
	316	#define CONFIG_TSEC2 1
	317	#define CONFIG_TSEC2_NAME "TSEC1"
03f5c550 WD	318	#define TSEC1_PHY_ADDR 0
03f5c550 WD	319	#define TSEC2_PHY_ADDR 1
03f5c550 WD	320	#define TSEC1_PHYIDX 0
03f5c550 WD	321	#define TSEC2_PHYIDX 0
3a79013e AF	322	#define TSEC1_FLAGS TSEC_GIGABIT
3a79013e AF	323	#define TSEC2_FLAGS TSEC_GIGABIT
d9b94f28 JL	324
	325	/* Options are: TSEC[0-1] */
	326	#define CONFIG_ETHPRIME "TSEC0"
03f5c550 WD	327
	328	#endif /* CONFIG_TSEC_ENET */
	329
03f5c550 WD	330	/*
	331	* Environment
	332	*/
5a1aceb0	333	#define CONFIG_ENV_IS_IN_FLASH 1
6d0f6bcf	334	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
0e8d1586 JCPV	335	#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
0e8d1586 JCPV	336	#define CONFIG_ENV_SIZE 0x2000
03f5c550 WD	337
03f5c550 WD	338	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	339	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
03f5c550	340
659e2f67 JL	341	/*
	342	* BOOTP options
	343	*/
	344	#define CONFIG_BOOTP_BOOTFILESIZE
	345	#define CONFIG_BOOTP_BOOTPATH
	346	#define CONFIG_BOOTP_GATEWAY
	347	#define CONFIG_BOOTP_HOSTNAME
	348
2835e518 JL	349	/*
	350	* Command line configuration.
	351	*/
1c9aa76b	352	#define CONFIG_CMD_IRQ
199e262e	353	#define CONFIG_CMD_REGINFO
2835e518	354
03f5c550	355	#if defined(CONFIG_PCI)
2835e518	356	#define CONFIG_CMD_PCI
03f5c550	357	#endif
2835e518	358
03f5c550 WD	359	#undef CONFIG_WATCHDOG /* watchdog disabled */
	360
	361	/*
	362	* Miscellaneous configurable options
	363	*/
6d0f6bcf	364	#define CONFIG_SYS_LONGHELP /* undef to save memory */
5be58f5f KP	365	#define CONFIG_CMDLINE_EDITING /* Command-line editing */
5be58f5f KP	366	#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
6d0f6bcf	367	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
2835e518	368	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	369	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
03f5c550	370	#else
6d0f6bcf	371	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
03f5c550	372	#endif
6d0f6bcf JCPV	373	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	374	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	375	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
03f5c550 WD	376
	377	/*
	378	* For booting Linux, the board info and command line data
a832ac41	379	* have to be in the first 64 MB of memory, since this is
03f5c550 WD	380	* the maximum mapped by the Linux kernel during initialization.
03f5c550 WD	381	*/
a832ac41 KG	382	#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
a832ac41 KG	383	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
03f5c550	384
2835e518	385	#if defined(CONFIG_CMD_KGDB)
03f5c550	386	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
03f5c550 WD	387	#endif
03f5c550 WD	388
03f5c550 WD	389	/*
	390	* Environment Configuration
	391	*/
03f5c550	392	#if defined(CONFIG_TSEC_ENET)
10327dc5	393	#define CONFIG_HAS_ETH0
e2ffd59b	394	#define CONFIG_HAS_ETH1
e2ffd59b	395	#define CONFIG_HAS_ETH2
03f5c550 WD	396	#endif
	397
	398	#define CONFIG_IPADDR 192.168.1.253
	399
	400	#define CONFIG_HOSTNAME unknown
8b3637c6	401	#define CONFIG_ROOTPATH "/nfsroot"
b3f44c21	402	#define CONFIG_BOOTFILE "your.uImage"
03f5c550 WD	403
	404	#define CONFIG_SERVERIP 192.168.1.1
	405	#define CONFIG_GATEWAYIP 192.168.1.1
	406	#define CONFIG_NETMASK 255.255.255.0
	407
	408	#define CONFIG_LOADADDR 200000 /default location for tftp and bootm/
	409
03f5c550 WD	410	#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
	411
	412	#define CONFIG_BAUDRATE 115200
	413
	414	#define CONFIG_EXTRA_ENV_SETTINGS \
	415	"netdev=eth0\0" \
	416	"consoledev=ttyS1\0" \
8272dc2f AF	417	"ramdiskaddr=600000\0" \
	418	"ramdiskfile=your.ramdisk.u-boot\0" \
	419	"fdtaddr=400000\0" \
	420	"fdtfile=your.fdt.dtb\0"
03f5c550 WD	421
	422	#define CONFIG_NFSBOOTCOMMAND \
	423	"setenv bootargs root=/dev/nfs rw " \
	424	"nfsroot=$serverip:$rootpath " \
	425	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
	426	"console=$consoledev,$baudrate $othbootargs;" \
	427	"tftp $loadaddr $bootfile;" \
8272dc2f AF	428	"tftp $fdtaddr $fdtfile;" \
8272dc2f AF	429	"bootm $loadaddr - $fdtaddr"
03f5c550 WD	430
	431	#define CONFIG_RAMBOOTCOMMAND \
	432	"setenv bootargs root=/dev/ram rw " \
	433	"console=$consoledev,$baudrate $othbootargs;" \
	434	"tftp $ramdiskaddr $ramdiskfile;" \
	435	"tftp $loadaddr $bootfile;" \
	436	"bootm $loadaddr $ramdiskaddr"
	437
	438	#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
	439
03f5c550	440	#endif /* __CONFIG_H */