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03f5c550 | 1 | /* |
7c57f3e8 | 2 | * Copyright 2004, 2011 Freescale Semiconductor. |
03f5c550 WD |
3 | * |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | /* | |
24 | * mpc8555cds board configuration file | |
25 | * | |
26 | * Please refer to doc/README.mpc85xxcds for more info. | |
27 | * | |
28 | */ | |
03f5c550 WD |
29 | #ifndef __CONFIG_H |
30 | #define __CONFIG_H | |
31 | ||
32 | /* High Level Configuration Options */ | |
33 | #define CONFIG_BOOKE 1 /* BOOKE */ | |
34 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
35 | #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */ | |
9c4c5ae3 | 36 | #define CONFIG_CPM2 1 /* has CPM2 */ |
03f5c550 WD |
37 | #define CONFIG_MPC8555 1 /* MPC8555 specific */ |
38 | #define CONFIG_MPC8555CDS 1 /* MPC8555CDS board specific */ | |
39 | ||
2ae18241 WD |
40 | #define CONFIG_SYS_TEXT_BASE 0xfff80000 |
41 | ||
03f5c550 | 42 | #define CONFIG_PCI |
0151cbac | 43 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
53677ef1 | 44 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
03f5c550 | 45 | #define CONFIG_ENV_OVERWRITE |
2cfaa1aa | 46 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
03f5c550 | 47 | |
25eedb2c | 48 | #define CONFIG_FSL_VIA |
e8d18541 | 49 | |
25eedb2c | 50 | |
03f5c550 WD |
51 | #ifndef __ASSEMBLY__ |
52 | extern unsigned long get_clock_freq(void); | |
53 | #endif | |
54 | #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ | |
55 | ||
56 | /* | |
57 | * These can be toggled for performance analysis, otherwise use default. | |
58 | */ | |
53677ef1 | 59 | #define CONFIG_L2_CACHE /* toggle L2 cache */ |
03f5c550 | 60 | #define CONFIG_BTB /* toggle branch predition */ |
03f5c550 | 61 | |
6d0f6bcf JCPV |
62 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ |
63 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
03f5c550 | 64 | |
e46fedfe TT |
65 | #define CONFIG_SYS_CCSRBAR 0xe0000000 |
66 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
03f5c550 | 67 | |
2b40edb1 JL |
68 | /* DDR Setup */ |
69 | #define CONFIG_FSL_DDR1 | |
70 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ | |
71 | #define CONFIG_DDR_SPD | |
72 | #undef CONFIG_FSL_DDR_INTERACTIVE | |
73 | ||
74 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
75 | ||
6d0f6bcf JCPV |
76 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ |
77 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
03f5c550 | 78 | |
2b40edb1 JL |
79 | #define CONFIG_NUM_DDR_CONTROLLERS 1 |
80 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
81 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
03f5c550 | 82 | |
2b40edb1 JL |
83 | /* I2C addresses of SPD EEPROMs */ |
84 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ | |
85 | ||
86 | /* Make sure required options are set */ | |
03f5c550 WD |
87 | #ifndef CONFIG_SPD_EEPROM |
88 | #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS") | |
89 | #endif | |
90 | ||
7202d43d JL |
91 | #undef CONFIG_CLOCKS_IN_MHZ |
92 | ||
03f5c550 | 93 | /* |
7202d43d | 94 | * Local Bus Definitions |
03f5c550 | 95 | */ |
7202d43d JL |
96 | |
97 | /* | |
98 | * FLASH on the Local Bus | |
99 | * Two banks, 8M each, using the CFI driver. | |
100 | * Boot from BR0/OR0 bank at 0xff00_0000 | |
101 | * Alternate BR1/OR1 bank at 0xff80_0000 | |
102 | * | |
103 | * BR0, BR1: | |
104 | * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 | |
105 | * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 | |
106 | * Port Size = 16 bits = BRx[19:20] = 10 | |
107 | * Use GPCM = BRx[24:26] = 000 | |
108 | * Valid = BRx[31] = 1 | |
109 | * | |
110 | * 0 4 8 12 16 20 24 28 | |
111 | * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 | |
112 | * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 | |
113 | * | |
114 | * OR0, OR1: | |
115 | * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 | |
116 | * Reserved ORx[17:18] = 11, confusion here? | |
117 | * CSNT = ORx[20] = 1 | |
118 | * ACS = half cycle delay = ORx[21:22] = 11 | |
119 | * SCY = 6 = ORx[24:27] = 0110 | |
120 | * TRLX = use relaxed timing = ORx[29] = 1 | |
121 | * EAD = use external address latch delay = OR[31] = 1 | |
122 | * | |
123 | * 0 4 8 12 16 20 24 28 | |
124 | * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx | |
125 | */ | |
126 | ||
6d0f6bcf | 127 | #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 8M */ |
03f5c550 | 128 | |
6d0f6bcf JCPV |
129 | #define CONFIG_SYS_BR0_PRELIM 0xff801001 |
130 | #define CONFIG_SYS_BR1_PRELIM 0xff001001 | |
03f5c550 | 131 | |
6d0f6bcf JCPV |
132 | #define CONFIG_SYS_OR0_PRELIM 0xff806e65 |
133 | #define CONFIG_SYS_OR1_PRELIM 0xff806e65 | |
03f5c550 | 134 | |
6d0f6bcf JCPV |
135 | #define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} |
136 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | |
137 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ | |
138 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
139 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
140 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
03f5c550 | 141 | |
14d0a02a | 142 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
03f5c550 | 143 | |
00b1883a | 144 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
145 | #define CONFIG_SYS_FLASH_CFI |
146 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
03f5c550 | 147 | |
03f5c550 WD |
148 | |
149 | /* | |
7202d43d | 150 | * SDRAM on the Local Bus |
03f5c550 | 151 | */ |
6d0f6bcf JCPV |
152 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ |
153 | #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ | |
03f5c550 WD |
154 | |
155 | /* | |
156 | * Base Register 2 and Option Register 2 configure SDRAM. | |
6d0f6bcf | 157 | * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. |
03f5c550 WD |
158 | * |
159 | * For BR2, need: | |
160 | * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 | |
161 | * port-size = 32-bits = BR2[19:20] = 11 | |
162 | * no parity checking = BR2[21:22] = 00 | |
163 | * SDRAM for MSEL = BR2[24:26] = 011 | |
164 | * Valid = BR[31] = 1 | |
165 | * | |
166 | * 0 4 8 12 16 20 24 28 | |
167 | * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 | |
168 | * | |
6d0f6bcf | 169 | * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into |
03f5c550 WD |
170 | * FIXME: the top 17 bits of BR2. |
171 | */ | |
172 | ||
6d0f6bcf | 173 | #define CONFIG_SYS_BR2_PRELIM 0xf0001861 |
03f5c550 WD |
174 | |
175 | /* | |
6d0f6bcf | 176 | * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. |
03f5c550 WD |
177 | * |
178 | * For OR2, need: | |
179 | * 64MB mask for AM, OR2[0:7] = 1111 1100 | |
180 | * XAM, OR2[17:18] = 11 | |
181 | * 9 columns OR2[19-21] = 010 | |
182 | * 13 rows OR2[23-25] = 100 | |
183 | * EAD set for extra time OR[31] = 1 | |
184 | * | |
185 | * 0 4 8 12 16 20 24 28 | |
186 | * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 | |
187 | */ | |
188 | ||
6d0f6bcf | 189 | #define CONFIG_SYS_OR2_PRELIM 0xfc006901 |
03f5c550 | 190 | |
6d0f6bcf JCPV |
191 | #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ |
192 | #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ | |
193 | #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ | |
194 | #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ | |
03f5c550 | 195 | |
03f5c550 WD |
196 | /* |
197 | * Common settings for all Local Bus SDRAM commands. | |
198 | * At run time, either BSMA1516 (for CPU 1.1) | |
199 | * or BSMA1617 (for CPU 1.0) (old) | |
200 | * is OR'ed in too. | |
201 | */ | |
b0fe93ed KG |
202 | #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ |
203 | | LSDMR_PRETOACT7 \ | |
204 | | LSDMR_ACTTORW7 \ | |
205 | | LSDMR_BL8 \ | |
206 | | LSDMR_WRC4 \ | |
207 | | LSDMR_CL3 \ | |
208 | | LSDMR_RFEN \ | |
03f5c550 WD |
209 | ) |
210 | ||
211 | /* | |
212 | * The CADMUS registers are connected to CS3 on CDS. | |
213 | * The new memory map places CADMUS at 0xf8000000. | |
214 | * | |
215 | * For BR3, need: | |
216 | * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 | |
217 | * port-size = 8-bits = BR[19:20] = 01 | |
218 | * no parity checking = BR[21:22] = 00 | |
219 | * GPMC for MSEL = BR[24:26] = 000 | |
220 | * Valid = BR[31] = 1 | |
221 | * | |
222 | * 0 4 8 12 16 20 24 28 | |
223 | * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 | |
224 | * | |
225 | * For OR3, need: | |
226 | * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 | |
227 | * disable buffer ctrl OR[19] = 0 | |
228 | * CSNT OR[20] = 1 | |
229 | * ACS OR[21:22] = 11 | |
230 | * XACS OR[23] = 1 | |
231 | * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe | |
232 | * SETA OR[28] = 0 | |
233 | * TRLX OR[29] = 1 | |
234 | * EHTR OR[30] = 1 | |
235 | * EAD extra time OR[31] = 1 | |
236 | * | |
237 | * 0 4 8 12 16 20 24 28 | |
238 | * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 | |
239 | */ | |
240 | ||
25eedb2c JL |
241 | #define CONFIG_FSL_CADMUS |
242 | ||
03f5c550 | 243 | #define CADMUS_BASE_ADDR 0xf8000000 |
6d0f6bcf JCPV |
244 | #define CONFIG_SYS_BR3_PRELIM 0xf8000801 |
245 | #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 | |
03f5c550 | 246 | |
6d0f6bcf JCPV |
247 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
248 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ | |
553f0982 | 249 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ |
03f5c550 | 250 | |
25ddd1fb | 251 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 252 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
03f5c550 | 253 | |
6d0f6bcf JCPV |
254 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
255 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ | |
03f5c550 WD |
256 | |
257 | /* Serial Port */ | |
258 | #define CONFIG_CONS_INDEX 2 | |
6d0f6bcf JCPV |
259 | #define CONFIG_SYS_NS16550 |
260 | #define CONFIG_SYS_NS16550_SERIAL | |
261 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
262 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
03f5c550 | 263 | |
6d0f6bcf | 264 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
03f5c550 WD |
265 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
266 | ||
6d0f6bcf JCPV |
267 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
268 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
03f5c550 WD |
269 | |
270 | /* Use the HUSH parser */ | |
6d0f6bcf JCPV |
271 | #define CONFIG_SYS_HUSH_PARSER |
272 | #ifdef CONFIG_SYS_HUSH_PARSER | |
273 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
03f5c550 WD |
274 | #endif |
275 | ||
0e16387d | 276 | /* pass open firmware flat tree */ |
b90d2549 KG |
277 | #define CONFIG_OF_LIBFDT 1 |
278 | #define CONFIG_OF_BOARD_SETUP 1 | |
279 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
0e16387d | 280 | |
20476726 JL |
281 | /* |
282 | * I2C | |
283 | */ | |
284 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
285 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
03f5c550 | 286 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
6d0f6bcf JCPV |
287 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
288 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
289 | #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ | |
290 | #define CONFIG_SYS_I2C_OFFSET 0x3000 | |
03f5c550 | 291 | |
e8d18541 TT |
292 | /* EEPROM */ |
293 | #define CONFIG_ID_EEPROM | |
6d0f6bcf JCPV |
294 | #define CONFIG_SYS_I2C_EEPROM_CCID |
295 | #define CONFIG_SYS_ID_EEPROM | |
296 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
297 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
e8d18541 | 298 | |
03f5c550 WD |
299 | /* |
300 | * General PCI | |
301 | * Addresses are mapped 1-1. | |
302 | */ | |
5af0fdd8 | 303 | #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 |
10795f42 | 304 | #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 |
5af0fdd8 | 305 | #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 |
6d0f6bcf | 306 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ |
aca5f018 | 307 | #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 |
5f91ef6a | 308 | #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 |
6d0f6bcf JCPV |
309 | #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 |
310 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ | |
311 | ||
5af0fdd8 | 312 | #define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000 |
10795f42 | 313 | #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 |
5af0fdd8 | 314 | #define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 |
6d0f6bcf | 315 | #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ |
aca5f018 | 316 | #define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000 |
5f91ef6a | 317 | #define CONFIG_SYS_PCI2_IO_BUS 0x00000000 |
6d0f6bcf JCPV |
318 | #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000 |
319 | #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ | |
03f5c550 | 320 | |
7f3f2bd2 RV |
321 | #ifdef CONFIG_LEGACY |
322 | #define BRIDGE_ID 17 | |
323 | #define VIA_ID 2 | |
324 | #else | |
325 | #define BRIDGE_ID 28 | |
326 | #define VIA_ID 4 | |
327 | #endif | |
03f5c550 WD |
328 | |
329 | #if defined(CONFIG_PCI) | |
330 | ||
53677ef1 | 331 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
bf1dfffd | 332 | #define CONFIG_MPC85XX_PCI2 |
03f5c550 WD |
333 | |
334 | #undef CONFIG_EEPRO100 | |
335 | #undef CONFIG_TULIP | |
336 | ||
bf1dfffd | 337 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
6d0f6bcf | 338 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ |
03f5c550 WD |
339 | |
340 | #endif /* CONFIG_PCI */ | |
341 | ||
342 | ||
343 | #if defined(CONFIG_TSEC_ENET) | |
344 | ||
03f5c550 | 345 | #define CONFIG_MII 1 /* MII PHY management */ |
255a3577 KP |
346 | #define CONFIG_TSEC1 1 |
347 | #define CONFIG_TSEC1_NAME "TSEC0" | |
348 | #define CONFIG_TSEC2 1 | |
349 | #define CONFIG_TSEC2_NAME "TSEC1" | |
03f5c550 WD |
350 | #define TSEC1_PHY_ADDR 0 |
351 | #define TSEC2_PHY_ADDR 1 | |
03f5c550 WD |
352 | #define TSEC1_PHYIDX 0 |
353 | #define TSEC2_PHYIDX 0 | |
3a79013e AF |
354 | #define TSEC1_FLAGS TSEC_GIGABIT |
355 | #define TSEC2_FLAGS TSEC_GIGABIT | |
d9b94f28 JL |
356 | |
357 | /* Options are: TSEC[0-1] */ | |
358 | #define CONFIG_ETHPRIME "TSEC0" | |
03f5c550 WD |
359 | |
360 | #endif /* CONFIG_TSEC_ENET */ | |
361 | ||
03f5c550 WD |
362 | /* |
363 | * Environment | |
364 | */ | |
5a1aceb0 | 365 | #define CONFIG_ENV_IS_IN_FLASH 1 |
6d0f6bcf | 366 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) |
0e8d1586 JCPV |
367 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ |
368 | #define CONFIG_ENV_SIZE 0x2000 | |
03f5c550 WD |
369 | |
370 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 371 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
03f5c550 | 372 | |
659e2f67 JL |
373 | /* |
374 | * BOOTP options | |
375 | */ | |
376 | #define CONFIG_BOOTP_BOOTFILESIZE | |
377 | #define CONFIG_BOOTP_BOOTPATH | |
378 | #define CONFIG_BOOTP_GATEWAY | |
379 | #define CONFIG_BOOTP_HOSTNAME | |
380 | ||
381 | ||
2835e518 JL |
382 | /* |
383 | * Command line configuration. | |
384 | */ | |
385 | #include <config_cmd_default.h> | |
386 | ||
387 | #define CONFIG_CMD_PING | |
388 | #define CONFIG_CMD_I2C | |
389 | #define CONFIG_CMD_MII | |
82ac8c97 | 390 | #define CONFIG_CMD_ELF |
1c9aa76b KG |
391 | #define CONFIG_CMD_IRQ |
392 | #define CONFIG_CMD_SETEXPR | |
199e262e | 393 | #define CONFIG_CMD_REGINFO |
2835e518 | 394 | |
03f5c550 | 395 | #if defined(CONFIG_PCI) |
2835e518 | 396 | #define CONFIG_CMD_PCI |
03f5c550 | 397 | #endif |
2835e518 | 398 | |
03f5c550 WD |
399 | |
400 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
401 | ||
402 | /* | |
403 | * Miscellaneous configurable options | |
404 | */ | |
6d0f6bcf | 405 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
5be58f5f KP |
406 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
407 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
6d0f6bcf JCPV |
408 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
409 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
2835e518 | 410 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 411 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
03f5c550 | 412 | #else |
6d0f6bcf | 413 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
03f5c550 | 414 | #endif |
6d0f6bcf JCPV |
415 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
416 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
417 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
418 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
03f5c550 WD |
419 | |
420 | /* | |
421 | * For booting Linux, the board info and command line data | |
a832ac41 | 422 | * have to be in the first 64 MB of memory, since this is |
03f5c550 WD |
423 | * the maximum mapped by the Linux kernel during initialization. |
424 | */ | |
a832ac41 KG |
425 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ |
426 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
03f5c550 | 427 | |
2835e518 | 428 | #if defined(CONFIG_CMD_KGDB) |
03f5c550 WD |
429 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
430 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
431 | #endif | |
432 | ||
03f5c550 WD |
433 | /* |
434 | * Environment Configuration | |
435 | */ | |
436 | ||
437 | /* The mac addresses for all ethernet interface */ | |
438 | #if defined(CONFIG_TSEC_ENET) | |
10327dc5 | 439 | #define CONFIG_HAS_ETH0 |
03f5c550 | 440 | #define CONFIG_ETHADDR 00:E0:0C:00:00:FD |
e2ffd59b | 441 | #define CONFIG_HAS_ETH1 |
03f5c550 | 442 | #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD |
e2ffd59b | 443 | #define CONFIG_HAS_ETH2 |
03f5c550 WD |
444 | #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD |
445 | #endif | |
446 | ||
447 | #define CONFIG_IPADDR 192.168.1.253 | |
448 | ||
449 | #define CONFIG_HOSTNAME unknown | |
450 | #define CONFIG_ROOTPATH /nfsroot | |
451 | #define CONFIG_BOOTFILE your.uImage | |
452 | ||
453 | #define CONFIG_SERVERIP 192.168.1.1 | |
454 | #define CONFIG_GATEWAYIP 192.168.1.1 | |
455 | #define CONFIG_NETMASK 255.255.255.0 | |
456 | ||
457 | #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ | |
458 | ||
459 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
460 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ | |
461 | ||
462 | #define CONFIG_BAUDRATE 115200 | |
463 | ||
464 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
465 | "netdev=eth0\0" \ | |
466 | "consoledev=ttyS1\0" \ | |
8272dc2f AF |
467 | "ramdiskaddr=600000\0" \ |
468 | "ramdiskfile=your.ramdisk.u-boot\0" \ | |
469 | "fdtaddr=400000\0" \ | |
470 | "fdtfile=your.fdt.dtb\0" | |
03f5c550 WD |
471 | |
472 | #define CONFIG_NFSBOOTCOMMAND \ | |
473 | "setenv bootargs root=/dev/nfs rw " \ | |
474 | "nfsroot=$serverip:$rootpath " \ | |
475 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
476 | "console=$consoledev,$baudrate $othbootargs;" \ | |
477 | "tftp $loadaddr $bootfile;" \ | |
8272dc2f AF |
478 | "tftp $fdtaddr $fdtfile;" \ |
479 | "bootm $loadaddr - $fdtaddr" | |
03f5c550 WD |
480 | |
481 | #define CONFIG_RAMBOOTCOMMAND \ | |
482 | "setenv bootargs root=/dev/ram rw " \ | |
483 | "console=$consoledev,$baudrate $othbootargs;" \ | |
484 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
485 | "tftp $loadaddr $bootfile;" \ | |
486 | "bootm $loadaddr $ramdiskaddr" | |
487 | ||
488 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
489 | ||
03f5c550 | 490 | #endif /* __CONFIG_H */ |