[u-boot.git] / include / ns9750_eth.h

/***********************************************************************
 *
 * Copyright (C) 2004 by FS Forth-Systeme GmbH.
 * All rights reserved.
 *
 * $Id: ns9750_eth.h,v 1.2 2004/02/24 13:25:39 mpietrek Exp $
 * @Author: Markus Pietrek
 * @References: [1] NS9750 Hardware Reference, December 2003
 *              [2] Intel LXT971 Datasheet #249414 Rev. 02
 *              [3] NS7520 Linux Ethernet Driver
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 ***********************************************************************/

#ifndef FS_NS9750_ETH_H
#define FS_NS9750_ETH_H

#ifdef CONFIG_DRIVER_NS9750_ETHERNET

#define	NS9750_ETH_MODULE_BASE	 	(0xA0600000)

#define get_eth_reg_addr(c) \
     ((volatile unsigned int*) ( NS9750_ETH_MODULE_BASE+(unsigned int) (c)))

#define NS9750_ETH_EGCR1	 	(0x0000)
#define NS9750_ETH_EGCR2	 	(0x0004)
#define NS9750_ETH_EGSR		 	(0x0008)
#define NS9750_ETH_FIFORX	 	(0x000C)
#define NS9750_ETH_FIFOTX	 	(0x0010)
#define NS9750_ETH_FIFOTXS	 	(0x0014)
#define NS9750_ETH_ETSR		 	(0x0018)
#define NS9750_ETH_ERSR		 	(0x001C)
#define NS9750_ETH_MAC1			(0x0400)
#define NS9750_ETH_MAC2			(0x0404)
#define NS9750_ETH_IPGT			(0x0408)
#define NS9750_ETH_IPGR			(0x040C)
#define NS9750_ETH_CLRT			(0x0410)
#define NS9750_ETH_MAXF			(0x0414)
#define NS9750_ETH_SUPP			(0x0418)
#define NS9750_ETH_TEST			(0x041C)
#define NS9750_ETH_MCFG			(0x0420)
#define NS9750_ETH_MCMD			(0x0424)
#define NS9750_ETH_MADR			(0x0428)
#define NS9750_ETH_MWTD			(0x042C)
#define NS9750_ETH_MRDD			(0x0430)
#define NS9750_ETH_MIND			(0x0434)
#define NS9750_ETH_SA1			(0x0440)
#define NS9750_ETH_SA2			(0x0444)
#define NS9750_ETH_SA3			(0x0448)
#define NS9750_ETH_SAFR			(0x0500)
#define NS9750_ETH_HT1		 	(0x0504)
#define NS9750_ETH_HT2		 	(0x0508)
#define NS9750_ETH_STAT_BASE	 	(0x0680)
#define NS9750_ETH_RXAPTR		(0x0A00)
#define NS9750_ETH_RXBPTR		(0x0A04)
#define NS9750_ETH_RXCPTR		(0x0A08)
#define NS9750_ETH_RXDPTR		(0x0A0C)
#define NS9750_ETH_EINTR		(0x0A10)
#define NS9750_ETH_EINTREN		(0x0A14)
#define NS9750_ETH_TXPTR		(0x0A18)
#define NS9750_ETH_TXRPTR		(0x0A1C)
#define NS9750_ETH_TXERBD		(0x0A20)
#define NS9750_ETH_TXSPTR		(0x0A24)
#define NS9750_ETH_RXAOFF		(0x0A28)
#define NS9750_ETH_RXBOFF		(0x0A2C)
#define NS9750_ETH_RXCOFF		(0x0A30)
#define NS9750_ETH_RXDOFF		(0x0A34)
#define NS9750_ETH_TXOFF		(0x0A38)
#define NS9750_ETH_RXFREE		(0x0A3C)
#define NS9750_ETH_TXBD			(0x1000)

/* register bit fields */

#define NS9750_ETH_EGCR1_ERX	 	(0x80000000)
#define NS9750_ETH_EGCR1_ERXDMA	 	(0x40000000)
#define NS9750_ETH_EGCR1_ERXSHT	 	(0x10000000)
#define NS9750_ETH_EGCR1_ERXSIZ	 	(0x08000000)
#define NS9750_ETH_EGCR1_ETXSIZ	 	(0x04000000)
#define NS9750_ETH_EGCR1_ETXDIAG	(0x02000000)
#define NS9750_ETH_EGCR1_ERXBAD	 	(0x01000000)
#define NS9750_ETH_EGCR1_ETX	 	(0x00800000)
#define NS9750_ETH_EGCR1_ETXDMA	 	(0x00400000)
#define NS9750_ETH_EGCR1_ETXWM	  	(0x00200000)
#define NS9750_ETH_EGCR1_ERXADV	 	(0x00100000)
#define NS9750_ETH_EGCR1_ERXINIT	(0x00080000)
#define NS9750_ETH_EGCR1_PHY_MODE_MA  	(0x0000C000)
#define NS9750_ETH_EGCR1_PHY_MODE_MII 	(0x00008000)
#define NS9750_ETH_EGCR1_PHY_MODE_RMII 	(0x00004000)
#define NS9750_ETH_EGCR1_RXCINV	 	(0x00001000)
#define NS9750_ETH_EGCR1_TXCINV	 	(0x00000800)
#define NS9750_ETH_EGCR1_RXALIGN	(0x00000400)
#define NS9750_ETH_EGCR1_MAC_HRST 	(0x00000200)
#define NS9750_ETH_EGCR1_ITXA	 	(0x00000100)

#define NS9750_ETH_EGCR2_TPTV_MA	(0xFFFF0000)
#define NS9750_ETH_EGCR2_TPCF		(0x00000040)
#define NS9750_ETH_EGCR2_THPDF		(0x00000020)
#define NS9750_ETH_EGCR2_TCLER		(0x00000008)
#define NS9750_ETH_EGCR2_AUTOZ		(0x00000004)
#define NS9750_ETH_EGCR2_CLRCNT		(0x00000002)
#define NS9750_ETH_EGCR2_STEN		(0x00000001)

#define NS9750_ETH_EGSR_RXINIT	 	(0x00100000)
#define NS9750_ETH_EGSR_TXFIFONF 	(0x00080000)
#define NS9750_ETH_EGSR_TXFIFOH	 	(0x00040000)
#define NS9750_ETH_EGSR_TXFIFOE	 	(0x00010000)

#define NS9750_ETH_FIFOTXS_ALL		(0x00000055)
#define NS9750_ETH_FIFOTXS_3		(0x000000d5)
#define NS9750_ETH_FIFOTXS_2		(0x00000035)
#define NS9750_ETH_FIFOTXS_1		(0x0000000D)
#define NS9750_ETH_FIFOTXS_0		(0x00000003)

#define NS9750_ETH_ETSR_TXOK	 	(0x00008000)
#define NS9750_ETH_ETSR_TXBR	 	(0x00004000)
#define NS9750_ETH_ETSR_TXMC	 	(0x00002000)
#define NS9750_ETH_ETSR_TXAL	 	(0x00001000)
#define NS9750_ETH_ETSR_TXAED	 	(0x00000800)
#define NS9750_ETH_ETSR_TXAEC	 	(0x00000400)
#define NS9750_ETH_ETSR_TXAUR	 	(0x00000200)
#define NS9750_ETH_ETSR_TXAJ	 	(0x00000100)
#define NS9750_ETH_ETSR_TXDEF	 	(0x00000040)
#define NS9750_ETH_ETSR_TXCRC	 	(0x00000020)
#define NS9750_ETH_ETSR_TXCOLC   	(0x0000000F)

#define NS9750_ETH_ERSR_RXSIZE_MA	(0x0FFF0000)
#define NS9750_ETH_ERSR_RXCE	 	(0x00008000)
#define NS9750_ETH_ERSR_RXDV	 	(0x00004000)
#define NS9750_ETH_ERSR_RXOK	 	(0x00002000)
#define NS9750_ETH_ERSR_RXBR	 	(0x00001000)
#define NS9750_ETH_ERSR_RXMC	 	(0x00000800)
#define NS9750_ETH_ERSR_RXCRC	 	(0x00000400)
#define NS9750_ETH_ERSR_RXDR	 	(0x00000200)
#define NS9750_ETH_ERSR_RXCV	 	(0x00000100)
#define NS9750_ETH_ERSR_RXSHT	 	(0x00000040)

#define NS9750_ETH_MAC1_SRST	 	(0x00008000)
#define NS9750_ETH_MAC1_SIMMRST	 	(0x00004000)
#define NS9750_ETH_MAC1_RPEMCSR	 	(0x00000800)
#define NS9750_ETH_MAC1_RPERFUN	 	(0x00000400)
#define NS9750_ETH_MAC1_RPEMCST	 	(0x00000200)
#define NS9750_ETH_MAC1_RPETFUN	 	(0x00000100)
#define NS9750_ETH_MAC1_LOOPBK	 	(0x00000010)
#define NS9750_ETH_MAC1_TXFLOW	 	(0x00000008)
#define NS9750_ETH_MAC1_RXFLOW	 	(0x00000004)
#define NS9750_ETH_MAC1_PALLRX	 	(0x00000002)
#define NS9750_ETH_MAC1_RXEN	 	(0x00000001)

#define NS9750_ETH_MAC2_EDEFER	 	(0x00004000)
#define NS9750_ETH_MAC2_BACKP	 	(0x00002000)
#define NS9750_ETH_MAC2_NOBO	 	(0x00001000)
#define NS9750_ETH_MAC2_LONGP	 	(0x00000200)
#define NS9750_ETH_MAC2_PUREP	 	(0x00000100)
#define NS9750_ETH_MAC2_AUTOP	 	(0x00000080)
#define NS9750_ETH_MAC2_VLANP	 	(0x00000040)
#define NS9750_ETH_MAC2_PADEN  	 	(0x00000020)
#define NS9750_ETH_MAC2_CRCEN	 	(0x00000010)
#define NS9750_ETH_MAC2_DELCRC	 	(0x00000008)
#define NS9750_ETH_MAC2_HUGE	 	(0x00000004)
#define NS9750_ETH_MAC2_FLENC	 	(0x00000002)
#define NS9750_ETH_MAC2_FULLD	 	(0x00000001)

#define NS9750_ETH_IPGT_MA	 	(0x0000007F)

#define NS9750_ETH_IPGR_IPGR1	 	(0x00007F00)
#define NS9750_ETH_IPGR_IPGR2	 	(0x0000007F)

#define NS9750_ETH_CLRT_CWIN	 	(0x00003F00)
#define	NS9750_ETH_CLRT_RETX	 	(0x0000000F)

#define NS9750_ETH_MAXF_MAXF	 	(0x0000FFFF)

#define NS9750_ETH_SUPP_RPERMII	 	(0x00008000)
#define NS9750_ETH_SUPP_SPEED  	 	(0x00000080)

#define NS9750_ETH_TEST_TBACK	 	(0x00000004)
#define NS9750_ETH_TEST_TPAUSE	 	(0x00000002)
#define NS9750_ETH_TEST_SPQ	 	(0x00000001)

#define NS9750_ETH_MCFG_RMIIM	 	(0x00008000)
#define NS9750_ETH_MCFG_CLKS_MA	 	(0x0000001C)
#define NS9750_ETH_MCFG_CLKS_4	 	(0x00000004)
#define NS9750_ETH_MCFG_CLKS_6	 	(0x00000008)
#define NS9750_ETH_MCFG_CLKS_8	 	(0x0000000C)
#define NS9750_ETH_MCFG_CLKS_10	 	(0x00000010)
#define NS9750_ETH_MCFG_CLKS_20	 	(0x00000014)
#define NS9750_ETH_MCFG_CLKS_30	 	(0x00000018)
#define NS9750_ETH_MCFG_CLKS_40	 	(0x0000001C)
#define NS9750_ETH_MCFG_SPRE	 	(0x00000002)
#define NS9750_ETH_MCFG_SCANI	 	(0x00000001)

#define NS9750_ETH_MCMD_SCAN	 	(0x00000002)
#define NS9750_ETH_MCMD_READ	 	(0x00000001)

#define NS9750_ETH_MADR_DADR_MA	 	(0x00001F00)
#define NS9750_ETH_MADR_RADR_MA	 	(0x0000001F)

#define NS9750_ETH_MWTD_MA	 	(0x0000FFFF)

#define NS9750_ETH_MRRD_MA	 	(0x0000FFFF)

#define NS9750_ETH_MIND_MIILF		(0x00000008)
#define NS9750_ETH_MIND_NVALID		(0x00000004)
#define NS9750_ETH_MIND_SCAN	 	(0x00000002)
#define NS9750_ETH_MIND_BUSY	 	(0x00000001)

#define NS9750_ETH_SA1_OCTET1_MA 	(0x0000FF00)
#define NS9750_ETH_SA1_OCTET2_MA 	(0x000000FF)

#define NS9750_ETH_SA2_OCTET3_MA 	(0x0000FF00)
#define NS9750_ETH_SA2_OCTET4_MA 	(0x000000FF)

#define NS9750_ETH_SA3_OCTET5_MA 	(0x0000FF00)
#define NS9750_ETH_SA3_OCTET6_MA 	(0x000000FF)

#define NS9750_ETH_SAFR_PRO	 	(0x00000008)
#define NS9750_ETH_SAFR_PRM	 	(0x00000004)
#define NS9750_ETH_SAFR_PRA	 	(0x00000002)
#define NS9750_ETH_SAFR_BROAD	 	(0x00000001)

#define NS9750_ETH_HT1_MA	 	(0x0000FFFF)

#define NS9750_ETH_HT2_MA	 	(0x0000FFFF)

/* also valid for EINTREN */
#define NS9750_ETH_EINTR_RXOVL_DATA	(0x02000000)
#define NS9750_ETH_EINTR_RXOVL_STAT	(0x01000000)
#define NS9750_ETH_EINTR_RXBUFC		(0x00800000)
#define NS9750_ETH_EINTR_RXDONEA	(0x00400000)
#define NS9750_ETH_EINTR_RXDONEB	(0x00200000)
#define NS9750_ETH_EINTR_RXDONEC	(0x00100000)
#define NS9750_ETH_EINTR_RXDONED	(0x00080000)
#define NS9750_ETH_EINTR_RXNOBUF	(0x00040000)
#define NS9750_ETH_EINTR_RXBUFFUL	(0x00020000)
#define NS9750_ETH_EINTR_RXBR		(0x00010000)
#define NS9750_ETH_EINTR_STOVFL		(0x00000040)
#define NS9750_ETH_EINTR_TXPAUSE	(0x00000020)
#define NS9750_ETH_EINTR_TXBUFC		(0x00000010)
#define NS9750_ETH_EINTR_TXBUFNR	(0x00000008)
#define NS9750_ETH_EINTR_TXDONE		(0x00000004)
#define NS9750_ETH_EINTR_TXERR 		(0x00000002)
#define NS9750_ETH_EINTR_TXIDLE		(0x00000001)
#define NS9750_ETH_EINTR_RX_MA	\
	(NS9750_ETH_EINTR_RXOVL_DATA | \
	 NS9750_ETH_EINTR_RXOVL_STAT | \
	 NS9750_ETH_EINTR_RXBUFC | \
	 NS9750_ETH_EINTR_RXDONEA | \
	 NS9750_ETH_EINTR_RXDONEB | \
	 NS9750_ETH_EINTR_RXDONEC | \
	 NS9750_ETH_EINTR_RXDONED | \
	 NS9750_ETH_EINTR_RXNOBUF | \
	 NS9750_ETH_EINTR_RXBUFFUL | \
	 NS9750_ETH_EINTR_RXBR )
#define NS9750_ETH_EINTR_TX_MA	\
	(NS9750_ETH_EINTR_TXPAUSE | \
	 NS9750_ETH_EINTR_TXBUFC | \
	 NS9750_ETH_EINTR_TXBUFNR | \
	 NS9750_ETH_EINTR_TXDONE | \
	 NS9750_ETH_EINTR_TXERR | \
	 NS9750_ETH_EINTR_TXIDLE)

/* for TXPTR, TXRPTR, TXERBD and TXSPTR */
#define NS9750_ETH_TXPTR_MA		(0x000000FF)

/* for RXAOFF, RXBOFF, RXCOFF and RXDOFF */
#define NS9750_ETH_RXOFF_MA		(0x000007FF)

#define NS9750_ETH_TXOFF_MA		(0x000003FF)

#define NS9750_ETH_RXFREE_D		(0x00000008)
#define NS9750_ETH_RXFREE_C		(0x00000004)
#define NS9750_ETH_RXFREE_B		(0x00000002)
#define NS9750_ETH_RXFREE_A		(0x00000001)

/* PHY definitions (LXT971A) [2] */

#define PHY_COMMON_CTRL    	 	(0x00)
#define PHY_COMMON_STAT    	 	(0x01)
#define PHY_COMMON_ID1    	 	(0x02)
#define PHY_COMMON_ID2           	(0x03)
#define PHY_COMMON_AUTO_ADV      	(0x04)
#define PHY_COMMON_AUTO_LNKB     	(0x05)
#define PHY_COMMON_AUTO_EXP      	(0x06)
#define PHY_COMMON_AUTO_NEXT     	(0x07)
#define PHY_COMMON_AUTO_LNKN     	(0x08)
#define PHY_LXT971_PORT_CFG      	(0x10)
#define PHY_LXT971_STAT2         	(0x11)
#define PHY_LXT971_INT_ENABLE    	(0x12)
#define PHY_LXT971_INT_STATUS    	(0x13)
#define PHY_LXT971_LED_CFG       	(0x14)
#define PHY_LXT971_DIG_CFG       	(0x1A)
#define PHY_LXT971_TX_CTRL       	(0x1E)

/* CTRL PHY Control Register Bit Fields */

#define PHY_COMMON_CTRL_RESET  	 	(0x8000)
#define PHY_COMMON_CTRL_LOOPBACK 	(0x4000)
#define PHY_COMMON_CTRL_SPD_MA   	(0x2040)
#define PHY_COMMON_CTRL_SPD_10   	(0x0000)
#define PHY_COMMON_CTRL_SPD_100  	(0x2000)
#define PHY_COMMON_CTRL_SPD_1000 	(0x0040)
#define PHY_COMMON_CTRL_SPD_RES  	(0x2040)
#define PHY_COMMON_CTRL_AUTO_NEG 	(0x1000)
#define PHY_COMMON_CTRL_POWER_DN 	(0x0800)
#define PHY_COMMON_CTRL_ISOLATE	 	(0x0400)
#define PHY_COMMON_CTRL_RES_AUTO 	(0x0200)
#define PHY_COMMON_CTRL_DUPLEX	 	(0x0100)
#define PHY_COMMON_CTRL_COL_TEST 	(0x0080)
#define PHY_COMMON_CTRL_RES1     	(0x003F)

/* STAT Status Register Bit Fields */

#define PHY_COMMON_STAT_100BT4	 	(0x8000)
#define PHY_COMMON_STAT_100BXFD	 	(0x4000)
#define PHY_COMMON_STAT_100BXHD	 	(0x2000)
#define PHY_COMMON_STAT_10BTFD	 	(0x1000)
#define PHY_COMMON_STAT_10BTHD	 	(0x0800)
#define PHY_COMMON_STAT_100BT2FD 	(0x0400)
#define PHY_COMMON_STAT_100BT2HD 	(0x0200)
#define PHY_COMMON_STAT_EXT_STAT 	(0x0100)
#define PHY_COMMON_STAT_RES1	 	(0x0080)
#define PHY_COMMON_STAT_MF_PSUP	 	(0x0040)
#define PHY_COMMON_STAT_AN_COMP  	(0x0020)
#define PHY_COMMON_STAT_RMT_FLT	 	(0x0010)
#define PHY_COMMON_STAT_AN_CAP	 	(0x0008)
#define PHY_COMMON_STAT_LNK_STAT 	(0x0004)
#define PHY_COMMON_STAT_JAB_DTCT 	(0x0002)
#define PHY_COMMON_STAT_EXT_CAP	 	(0x0001)


/* AUTO_ADV Auto-neg Advert Register Bit Fields */

#define PHY_COMMON_AUTO_ADV_NP       	(0x8000)
#define PHY_COMMON_AUTO_ADV_RES1        (0x4000)
#define PHY_COMMON_AUTO_ADV_RMT_FLT     (0x2000)
#define PHY_COMMON_AUTO_ADV_RES2        (0x1000)
#define PHY_COMMON_AUTO_ADV_AS_PAUSE    (0x0800)
#define PHY_COMMON_AUTO_ADV_PAUSE       (0x0400)
#define PHY_COMMON_AUTO_ADV_100BT4      (0x0200)
#define PHY_COMMON_AUTO_ADV_100BTXFD   	(0x0100)
#define PHY_COMMON_AUTO_ADV_100BTX      (0x0080)
#define PHY_COMMON_AUTO_ADV_10BTFD   	(0x0040)
#define PHY_COMMON_AUTO_ADV_10BT     	(0x0020)
#define PHY_COMMON_AUTO_ADV_SEL_FLD_MA  (0x001F)
#define PHY_COMMON_AUTO_ADV_802_9       (0x0002)
#define PHY_COMMON_AUTO_ADV_802_3       (0x0001)

/* AUTO_LNKB Auto-neg Link Ability Register Bit Fields */

#define PHY_COMMON_AUTO_LNKB_NP       	(0x8000)
#define PHY_COMMON_AUTO_LNKB_ACK        (0x4000)
#define PHY_COMMON_AUTO_LNKB_RMT_FLT    (0x2000)
#define PHY_COMMON_AUTO_LNKB_RES2       (0x1000)
#define PHY_COMMON_AUTO_LNKB_AS_PAUSE   (0x0800)
#define PHY_COMMON_AUTO_LNKB_PAUSE      (0x0400)
#define PHY_COMMON_AUTO_LNKB_100BT4     (0x0200)
#define PHY_COMMON_AUTO_LNKB_100BTXFD   (0x0100)
#define PHY_COMMON_AUTO_LNKB_100BTX     (0x0080)
#define PHY_COMMON_AUTO_LNKB_10BTFD   	(0x0040)
#define PHY_COMMON_AUTO_LNKB_10BT     	(0x0020)
#define PHY_COMMON_AUTO_LNKB_SEL_FLD_MA (0x001F)
#define PHY_COMMON_AUTO_LNKB_802_9      (0x0002)
#define PHY_COMMON_AUTO_LNKB_802_3      (0x0001)

/* AUTO_EXP Auto-neg Expansion Register Bit Fields */

#define PHY_COMMON_AUTO_EXP_RES1        (0xFFC0)
#define PHY_COMMON_AUTO_EXP_BASE_PAGE   (0x0020)
#define PHY_COMMON_AUTO_EXP_PAR_DT_FLT  (0x0010)
#define PHY_COMMON_AUTO_EXP_LNK_NP_CAP  (0x0008)
#define PHY_COMMON_AUTO_EXP_NP_CAP      (0x0004)
#define PHY_COMMON_AUTO_EXP_PAGE_REC    (0x0002)
#define PHY_COMMON_AUTO_EXP_LNK_AN_CAP  (0x0001)

/* AUTO_NEXT Aut-neg Next Page Tx Register Bit Fields */

#define PHY_COMMON_AUTO_NEXT_NP         (0x8000)
#define PHY_COMMON_AUTO_NEXT_RES1       (0x4000)
#define PHY_COMMON_AUTO_NEXT_MSG_PAGE   (0x2000)
#define PHY_COMMON_AUTO_NEXT_ACK_2      (0x1000)
#define PHY_COMMON_AUTO_NEXT_TOGGLE     (0x0800)
#define PHY_COMMON_AUTO_NEXT_MSG        (0x07FF)

/* AUTO_LNKN Auto-neg Link Partner Rx Reg Bit Fields */

#define PHY_COMMON_AUTO_LNKN_NP         (0x8000)
#define PHY_COMMON_AUTO_LNKN_ACK        (0x4000)
#define PHY_COMMON_AUTO_LNKN_MSG_PAGE   (0x2000)
#define PHY_COMMON_AUTO_LNKN_ACK_2      (0x1000)
#define PHY_COMMON_AUTO_LNKN_TOGGLE     (0x0800)
#define PHY_COMMON_AUTO_LNKN_MSG        (0x07FF)

/* PORT_CFG Port Configuration Register Bit Fields */

#define PHY_LXT971_PORT_CFG_RES1        (0x8000)
#define PHY_LXT971_PORT_CFG_FORCE_LNK   (0x4000)
#define PHY_LXT971_PORT_CFG_TX_DISABLE  (0x2000)
#define PHY_LXT971_PORT_CFG_BYPASS_SCR  (0x1000)
#define PHY_LXT971_PORT_CFG_RES2        (0x0800)
#define PHY_LXT971_PORT_CFG_JABBER      (0x0400)
#define PHY_LXT971_PORT_CFG_SQE	        (0x0200)
#define PHY_LXT971_PORT_CFG_TP_LOOPBACK (0x0100)
#define PHY_LXT971_PORT_CFG_CRS_SEL     (0x0080)
#define PHY_LXT971_PORT_CFG_SLEEP_MODE  (0x0040)
#define PHY_LXT971_PORT_CFG_PRE_EN      (0x0020)
#define PHY_LXT971_PORT_CFG_SLEEP_T_MA  (0x0018)
#define PHY_LXT971_PORT_CFG_SLEEP_T_104 (0x0010)
#define PHY_LXT971_PORT_CFG_SLEEP_T_200 (0x0001)
#define PHY_LXT971_PORT_CFG_SLEEP_T_304 (0x0000)
#define PHY_LXT971_PORT_CFG_FLT_CODE_EN (0x0004)
#define PHY_LXT971_PORT_CFG_ALT_NP      (0x0002)
#define PHY_LXT971_PORT_CFG_FIBER_SEL   (0x0001)

/* STAT2 Status Register #2 Bit Fields */

#define PHY_LXT971_STAT2_RES1   	(0x8000)
#define PHY_LXT971_STAT2_100BTX 	(0x4000)
#define PHY_LXT971_STAT2_TX_STATUS	(0x2000)
#define PHY_LXT971_STAT2_RX_STATUS	(0x1000)
#define PHY_LXT971_STAT2_COL_STATUS	(0x0800)
#define PHY_LXT971_STAT2_LINK   	(0x0400)
#define PHY_LXT971_STAT2_DUPLEX_MODE	(0x0200)
#define PHY_LXT971_STAT2_AUTO_NEG	(0x0100)
#define PHY_LXT971_STAT2_AUTO_NEG_COMP 	(0x0080)
#define PHY_LXT971_STAT2_RES2   	(0x0040)
#define PHY_LXT971_STAT2_POLARITY	(0x0020)
#define PHY_LXT971_STAT2_PAUSE  	(0x0010)
#define PHY_LXT971_STAT2_ERROR  	(0x0008)
#define PHY_LXT971_STAT2_RES3   	(0x0007)

/* INT_ENABLE Interrupt Enable Register Bit Fields */

#define PHY_LXT971_INT_ENABLE_RES1      (0xFF00)
#define PHY_LXT971_INT_ENABLE_ANMSK     (0x0080)
#define PHY_LXT971_INT_ENABLE_SPEEDMSK  (0x0040)
#define PHY_LXT971_INT_ENABLE_DUPLEXMSK (0x0020)
#define PHY_LXT971_INT_ENABLE_LINKMSK   (0x0010)
#define PHY_LXT971_INT_ENABLE_RES2      (0x000C)
#define PHY_LXT971_INT_ENABLE_INTEN     (0x0002)
#define PHY_LXT971_INT_ENABLE_TINT      (0x0001)

/* INT_STATUS Interrupt Status Register Bit Fields */

#define PHY_LXT971_INT_STATUS_RES1      (0xFF00)
#define PHY_LXT971_INT_STATUS_ANDONE    (0x0080)
#define PHY_LXT971_INT_STATUS_SPEEDCHG  (0x0040)
#define PHY_LXT971_INT_STATUS_DUPLEXCHG (0x0020)
#define PHY_LXT971_INT_STATUS_LINKCHG   (0x0010)
#define PHY_LXT971_INT_STATUS_RES2      (0x0008)
#define PHY_LXT971_INT_STATUS_MDINT     (0x0004)
#define PHY_LXT971_INT_STATUS_RES3      (0x0003)

/* LED_CFG Interrupt LED Configuration Register Bit Fields */

#define PHY_LXT971_LED_CFG_SHIFT_LED1   (0x000C)
#define PHY_LXT971_LED_CFG_SHIFT_LED2   (0x0008)
#define PHY_LXT971_LED_CFG_SHIFT_LED3   (0x0004)
#define PHY_LXT971_LED_CFG_LEDFREQ_MA	(0x000C)
#define PHY_LXT971_LED_CFG_LEDFREQ_RES	(0x000C)
#define PHY_LXT971_LED_CFG_LEDFREQ_100	(0x0008)
#define PHY_LXT971_LED_CFG_LEDFREQ_60	(0x0004)
#define PHY_LXT971_LED_CFG_LEDFREQ_30	(0x0000)
#define PHY_LXT971_LED_CFG_PULSE_STR    (0x0002)
#define PHY_LXT971_LED_CFG_RES1         (0x0001)

/* only one of these values must be shifted for each SHIFT_LED?  */

#define PHY_LXT971_LED_CFG_UNUSED1      (0x000F)
#define PHY_LXT971_LED_CFG_DUPLEX_COL   (0x000E)
#define PHY_LXT971_LED_CFG_LINK_ACT     (0x000D)
#define PHY_LXT971_LED_CFG_LINK_RX      (0x000C)
#define PHY_LXT971_LED_CFG_TEST_BLK_SLW (0x000B)
#define PHY_LXT971_LED_CFG_TEST_BLK_FST (0x000A)
#define PHY_LXT971_LED_CFG_TEST_OFF     (0x0009)
#define PHY_LXT971_LED_CFG_TEST_ON      (0x0008)
#define PHY_LXT971_LED_CFG_RX_OR_TX     (0x0007)
#define PHY_LXT971_LED_CFG_UNUSED2      (0x0006)
#define PHY_LXT971_LED_CFG_DUPLEX       (0x0005)
#define PHY_LXT971_LED_CFG_LINK	        (0x0004)
#define PHY_LXT971_LED_CFG_COLLISION    (0x0003)
#define PHY_LXT971_LED_CFG_RECEIVE      (0x0002)
#define PHY_LXT971_LED_CFG_TRANSMIT     (0x0001)
#define PHY_LXT971_LED_CFG_SPEED        (0x0000)

/* DIG_CFG Digitial Configuration Register Bit Fields */

#define PHY_LXT971_DIG_CFG_RES1 	(0xF000)
#define PHY_LXT971_DIG_CFG_MII_DRIVE	(0x0800)
#define PHY_LXT971_DIG_CFG_RES2 	(0x0400)
#define PHY_LXT971_DIG_CFG_SHOW_SYMBOL	(0x0200)
#define PHY_LXT971_DIG_CFG_RES3 	(0x01FF)

#define PHY_LXT971_MDIO_MAX_CLK		(8000000)

/* TX_CTRL Transmit Control Register Bit Fields
   documentation is buggy for this register, therefore setting not included */

typedef enum
{
	PHY_NONE    = 0x0000, /* no PHY detected yet */
	PHY_LXT971A = 0x0013
} PhyType;

#define PHY_MDIO_MAX_CLK		(2500000)

#ifndef NS9750_ETH_PHY_ADDRESS
# define NS9750_ETH_PHY_ADDRESS	 	(0x0001) /* suitable for UNC20 */
#endif /* NETARM_ETH_PHY_ADDRESS */

#endif /* CONFIG_DRIVER_NS9750_ETHERNET */

#endif /* FS_NS9750_ETH_H */
Commit	Line	Data
80885a9d WD	1	/***********************************************************************
	2	*
	3	* Copyright (C) 2004 by FS Forth-Systeme GmbH.
	4	* All rights reserved.
	5	*
	6	* $Id: ns9750_eth.h,v 1.2 2004/02/24 13:25:39 mpietrek Exp $
	7	* @Author: Markus Pietrek
	8	* @References: [1] NS9750 Hardware Reference, December 2003
	9	* [2] Intel LXT971 Datasheet #249414 Rev. 02
	10	* [3] NS7520 Linux Ethernet Driver
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	* MA 02111-1307 USA
	26	*
	27	***********************************************************************/
	28
	29	#ifndef FS_NS9750_ETH_H
	30	#define FS_NS9750_ETH_H
	31
	32	#ifdef CONFIG_DRIVER_NS9750_ETHERNET
	33
	34	#define NS9750_ETH_MODULE_BASE (0xA0600000)
	35
	36	#define get_eth_reg_addr(c) \
	37	((volatile unsigned int*) ( NS9750_ETH_MODULE_BASE+(unsigned int) (c)))
	38
	39	#define NS9750_ETH_EGCR1 (0x0000)
	40	#define NS9750_ETH_EGCR2 (0x0004)
	41	#define NS9750_ETH_EGSR (0x0008)
	42	#define NS9750_ETH_FIFORX (0x000C)
	43	#define NS9750_ETH_FIFOTX (0x0010)
	44	#define NS9750_ETH_FIFOTXS (0x0014)
	45	#define NS9750_ETH_ETSR (0x0018)
	46	#define NS9750_ETH_ERSR (0x001C)
	47	#define NS9750_ETH_MAC1 (0x0400)
	48	#define NS9750_ETH_MAC2 (0x0404)
	49	#define NS9750_ETH_IPGT (0x0408)
	50	#define NS9750_ETH_IPGR (0x040C)
	51	#define NS9750_ETH_CLRT (0x0410)
	52	#define NS9750_ETH_MAXF (0x0414)
	53	#define NS9750_ETH_SUPP (0x0418)
	54	#define NS9750_ETH_TEST (0x041C)
	55	#define NS9750_ETH_MCFG (0x0420)
	56	#define NS9750_ETH_MCMD (0x0424)
	57	#define NS9750_ETH_MADR (0x0428)
	58	#define NS9750_ETH_MWTD (0x042C)
	59	#define NS9750_ETH_MRDD (0x0430)
	60	#define NS9750_ETH_MIND (0x0434)
	61	#define NS9750_ETH_SA1 (0x0440)
	62	#define NS9750_ETH_SA2 (0x0444)
	63	#define NS9750_ETH_SA3 (0x0448)
	64	#define NS9750_ETH_SAFR (0x0500)
65	#define NS9750_ETH_HT1 (0x0504)
66	#define NS9750_ETH_HT2 (0x0508)
67	#define NS9750_ETH_STAT_BASE (0x0680)
68	#define NS9750_ETH_RXAPTR (0x0A00)
69	#define NS9750_ETH_RXBPTR (0x0A04)
70	#define NS9750_ETH_RXCPTR (0x0A08)
71	#define NS9750_ETH_RXDPTR (0x0A0C)
72	#define NS9750_ETH_EINTR (0x0A10)
73	#define NS9750_ETH_EINTREN (0x0A14)
74	#define NS9750_ETH_TXPTR (0x0A18)
75	#define NS9750_ETH_TXRPTR (0x0A1C)
76	#define NS9750_ETH_TXERBD (0x0A20)
77	#define NS9750_ETH_TXSPTR (0x0A24)
78	#define NS9750_ETH_RXAOFF (0x0A28)
79	#define NS9750_ETH_RXBOFF (0x0A2C)
80	#define NS9750_ETH_RXCOFF (0x0A30)
81	#define NS9750_ETH_RXDOFF (0x0A34)
82	#define NS9750_ETH_TXOFF (0x0A38)
83	#define NS9750_ETH_RXFREE (0x0A3C)
84	#define NS9750_ETH_TXBD (0x1000)
85
86	/* register bit fields */
87
88	#define NS9750_ETH_EGCR1_ERX (0x80000000)
89	#define NS9750_ETH_EGCR1_ERXDMA (0x40000000)
90	#define NS9750_ETH_EGCR1_ERXSHT (0x10000000)
91	#define NS9750_ETH_EGCR1_ERXSIZ (0x08000000)
92	#define NS9750_ETH_EGCR1_ETXSIZ (0x04000000)
93	#define NS9750_ETH_EGCR1_ETXDIAG (0x02000000)
94	#define NS9750_ETH_EGCR1_ERXBAD (0x01000000)
95	#define NS9750_ETH_EGCR1_ETX (0x00800000)
96	#define NS9750_ETH_EGCR1_ETXDMA (0x00400000)
97	#define NS9750_ETH_EGCR1_ETXWM (0x00200000)
98	#define NS9750_ETH_EGCR1_ERXADV (0x00100000)
99	#define NS9750_ETH_EGCR1_ERXINIT (0x00080000)
100	#define NS9750_ETH_EGCR1_PHY_MODE_MA (0x0000C000)
101	#define NS9750_ETH_EGCR1_PHY_MODE_MII (0x00008000)
102	#define NS9750_ETH_EGCR1_PHY_MODE_RMII (0x00004000)
103	#define NS9750_ETH_EGCR1_RXCINV (0x00001000)
104	#define NS9750_ETH_EGCR1_TXCINV (0x00000800)
105	#define NS9750_ETH_EGCR1_RXALIGN (0x00000400)
106	#define NS9750_ETH_EGCR1_MAC_HRST (0x00000200)
107	#define NS9750_ETH_EGCR1_ITXA (0x00000100)
108
109	#define NS9750_ETH_EGCR2_TPTV_MA (0xFFFF0000)
110	#define NS9750_ETH_EGCR2_TPCF (0x00000040)
111	#define NS9750_ETH_EGCR2_THPDF (0x00000020)
112	#define NS9750_ETH_EGCR2_TCLER (0x00000008)
113	#define NS9750_ETH_EGCR2_AUTOZ (0x00000004)
114	#define NS9750_ETH_EGCR2_CLRCNT (0x00000002)
115	#define NS9750_ETH_EGCR2_STEN (0x00000001)
116
117	#define NS9750_ETH_EGSR_RXINIT (0x00100000)
118	#define NS9750_ETH_EGSR_TXFIFONF (0x00080000)
119	#define NS9750_ETH_EGSR_TXFIFOH (0x00040000)
120	#define NS9750_ETH_EGSR_TXFIFOE (0x00010000)
121
122	#define NS9750_ETH_FIFOTXS_ALL (0x00000055)
123	#define NS9750_ETH_FIFOTXS_3 (0x000000d5)
124	#define NS9750_ETH_FIFOTXS_2 (0x00000035)
125	#define NS9750_ETH_FIFOTXS_1 (0x0000000D)
126	#define NS9750_ETH_FIFOTXS_0 (0x00000003)
127
128	#define NS9750_ETH_ETSR_TXOK (0x00008000)
129	#define NS9750_ETH_ETSR_TXBR (0x00004000)
130	#define NS9750_ETH_ETSR_TXMC (0x00002000)
131	#define NS9750_ETH_ETSR_TXAL (0x00001000)
132	#define NS9750_ETH_ETSR_TXAED (0x00000800)
133	#define NS9750_ETH_ETSR_TXAEC (0x00000400)
134	#define NS9750_ETH_ETSR_TXAUR (0x00000200)
135	#define NS9750_ETH_ETSR_TXAJ (0x00000100)
136	#define NS9750_ETH_ETSR_TXDEF (0x00000040)
137	#define NS9750_ETH_ETSR_TXCRC (0x00000020)
138	#define NS9750_ETH_ETSR_TXCOLC (0x0000000F)
139
140	#define NS9750_ETH_ERSR_RXSIZE_MA (0x0FFF0000)
141	#define NS9750_ETH_ERSR_RXCE (0x00008000)
142	#define NS9750_ETH_ERSR_RXDV (0x00004000)
143	#define NS9750_ETH_ERSR_RXOK (0x00002000)
144	#define NS9750_ETH_ERSR_RXBR (0x00001000)
145	#define NS9750_ETH_ERSR_RXMC (0x00000800)
146	#define NS9750_ETH_ERSR_RXCRC (0x00000400)
147	#define NS9750_ETH_ERSR_RXDR (0x00000200)
148	#define NS9750_ETH_ERSR_RXCV (0x00000100)
149	#define NS9750_ETH_ERSR_RXSHT (0x00000040)
150
151	#define NS9750_ETH_MAC1_SRST (0x00008000)
152	#define NS9750_ETH_MAC1_SIMMRST (0x00004000)
153	#define NS9750_ETH_MAC1_RPEMCSR (0x00000800)
154	#define NS9750_ETH_MAC1_RPERFUN (0x00000400)
155	#define NS9750_ETH_MAC1_RPEMCST (0x00000200)
156	#define NS9750_ETH_MAC1_RPETFUN (0x00000100)
157	#define NS9750_ETH_MAC1_LOOPBK (0x00000010)
158	#define NS9750_ETH_MAC1_TXFLOW (0x00000008)
159	#define NS9750_ETH_MAC1_RXFLOW (0x00000004)
160	#define NS9750_ETH_MAC1_PALLRX (0x00000002)
161	#define NS9750_ETH_MAC1_RXEN (0x00000001)
162
163	#define NS9750_ETH_MAC2_EDEFER (0x00004000)
164	#define NS9750_ETH_MAC2_BACKP (0x00002000)
165	#define NS9750_ETH_MAC2_NOBO (0x00001000)
166	#define NS9750_ETH_MAC2_LONGP (0x00000200)
167	#define NS9750_ETH_MAC2_PUREP (0x00000100)
168	#define NS9750_ETH_MAC2_AUTOP (0x00000080)
169	#define NS9750_ETH_MAC2_VLANP (0x00000040)
170	#define NS9750_ETH_MAC2_PADEN (0x00000020)
171	#define NS9750_ETH_MAC2_CRCEN (0x00000010)
172	#define NS9750_ETH_MAC2_DELCRC (0x00000008)
173	#define NS9750_ETH_MAC2_HUGE (0x00000004)
174	#define NS9750_ETH_MAC2_FLENC (0x00000002)
175	#define NS9750_ETH_MAC2_FULLD (0x00000001)
176
177	#define NS9750_ETH_IPGT_MA (0x0000007F)
178
179	#define NS9750_ETH_IPGR_IPGR1 (0x00007F00)
180	#define NS9750_ETH_IPGR_IPGR2 (0x0000007F)
181
182	#define NS9750_ETH_CLRT_CWIN (0x00003F00)
183	#define NS9750_ETH_CLRT_RETX (0x0000000F)
184
185	#define NS9750_ETH_MAXF_MAXF (0x0000FFFF)
186
187	#define NS9750_ETH_SUPP_RPERMII (0x00008000)
188	#define NS9750_ETH_SUPP_SPEED (0x00000080)
189
190	#define NS9750_ETH_TEST_TBACK (0x00000004)
191	#define NS9750_ETH_TEST_TPAUSE (0x00000002)
192	#define NS9750_ETH_TEST_SPQ (0x00000001)
193
194	#define NS9750_ETH_MCFG_RMIIM (0x00008000)
195	#define NS9750_ETH_MCFG_CLKS_MA (0x0000001C)
196	#define NS9750_ETH_MCFG_CLKS_4 (0x00000004)
197	#define NS9750_ETH_MCFG_CLKS_6 (0x00000008)
198	#define NS9750_ETH_MCFG_CLKS_8 (0x0000000C)
199	#define NS9750_ETH_MCFG_CLKS_10 (0x00000010)
200	#define NS9750_ETH_MCFG_CLKS_20 (0x00000014)
201	#define NS9750_ETH_MCFG_CLKS_30 (0x00000018)
202	#define NS9750_ETH_MCFG_CLKS_40 (0x0000001C)
203	#define NS9750_ETH_MCFG_SPRE (0x00000002)
204	#define NS9750_ETH_MCFG_SCANI (0x00000001)
205
206	#define NS9750_ETH_MCMD_SCAN (0x00000002)
207	#define NS9750_ETH_MCMD_READ (0x00000001)
208
209	#define NS9750_ETH_MADR_DADR_MA (0x00001F00)
210	#define NS9750_ETH_MADR_RADR_MA (0x0000001F)
211
212	#define NS9750_ETH_MWTD_MA (0x0000FFFF)
213
214	#define NS9750_ETH_MRRD_MA (0x0000FFFF)
215
216	#define NS9750_ETH_MIND_MIILF (0x00000008)
217	#define NS9750_ETH_MIND_NVALID (0x00000004)
218	#define NS9750_ETH_MIND_SCAN (0x00000002)
219	#define NS9750_ETH_MIND_BUSY (0x00000001)
220
221	#define NS9750_ETH_SA1_OCTET1_MA (0x0000FF00)
222	#define NS9750_ETH_SA1_OCTET2_MA (0x000000FF)
223
224	#define NS9750_ETH_SA2_OCTET3_MA (0x0000FF00)
225	#define NS9750_ETH_SA2_OCTET4_MA (0x000000FF)
226
227	#define NS9750_ETH_SA3_OCTET5_MA (0x0000FF00)
228	#define NS9750_ETH_SA3_OCTET6_MA (0x000000FF)
229
230	#define NS9750_ETH_SAFR_PRO (0x00000008)
231	#define NS9750_ETH_SAFR_PRM (0x00000004)
232	#define NS9750_ETH_SAFR_PRA (0x00000002)
233	#define NS9750_ETH_SAFR_BROAD (0x00000001)
234
235	#define NS9750_ETH_HT1_MA (0x0000FFFF)
236
237	#define NS9750_ETH_HT2_MA (0x0000FFFF)
238
239	/* also valid for EINTREN */
240	#define NS9750_ETH_EINTR_RXOVL_DATA (0x02000000)
241	#define NS9750_ETH_EINTR_RXOVL_STAT (0x01000000)
242	#define NS9750_ETH_EINTR_RXBUFC (0x00800000)
243	#define NS9750_ETH_EINTR_RXDONEA (0x00400000)
244	#define NS9750_ETH_EINTR_RXDONEB (0x00200000)
245	#define NS9750_ETH_EINTR_RXDONEC (0x00100000)
246	#define NS9750_ETH_EINTR_RXDONED (0x00080000)
247	#define NS9750_ETH_EINTR_RXNOBUF (0x00040000)
248	#define NS9750_ETH_EINTR_RXBUFFUL (0x00020000)
249	#define NS9750_ETH_EINTR_RXBR (0x00010000)
250	#define NS9750_ETH_EINTR_STOVFL (0x00000040)
251	#define NS9750_ETH_EINTR_TXPAUSE (0x00000020)
252	#define NS9750_ETH_EINTR_TXBUFC (0x00000010)
253	#define NS9750_ETH_EINTR_TXBUFNR (0x00000008)
254	#define NS9750_ETH_EINTR_TXDONE (0x00000004)
255	#define NS9750_ETH_EINTR_TXERR (0x00000002)
256	#define NS9750_ETH_EINTR_TXIDLE (0x00000001)
257	#define NS9750_ETH_EINTR_RX_MA \
258	(NS9750_ETH_EINTR_RXOVL_DATA \| \
259	NS9750_ETH_EINTR_RXOVL_STAT \| \
260	NS9750_ETH_EINTR_RXBUFC \| \
261	NS9750_ETH_EINTR_RXDONEA \| \
262	NS9750_ETH_EINTR_RXDONEB \| \
263	NS9750_ETH_EINTR_RXDONEC \| \
264	NS9750_ETH_EINTR_RXDONED \| \
265	NS9750_ETH_EINTR_RXNOBUF \| \
266	NS9750_ETH_EINTR_RXBUFFUL \| \
267	NS9750_ETH_EINTR_RXBR )
268	#define NS9750_ETH_EINTR_TX_MA \
269	(NS9750_ETH_EINTR_TXPAUSE \| \
270	NS9750_ETH_EINTR_TXBUFC \| \
271	NS9750_ETH_EINTR_TXBUFNR \| \
272	NS9750_ETH_EINTR_TXDONE \| \
273	NS9750_ETH_EINTR_TXERR \| \
274	NS9750_ETH_EINTR_TXIDLE)
275
276	/* for TXPTR, TXRPTR, TXERBD and TXSPTR */
277	#define NS9750_ETH_TXPTR_MA (0x000000FF)
278
279	/* for RXAOFF, RXBOFF, RXCOFF and RXDOFF */
280	#define NS9750_ETH_RXOFF_MA (0x000007FF)
281
282	#define NS9750_ETH_TXOFF_MA (0x000003FF)
283
284	#define NS9750_ETH_RXFREE_D (0x00000008)
285	#define NS9750_ETH_RXFREE_C (0x00000004)
286	#define NS9750_ETH_RXFREE_B (0x00000002)
287	#define NS9750_ETH_RXFREE_A (0x00000001)
288
289	/* PHY definitions (LXT971A) [2] */
290
291	#define PHY_COMMON_CTRL (0x00)
292	#define PHY_COMMON_STAT (0x01)
293	#define PHY_COMMON_ID1 (0x02)
294	#define PHY_COMMON_ID2 (0x03)
295	#define PHY_COMMON_AUTO_ADV (0x04)
296	#define PHY_COMMON_AUTO_LNKB (0x05)
297	#define PHY_COMMON_AUTO_EXP (0x06)
298	#define PHY_COMMON_AUTO_NEXT (0x07)
299	#define PHY_COMMON_AUTO_LNKN (0x08)
300	#define PHY_LXT971_PORT_CFG (0x10)
301	#define PHY_LXT971_STAT2 (0x11)
302	#define PHY_LXT971_INT_ENABLE (0x12)
303	#define PHY_LXT971_INT_STATUS (0x13)
304	#define PHY_LXT971_LED_CFG (0x14)
305	#define PHY_LXT971_DIG_CFG (0x1A)
306	#define PHY_LXT971_TX_CTRL (0x1E)
307
308	/* CTRL PHY Control Register Bit Fields */
309
310	#define PHY_COMMON_CTRL_RESET (0x8000)
311	#define PHY_COMMON_CTRL_LOOPBACK (0x4000)
312	#define PHY_COMMON_CTRL_SPD_MA (0x2040)
313	#define PHY_COMMON_CTRL_SPD_10 (0x0000)
314	#define PHY_COMMON_CTRL_SPD_100 (0x2000)
315	#define PHY_COMMON_CTRL_SPD_1000 (0x0040)
316	#define PHY_COMMON_CTRL_SPD_RES (0x2040)
317	#define PHY_COMMON_CTRL_AUTO_NEG (0x1000)
318	#define PHY_COMMON_CTRL_POWER_DN (0x0800)
319	#define PHY_COMMON_CTRL_ISOLATE (0x0400)
320	#define PHY_COMMON_CTRL_RES_AUTO (0x0200)
321	#define PHY_COMMON_CTRL_DUPLEX (0x0100)
322	#define PHY_COMMON_CTRL_COL_TEST (0x0080)
323	#define PHY_COMMON_CTRL_RES1 (0x003F)
324
325	/* STAT Status Register Bit Fields */
326
327	#define PHY_COMMON_STAT_100BT4 (0x8000)
328	#define PHY_COMMON_STAT_100BXFD (0x4000)
329	#define PHY_COMMON_STAT_100BXHD (0x2000)
330	#define PHY_COMMON_STAT_10BTFD (0x1000)
331	#define PHY_COMMON_STAT_10BTHD (0x0800)
332	#define PHY_COMMON_STAT_100BT2FD (0x0400)
333	#define PHY_COMMON_STAT_100BT2HD (0x0200)
334	#define PHY_COMMON_STAT_EXT_STAT (0x0100)
335	#define PHY_COMMON_STAT_RES1 (0x0080)
336	#define PHY_COMMON_STAT_MF_PSUP (0x0040)
337	#define PHY_COMMON_STAT_AN_COMP (0x0020)
338	#define PHY_COMMON_STAT_RMT_FLT (0x0010)
339	#define PHY_COMMON_STAT_AN_CAP (0x0008)
340	#define PHY_COMMON_STAT_LNK_STAT (0x0004)
341	#define PHY_COMMON_STAT_JAB_DTCT (0x0002)
342	#define PHY_COMMON_STAT_EXT_CAP (0x0001)
343
344
345	/* AUTO_ADV Auto-neg Advert Register Bit Fields */
346
347	#define PHY_COMMON_AUTO_ADV_NP (0x8000)
348	#define PHY_COMMON_AUTO_ADV_RES1 (0x4000)
349	#define PHY_COMMON_AUTO_ADV_RMT_FLT (0x2000)
350	#define PHY_COMMON_AUTO_ADV_RES2 (0x1000)
351	#define PHY_COMMON_AUTO_ADV_AS_PAUSE (0x0800)
352	#define PHY_COMMON_AUTO_ADV_PAUSE (0x0400)
353	#define PHY_COMMON_AUTO_ADV_100BT4 (0x0200)
354	#define PHY_COMMON_AUTO_ADV_100BTXFD (0x0100)
355	#define PHY_COMMON_AUTO_ADV_100BTX (0x0080)
356	#define PHY_COMMON_AUTO_ADV_10BTFD (0x0040)
357	#define PHY_COMMON_AUTO_ADV_10BT (0x0020)
358	#define PHY_COMMON_AUTO_ADV_SEL_FLD_MA (0x001F)
359	#define PHY_COMMON_AUTO_ADV_802_9 (0x0002)
360	#define PHY_COMMON_AUTO_ADV_802_3 (0x0001)
361
362	/* AUTO_LNKB Auto-neg Link Ability Register Bit Fields */
363
364	#define PHY_COMMON_AUTO_LNKB_NP (0x8000)
365	#define PHY_COMMON_AUTO_LNKB_ACK (0x4000)
366	#define PHY_COMMON_AUTO_LNKB_RMT_FLT (0x2000)
367	#define PHY_COMMON_AUTO_LNKB_RES2 (0x1000)
368	#define PHY_COMMON_AUTO_LNKB_AS_PAUSE (0x0800)
369	#define PHY_COMMON_AUTO_LNKB_PAUSE (0x0400)
370	#define PHY_COMMON_AUTO_LNKB_100BT4 (0x0200)
371	#define PHY_COMMON_AUTO_LNKB_100BTXFD (0x0100)
372	#define PHY_COMMON_AUTO_LNKB_100BTX (0x0080)
373	#define PHY_COMMON_AUTO_LNKB_10BTFD (0x0040)
374	#define PHY_COMMON_AUTO_LNKB_10BT (0x0020)
375	#define PHY_COMMON_AUTO_LNKB_SEL_FLD_MA (0x001F)
376	#define PHY_COMMON_AUTO_LNKB_802_9 (0x0002)
377	#define PHY_COMMON_AUTO_LNKB_802_3 (0x0001)
378
379	/* AUTO_EXP Auto-neg Expansion Register Bit Fields */
380
381	#define PHY_COMMON_AUTO_EXP_RES1 (0xFFC0)
382	#define PHY_COMMON_AUTO_EXP_BASE_PAGE (0x0020)
383	#define PHY_COMMON_AUTO_EXP_PAR_DT_FLT (0x0010)
384	#define PHY_COMMON_AUTO_EXP_LNK_NP_CAP (0x0008)
385	#define PHY_COMMON_AUTO_EXP_NP_CAP (0x0004)
386	#define PHY_COMMON_AUTO_EXP_PAGE_REC (0x0002)
387	#define PHY_COMMON_AUTO_EXP_LNK_AN_CAP (0x0001)
388
389	/* AUTO_NEXT Aut-neg Next Page Tx Register Bit Fields */
390
391	#define PHY_COMMON_AUTO_NEXT_NP (0x8000)
392	#define PHY_COMMON_AUTO_NEXT_RES1 (0x4000)
393	#define PHY_COMMON_AUTO_NEXT_MSG_PAGE (0x2000)
394	#define PHY_COMMON_AUTO_NEXT_ACK_2 (0x1000)
395	#define PHY_COMMON_AUTO_NEXT_TOGGLE (0x0800)
396	#define PHY_COMMON_AUTO_NEXT_MSG (0x07FF)
397
398	/* AUTO_LNKN Auto-neg Link Partner Rx Reg Bit Fields */
399
400	#define PHY_COMMON_AUTO_LNKN_NP (0x8000)
401	#define PHY_COMMON_AUTO_LNKN_ACK (0x4000)
402	#define PHY_COMMON_AUTO_LNKN_MSG_PAGE (0x2000)
403	#define PHY_COMMON_AUTO_LNKN_ACK_2 (0x1000)
404	#define PHY_COMMON_AUTO_LNKN_TOGGLE (0x0800)
405	#define PHY_COMMON_AUTO_LNKN_MSG (0x07FF)
406
407	/* PORT_CFG Port Configuration Register Bit Fields */
408
409	#define PHY_LXT971_PORT_CFG_RES1 (0x8000)
410	#define PHY_LXT971_PORT_CFG_FORCE_LNK (0x4000)
411	#define PHY_LXT971_PORT_CFG_TX_DISABLE (0x2000)
412	#define PHY_LXT971_PORT_CFG_BYPASS_SCR (0x1000)
413	#define PHY_LXT971_PORT_CFG_RES2 (0x0800)
414	#define PHY_LXT971_PORT_CFG_JABBER (0x0400)
415	#define PHY_LXT971_PORT_CFG_SQE (0x0200)
416	#define PHY_LXT971_PORT_CFG_TP_LOOPBACK (0x0100)
417	#define PHY_LXT971_PORT_CFG_CRS_SEL (0x0080)
418	#define PHY_LXT971_PORT_CFG_SLEEP_MODE (0x0040)
419	#define PHY_LXT971_PORT_CFG_PRE_EN (0x0020)
420	#define PHY_LXT971_PORT_CFG_SLEEP_T_MA (0x0018)
421	#define PHY_LXT971_PORT_CFG_SLEEP_T_104 (0x0010)
422	#define PHY_LXT971_PORT_CFG_SLEEP_T_200 (0x0001)
423	#define PHY_LXT971_PORT_CFG_SLEEP_T_304 (0x0000)
424	#define PHY_LXT971_PORT_CFG_FLT_CODE_EN (0x0004)
425	#define PHY_LXT971_PORT_CFG_ALT_NP (0x0002)
426	#define PHY_LXT971_PORT_CFG_FIBER_SEL (0x0001)
427
428	/* STAT2 Status Register #2 Bit Fields */
429
430	#define PHY_LXT971_STAT2_RES1 (0x8000)
431	#define PHY_LXT971_STAT2_100BTX (0x4000)
432	#define PHY_LXT971_STAT2_TX_STATUS (0x2000)
433	#define PHY_LXT971_STAT2_RX_STATUS (0x1000)
434	#define PHY_LXT971_STAT2_COL_STATUS (0x0800)
435	#define PHY_LXT971_STAT2_LINK (0x0400)
436	#define PHY_LXT971_STAT2_DUPLEX_MODE (0x0200)
437	#define PHY_LXT971_STAT2_AUTO_NEG (0x0100)
438	#define PHY_LXT971_STAT2_AUTO_NEG_COMP (0x0080)
439	#define PHY_LXT971_STAT2_RES2 (0x0040)
440	#define PHY_LXT971_STAT2_POLARITY (0x0020)
441	#define PHY_LXT971_STAT2_PAUSE (0x0010)
442	#define PHY_LXT971_STAT2_ERROR (0x0008)
443	#define PHY_LXT971_STAT2_RES3 (0x0007)
444
445	/* INT_ENABLE Interrupt Enable Register Bit Fields */
446
447	#define PHY_LXT971_INT_ENABLE_RES1 (0xFF00)
448	#define PHY_LXT971_INT_ENABLE_ANMSK (0x0080)
449	#define PHY_LXT971_INT_ENABLE_SPEEDMSK (0x0040)
450	#define PHY_LXT971_INT_ENABLE_DUPLEXMSK (0x0020)
451	#define PHY_LXT971_INT_ENABLE_LINKMSK (0x0010)
452	#define PHY_LXT971_INT_ENABLE_RES2 (0x000C)
453	#define PHY_LXT971_INT_ENABLE_INTEN (0x0002)
454	#define PHY_LXT971_INT_ENABLE_TINT (0x0001)
455
456	/* INT_STATUS Interrupt Status Register Bit Fields */
457
458	#define PHY_LXT971_INT_STATUS_RES1 (0xFF00)
459	#define PHY_LXT971_INT_STATUS_ANDONE (0x0080)
460	#define PHY_LXT971_INT_STATUS_SPEEDCHG (0x0040)
461	#define PHY_LXT971_INT_STATUS_DUPLEXCHG (0x0020)
462	#define PHY_LXT971_INT_STATUS_LINKCHG (0x0010)
463	#define PHY_LXT971_INT_STATUS_RES2 (0x0008)
464	#define PHY_LXT971_INT_STATUS_MDINT (0x0004)
465	#define PHY_LXT971_INT_STATUS_RES3 (0x0003)
466
467	/* LED_CFG Interrupt LED Configuration Register Bit Fields */
468
469	#define PHY_LXT971_LED_CFG_SHIFT_LED1 (0x000C)
470	#define PHY_LXT971_LED_CFG_SHIFT_LED2 (0x0008)
471	#define PHY_LXT971_LED_CFG_SHIFT_LED3 (0x0004)
472	#define PHY_LXT971_LED_CFG_LEDFREQ_MA (0x000C)
473	#define PHY_LXT971_LED_CFG_LEDFREQ_RES (0x000C)
474	#define PHY_LXT971_LED_CFG_LEDFREQ_100 (0x0008)
475	#define PHY_LXT971_LED_CFG_LEDFREQ_60 (0x0004)
476	#define PHY_LXT971_LED_CFG_LEDFREQ_30 (0x0000)
477	#define PHY_LXT971_LED_CFG_PULSE_STR (0x0002)
478	#define PHY_LXT971_LED_CFG_RES1 (0x0001)
479
480	/* only one of these values must be shifted for each SHIFT_LED? */
481
482	#define PHY_LXT971_LED_CFG_UNUSED1 (0x000F)
483	#define PHY_LXT971_LED_CFG_DUPLEX_COL (0x000E)
484	#define PHY_LXT971_LED_CFG_LINK_ACT (0x000D)
485	#define PHY_LXT971_LED_CFG_LINK_RX (0x000C)
486	#define PHY_LXT971_LED_CFG_TEST_BLK_SLW (0x000B)
487	#define PHY_LXT971_LED_CFG_TEST_BLK_FST (0x000A)
488	#define PHY_LXT971_LED_CFG_TEST_OFF (0x0009)
489	#define PHY_LXT971_LED_CFG_TEST_ON (0x0008)
490	#define PHY_LXT971_LED_CFG_RX_OR_TX (0x0007)
491	#define PHY_LXT971_LED_CFG_UNUSED2 (0x0006)
492	#define PHY_LXT971_LED_CFG_DUPLEX (0x0005)
493	#define PHY_LXT971_LED_CFG_LINK (0x0004)
494	#define PHY_LXT971_LED_CFG_COLLISION (0x0003)
495	#define PHY_LXT971_LED_CFG_RECEIVE (0x0002)
496	#define PHY_LXT971_LED_CFG_TRANSMIT (0x0001)
497	#define PHY_LXT971_LED_CFG_SPEED (0x0000)
498
499	/* DIG_CFG Digitial Configuration Register Bit Fields */
500
501	#define PHY_LXT971_DIG_CFG_RES1 (0xF000)
502	#define PHY_LXT971_DIG_CFG_MII_DRIVE (0x0800)
503	#define PHY_LXT971_DIG_CFG_RES2 (0x0400)
504	#define PHY_LXT971_DIG_CFG_SHOW_SYMBOL (0x0200)
505	#define PHY_LXT971_DIG_CFG_RES3 (0x01FF)
506
507	#define PHY_LXT971_MDIO_MAX_CLK (8000000)
508
509	/* TX_CTRL Transmit Control Register Bit Fields
510	documentation is buggy for this register, therefore setting not included */
511
512	typedef enum
513	{
514	PHY_NONE = 0x0000, /* no PHY detected yet */
515	PHY_LXT971A = 0x0013
516	} PhyType;
517
518	#define PHY_MDIO_MAX_CLK (2500000)
519
520	#ifndef NS9750_ETH_PHY_ADDRESS
521	# define NS9750_ETH_PHY_ADDRESS (0x0001) /* suitable for UNC20 */
522	#endif /* NETARM_ETH_PHY_ADDRESS */
523
524	#endif /* CONFIG_DRIVER_NS9750_ETHERNET */
525
526	#endif /* FS_NS9750_ETH_H */