[u-boot.git] / include / configs / eXalion.h

/*
 * (C) Copyright 2001
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/* ------------------------------------------------------------------------- */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC824X		1
/* #define CONFIG_MPC8240	   1 */
#define CONFIG_MPC8245		1
#define CONFIG_EXALION		1

#if defined (CONFIG_MPC8240)
    /* #warning	 ---------- eXalion with MPC8240 --------------- */
#elif defined (CONFIG_MPC8245)
    /* #warning	 ++++++++++ eXalion with MPC8245 +++++++++++++++ */
#elif defined (CONFIG_MPC8245) && defined (CONFIG_MPC8245)
#error #### Both types of MPC824x defined (CONFIG_8240 and CONFIG_8245)
#else
#error #### Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
#endif
/* older kernels need clock in MHz newer in Hz */
					/* #define CONFIG_CLOCKS_IN_MHZ 1 *//* clocks passsed to Linux in MHz	    */
#undef CONFIG_CLOCKS_IN_MHZ

#define CONFIG_BOOTDELAY	10


						    /*#define CONFIG_DRAM_SPEED	      66   *//* MHz			     */

#define CONFIG_COMMANDS		(   CONFIG_CMD_DFL  | \
				    CFG_CMD_FLASH   | \
				    CFG_CMD_SDRAM   | \
				    CFG_CMD_I2C	    | \
				    CFG_CMD_IDE	    | \
				    CFG_CMD_FAT	    | \
				    CFG_CMD_ENV	    | \
				    CFG_CMD_PCI )

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any)	*/
#include <cmd_confdefs.h>


/*-----------------------------------------------------------------------
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP		1	/* undef to save memory		*/
#define CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
#define CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size	*/
#define CFG_MAXARGS		8	/* max number of command args	*/
#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
#define CFG_LOAD_ADDR		0x00100000	/* default load address		*/

#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

#define CONFIG_MISC_INIT_R	1

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define CFG_SDRAM_BASE		0x00000000
#define CFG_MAX_RAM_SIZE	0x10000000	/* 1 GBytes - initdram() will	   */
					     /* return real value.		*/

#define CFG_RESET_ADDRESS	0xFFF00100

#undef	CFG_RAMBOOT
#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	    */
#define CFG_MONITOR_BASE	TEXT_BASE

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area
 */
#define CFG_INIT_DATA_SIZE	128

#define CFG_INIT_RAM_ADDR	0x40000000
#define CFG_INIT_RAM_END	0x1000
#define CFG_INIT_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)

#define CFG_GBL_DATA_SIZE	 256	/* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET


#if defined (CONFIG_MPC8240)
#define CFG_FLASH_BASE	    0xFFE00000
#define CFG_FLASH_SIZE	    (2 * 1024 * 1024)	/* onboard 2MByte flash	    */
#elif defined (CONFIG_MPC8245)
#define CFG_FLASH_BASE	    0xFFC00000
#define CFG_FLASH_SIZE	    (4 * 1024 * 1024)	/* onboard 4MByte flash	    */
#else
#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
#endif

#define CFG_ENV_IS_IN_FLASH	1
#define CFG_ENV_SECT_SIZE	0x20000 /* Size of one Flash sector */
#define CFG_ENV_SIZE		CFG_ENV_SECT_SIZE	/* Use one Flash sector for enviroment	*/
#define CFG_ENV_ADDR		0xFFFC0000
#define CFG_ENV_OFFSET		0	/* starting right at the beginning  */

#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/

#define CFG_ALT_MEMTEST		1	/* use real memory test	    */
#define CFG_MEMTEST_START	0x00004000	/* memtest works on	    */
#define CFG_MEMTEST_END		0x02000000	/* 0 ... 32 MB in DRAM	    */

#define CFG_EUMB_ADDR		0xFC000000

/* #define CFG_ISA_MEM		   0xFD000000 */
#define CFG_ISA_IO		0xFE000000

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	1	/* Max number of flash banks	    */
#define CFG_MAX_FLASH_SECT	64	/* Max number of sectors per flash  */

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */

#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE
#define FLASH_BASE1_PRELIM	0


/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */

#define CFG_FLASH_CFI		1	/* Flash is CFI conformant		*/
#define CFG_FLASH_CFI_DRIVER	1	/* Use the common driver		*/
#define CFG_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CFG_FLASH_INCREMENT	0	/* there is only one bank		*/
#define CFG_FLASH_PROTECTION	1	/* use hardware protection		*/
#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/


/*-----------------------------------------------------------------------
 * PCI stuff
 */
#define CONFIG_PCI		1	/* include pci support		*/
#undef	CONFIG_PCI_PNP

#define CONFIG_NET_MULTI	1	/* Multi ethernet cards support */

#define CONFIG_EEPRO100		1

#define PCI_ENET0_MEMADDR	0x80000000	/* Intel 82559ER */
#define PCI_ENET0_IOADDR	0x80000000
#define PCI_ENET1_MEMADDR	0x81000000	/* Intel 82559ER */
#define PCI_ENET1_IOADDR	0x81000000
#define PCI_ENET2_MEMADDR	0x82000000	/* Broadcom BCM569xx */
#define PCI_ENET2_IOADDR	0x82000000
#define PCI_ENET3_MEMADDR	0x83000000	/* Broadcom BCM56xx */
#define PCI_ENET3_IOADDR	0x83000000

/*-----------------------------------------------------------------------
 * NS16550 Configuration
 */
#define CFG_NS16550		1
#define CFG_NS16550_SERIAL	1

#define CONFIG_CONS_INDEX	1
#define CONFIG_BAUDRATE		38400

#define CFG_NS16550_REG_SIZE	1

#if (CONFIG_CONS_INDEX == 1)
#define CFG_NS16550_CLK		1843200 /* COM1 only !	*/
#else
#define CFG_NS16550_CLK ({ extern ulong get_bus_freq (ulong); get_bus_freq (0); })
#endif

#define CFG_NS16550_COM1	(CFG_ISA_IO + 0x3F8)
#define CFG_NS16550_COM2	(CFG_EUMB_ADDR + 0x4500)
#define CFG_NS16550_COM3	(CFG_EUMB_ADDR + 0x4600)

/*-----------------------------------------------------------------------
 * select i2c support configuration
 *
 * Supported configurations are {none, software, hardware} drivers.
 * If the software driver is chosen, there are some additional
 * configuration items that the driver uses to drive the port pins.
 */
#define CONFIG_HARD_I2C		1	/* To enable I2C support	*/
#undef	CONFIG_SOFT_I2C		/* I2C bit-banged		*/
#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
#define CFG_I2C_SLAVE		0x7F

/*-----------------------------------------------------------------------
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
#define CFG_HZ			1000

#define CONFIG_SYS_CLK_FREQ	33333333	/* external frequency to pll	*/
#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER  2	/* for MPC8240 only		*/

				       /*#define CONFIG_133MHZ_DRAM	 1 *//* For 133 MHZ DRAM only !!!!!!!!!!!    */

#if defined (CONFIG_MPC8245)
/* Bit-field values for PMCR2.							*/
#if defined (CONFIG_133MHZ_DRAM)
#define CFG_DLL_EXTEND		0x80	/* use DLL extended range - 133MHz only */
#define CFG_PCI_HOLD_DEL	0x20	/* delay and hold timing - 133MHz only	*/
#endif

/* Bit-field values for MIOCR1.							*/
#if !defined (CONFIG_133MHZ_DRAM)
#define CFG_DLL_MAX_DELAY	0x04	/*  longer DLL delay line - 66MHz only	*/
#endif
/* Bit-field values for MIOCR2.							*/
#define CFG_SDRAM_DSCD		0x20	/* SDRAM data in sample clock delay	*/
					/*	- note bottom 3 bits MUST be 0	*/
#endif

/* Bit-field values for MCCR1.							*/
#define CFG_ROMNAL		7	/*rom/flash next access time		*/
#define CFG_ROMFAL	       11	/*rom/flash access time			*/

/* Bit-field values for MCCR2.							*/
#define CFG_TSWAIT		0x5	/* Transaction Start Wait States timer	*/
#if defined (CONFIG_133MHZ_DRAM)
#define CFG_REFINT		1300	/* no of clock cycles between CBR	*/
#else  /* refresh cycles */
#define CFG_REFINT		750
#endif

/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.		*/
#if defined (CONFIG_133MHZ_DRAM)
#define CFG_BSTOPRE		1023
#else
#define CFG_BSTOPRE		250
#endif

/* Bit-field values for MCCR3.							*/
/* the following are for SDRAM only						*/

#if defined (CONFIG_133MHZ_DRAM)
#define CFG_REFREC		9	/* Refresh to activate interval		*/
#else
#define CFG_REFREC		5	/* Refresh to activate interval		*/
#endif
#if defined (CONFIG_MPC8240)
#define CFG_RDLAT		2	/* data latency from read command	*/
#endif

/* Bit-field values for MCCR4.	*/
#if defined (CONFIG_133MHZ_DRAM)
#define CFG_PRETOACT		3	/* Precharge to activate interval	*/
#define CFG_ACTTOPRE		7	/* Activate to Precharge interval	*/
#define CFG_ACTORW		5	/* Activate to R/W			*/
#define CFG_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
#else
#if 0
#define CFG_PRETOACT		2	/* Precharge to activate interval	*/
#define CFG_ACTTOPRE		3	/* Activate to Precharge interval	*/
#define CFG_ACTORW		3	/* Activate to R/W			*/
#define CFG_SDMODE_CAS_LAT	2	/* SDMODE CAS latency			*/
#endif
#define CFG_PRETOACT		2	/* Precharge to activate interval	*/
#define CFG_ACTTOPRE		5	/* Activate to Precharge interval	*/
#define CFG_ACTORW		3	/* Activate to R/W			*/
#define CFG_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
#endif
#define CFG_SDMODE_WRAP		0	/* SDMODE wrap type			*/
#define CFG_SDMODE_BURSTLEN	2	/* SDMODE Burst length 2=4, 3=8		*/
#define CFG_REGDIMM		0
#if defined (CONFIG_MPC8240)
#define CFG_REGISTERD_TYPE_BUFFER   0
#elif defined (CONFIG_MPC8245)
#define CFG_REGISTERD_TYPE_BUFFER   1
#define CFG_EXTROM		    0
#else
#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
#endif


/*-----------------------------------------------------------------------
 memory bank settings
 * only bits 20-29 are actually used from these vales to set the
 * start/end address the upper two bits will be 0, and the lower 20
 * bits will be set to 0x00000 for a start address, or 0xfffff for an
 * end address
 */
#define CFG_BANK0_START		0x00000000
#define CFG_BANK0_END		(CFG_MAX_RAM_SIZE - 1)
#define CFG_BANK0_ENABLE	1
#define CFG_BANK1_START		0x3ff00000
#define CFG_BANK1_END		0x3fffffff
#define CFG_BANK1_ENABLE	0
#define CFG_BANK2_START		0x3ff00000
#define CFG_BANK2_END		0x3fffffff
#define CFG_BANK2_ENABLE	0
#define CFG_BANK3_START		0x3ff00000
#define CFG_BANK3_END		0x3fffffff
#define CFG_BANK3_ENABLE	0
#define CFG_BANK4_START		0x00000000
#define CFG_BANK4_END		0x00000000
#define CFG_BANK4_ENABLE	0
#define CFG_BANK5_START		0x00000000
#define CFG_BANK5_END		0x00000000
#define CFG_BANK5_ENABLE	0
#define CFG_BANK6_START		0x00000000
#define CFG_BANK6_END		0x00000000
#define CFG_BANK6_ENABLE	0
#define CFG_BANK7_START		0x00000000
#define CFG_BANK7_END		0x00000000
#define CFG_BANK7_ENABLE	0

/*-----------------------------------------------------------------------
 * Memory bank enable bitmask, specifying which of the banks defined above
 are actually present. MSB is for bank #7, LSB is for bank #0.
 */
#define CFG_BANK_ENABLE		0x01

#if defined (CONFIG_MPC8240)
#define CFG_ODCR		0xDF	/* configures line driver impedances,	*/
					/* see 8240 book for bit definitions	*/
#elif defined (CONFIG_MPC8245)
#if defined (CONFIG_133MHZ_DRAM)
#define CFG_ODCR		0xFE	/* configures line driver impedances - 133MHz	*/
#else
#define CFG_ODCR		0xDE	/* configures line driver impedances - 66MHz	*/
#endif
#else
#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
#endif

#define CFG_PGMAX		0x32	/* how long the 8240 retains the	*/
					/* currently accessed page in memory	*/
					/* see 8240 book for details		*/

/*-----------------------------------------------------------------------
 * Block Address Translation (BAT) register settings.
 */
/* SDRAM 0 - 256MB */
#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)

/* stack in DCACHE @ 1GB (no backing mem) */
#define CFG_IBAT1L	(CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT1U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)

/* PCI memory */
#define CFG_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CFG_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)

/* Flash, config addrs, etc */
#define CFG_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CFG_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)

#define CFG_DBAT0L	CFG_IBAT0L
#define CFG_DBAT0U	CFG_IBAT0U
#define CFG_DBAT1L	CFG_IBAT1L
#define CFG_DBAT1U	CFG_IBAT1U
#define CFG_DBAT2L	CFG_IBAT2L
#define CFG_DBAT2U	CFG_IBAT2U
#define CFG_DBAT3L	CFG_IBAT3L
#define CFG_DBAT3U	CFG_IBAT3U


/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE	32
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif


/*-----------------------------------------------------------------------
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM		0x02	/* Software reboot			*/


/* values according to the manual */
#define CONFIG_DRAM_50MHZ	1
#define CONFIG_SDRAM_50MHZ

#undef	NR_8259_INTS
#define NR_8259_INTS		1

/*-----------------------------------------------------------------------
 * IDE/ATA stuff
 */
#define CFG_IDE_MAXBUS	    1	/* max. 2 IDE busses	*/
#define CFG_IDE_MAXDEVICE   (CFG_IDE_MAXBUS*1)	/* max. 2 drives per IDE bus */

#define CFG_ATA_BASE_ADDR   CFG_ISA_IO	/* base address */
#define CFG_ATA_IDE0_OFFSET 0x01F0	/* ide0 offste */
#define CFG_ATA_IDE1_OFFSET 0x0170	/* ide1 offset */
#define CFG_ATA_DATA_OFFSET 0	/* data reg offset  */
#define CFG_ATA_REG_OFFSET  0	/* reg offset */
#define CFG_ATA_ALT_OFFSET  0x200	/* alternate register offset */

#define CONFIG_ATAPI

#undef	CONFIG_IDE_8xx_DIRECT	/* no pcmcia interface required */
#undef	CONFIG_IDE_LED		/* no led for ide supported	*/
#undef	CONFIG_IDE_RESET	/* reset for ide supported...	 */
#undef	CONFIG_IDE_RESET_ROUTINE	/* with a special reset function */

/*-----------------------------------------------------------------------
 * DISK Partition support
 */
#define CONFIG_DOS_PARTITION

/*-----------------------------------------------------------------------
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

#endif /* __CONFIG_H */
Commit	Line	Data
80885a9d WD	1	/*
	2	* (C) Copyright 2001
	3	* Wolfgang Denk, DENX Software Engineering, [email protected].
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/* ------------------------------------------------------------------------- */
	25
	26	/*
	27	* board/config.h - configuration options, board specific
	28	*/
	29
	30	#ifndef __CONFIG_H
	31	#define __CONFIG_H
	32
	33	/*
	34	* High Level Configuration Options
	35	* (easy to change)
	36	*/
	37
	38	#define CONFIG_MPC824X 1
	39	/* #define CONFIG_MPC8240 1 */
	40	#define CONFIG_MPC8245 1
	41	#define CONFIG_EXALION 1
	42
	43	#if defined (CONFIG_MPC8240)
	44	/* #warning ---------- eXalion with MPC8240 --------------- */
	45	#elif defined (CONFIG_MPC8245)
	46	/* #warning ++++++++++ eXalion with MPC8245 +++++++++++++++ */
	47	#elif defined (CONFIG_MPC8245) && defined (CONFIG_MPC8245)
	48	#error #### Both types of MPC824x defined (CONFIG_8240 and CONFIG_8245)
	49	#else
	50	#error #### Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
	51	#endif
	52	/* older kernels need clock in MHz newer in Hz */
	53	/* #define CONFIG_CLOCKS_IN_MHZ 1 // clocks passsed to Linux in MHz */
	54	#undef CONFIG_CLOCKS_IN_MHZ
	55
	56	#define CONFIG_BOOTDELAY 10
	57
	58
	59	/#define CONFIG_DRAM_SPEED 66 //* MHz */
	60
	61	#define CONFIG_COMMANDS ( CONFIG_CMD_DFL \| \
	62	CFG_CMD_FLASH \| \
	63	CFG_CMD_SDRAM \| \
	64	CFG_CMD_I2C \| \
65	CFG_CMD_IDE \| \
66	CFG_CMD_FAT \| \
67	CFG_CMD_ENV \| \
68	CFG_CMD_PCI )
69
70	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
71	#include <cmd_confdefs.h>
72
73
74	/*-----------------------------------------------------------------------
75	* Miscellaneous configurable options
76	*/
77	#define CFG_LONGHELP 1 /* undef to save memory */
78	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
79	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
80	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
81	#define CFG_MAXARGS 8 /* max number of command args */
82	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
83	#define CFG_LOAD_ADDR 0x00100000 /* default load address */
84
85	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
86
87	#define CONFIG_MISC_INIT_R 1
88
89	/*-----------------------------------------------------------------------
90	* Start addresses for the final memory configuration
91	* (Set up by the startup code)
92	* Please note that CFG_SDRAM_BASE _must_ start at 0
93	*/
94	#define CFG_SDRAM_BASE 0x00000000
95	#define CFG_MAX_RAM_SIZE 0x10000000 /* 1 GBytes - initdram() will */
96	/* return real value. */
97
98	#define CFG_RESET_ADDRESS 0xFFF00100
99
100	#undef CFG_RAMBOOT
101	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
102	#define CFG_MONITOR_BASE TEXT_BASE
103
104	/*-----------------------------------------------------------------------
105	* Definitions for initial stack pointer and data area
106	*/
107	#define CFG_INIT_DATA_SIZE 128
108
109	#define CFG_INIT_RAM_ADDR 0x40000000
110	#define CFG_INIT_RAM_END 0x1000
111	#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
112
113	#define CFG_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */
114	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
115	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
116
117
118	#if defined (CONFIG_MPC8240)
119	#define CFG_FLASH_BASE 0xFFE00000
120	#define CFG_FLASH_SIZE (2 * 1024 * 1024) /* onboard 2MByte flash */
121	#elif defined (CONFIG_MPC8245)
122	#define CFG_FLASH_BASE 0xFFC00000
123	#define CFG_FLASH_SIZE (4 * 1024 * 1024) /* onboard 4MByte flash */
124	#else
125	#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
126	#endif
127
128	#define CFG_ENV_IS_IN_FLASH 1
129	#define CFG_ENV_SECT_SIZE 0x20000 /* Size of one Flash sector */
130	#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE /* Use one Flash sector for enviroment */
131	#define CFG_ENV_ADDR 0xFFFC0000
132	#define CFG_ENV_OFFSET 0 /* starting right at the beginning */
133
134	#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
135
136	#define CFG_ALT_MEMTEST 1 /* use real memory test */
137	#define CFG_MEMTEST_START 0x00004000 /* memtest works on */
138	#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
139
140	#define CFG_EUMB_ADDR 0xFC000000
141
142	/* #define CFG_ISA_MEM 0xFD000000 */
143	#define CFG_ISA_IO 0xFE000000
144
145	/*-----------------------------------------------------------------------
146	* FLASH organization
147	*/
148	#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */
149	#define CFG_MAX_FLASH_SECT 64 /* Max number of sectors per flash */
150
151	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
152	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
153
154	#define FLASH_BASE0_PRELIM CFG_FLASH_BASE
155	#define FLASH_BASE1_PRELIM 0
156
157
158	/*-----------------------------------------------------------------------
159	* FLASH and environment organization
160	*/
161
162	#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
163	#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
164	#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
165	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
166	#define CFG_FLASH_INCREMENT 0 /* there is only one bank */
167	#define CFG_FLASH_PROTECTION 1 /* use hardware protection */
168	#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
169
170
171	/*-----------------------------------------------------------------------
172	* PCI stuff
173	*/
174	#define CONFIG_PCI 1 /* include pci support */
175	#undef CONFIG_PCI_PNP
176
177	#define CONFIG_NET_MULTI 1 /* Multi ethernet cards support */
178
179	#define CONFIG_EEPRO100 1
180
181	#define PCI_ENET0_MEMADDR 0x80000000 /* Intel 82559ER */
182	#define PCI_ENET0_IOADDR 0x80000000
183	#define PCI_ENET1_MEMADDR 0x81000000 /* Intel 82559ER */
184	#define PCI_ENET1_IOADDR 0x81000000
185	#define PCI_ENET2_MEMADDR 0x82000000 /* Broadcom BCM569xx */
186	#define PCI_ENET2_IOADDR 0x82000000
187	#define PCI_ENET3_MEMADDR 0x83000000 /* Broadcom BCM56xx */
188	#define PCI_ENET3_IOADDR 0x83000000
189
190	/*-----------------------------------------------------------------------
191	* NS16550 Configuration
192	*/
193	#define CFG_NS16550 1
194	#define CFG_NS16550_SERIAL 1
195
196	#define CONFIG_CONS_INDEX 1
197	#define CONFIG_BAUDRATE 38400
198
199	#define CFG_NS16550_REG_SIZE 1
200
201	#if (CONFIG_CONS_INDEX == 1)
202	#define CFG_NS16550_CLK 1843200 /* COM1 only ! */
203	#else
204	#define CFG_NS16550_CLK ({ extern ulong get_bus_freq (ulong); get_bus_freq (0); })
205	#endif
206
207	#define CFG_NS16550_COM1 (CFG_ISA_IO + 0x3F8)
208	#define CFG_NS16550_COM2 (CFG_EUMB_ADDR + 0x4500)
209	#define CFG_NS16550_COM3 (CFG_EUMB_ADDR + 0x4600)
210
211	/*-----------------------------------------------------------------------
212	* select i2c support configuration
213	*
214	* Supported configurations are {none, software, hardware} drivers.
215	* If the software driver is chosen, there are some additional
216	* configuration items that the driver uses to drive the port pins.
217	*/
218	#define CONFIG_HARD_I2C 1 /* To enable I2C support */
219	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
220	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
221	#define CFG_I2C_SLAVE 0x7F
222
223	/*-----------------------------------------------------------------------
224	* Low Level Configuration Settings
225	* (address mappings, register initial values, etc.)
226	* You should know what you are doing if you make changes here.
227	*/
228	#define CFG_HZ 1000
229
230	#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
231	#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 2 /* for MPC8240 only */
232
233	/#define CONFIG_133MHZ_DRAM 1 //* For 133 MHZ DRAM only !!!!!!!!!!! */
234
235	#if defined (CONFIG_MPC8245)
236	/* Bit-field values for PMCR2. */
237	#if defined (CONFIG_133MHZ_DRAM)
238	#define CFG_DLL_EXTEND 0x80 /* use DLL extended range - 133MHz only */
239	#define CFG_PCI_HOLD_DEL 0x20 /* delay and hold timing - 133MHz only */
240	#endif
241
242	/* Bit-field values for MIOCR1. */
243	#if !defined (CONFIG_133MHZ_DRAM)
244	#define CFG_DLL_MAX_DELAY 0x04 /* longer DLL delay line - 66MHz only */
245	#endif
246	/* Bit-field values for MIOCR2. */
247	#define CFG_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay */
248	/* - note bottom 3 bits MUST be 0 */
249	#endif
250
251	/* Bit-field values for MCCR1. */
252	#define CFG_ROMNAL 7 /rom/flash next access time /
253	#define CFG_ROMFAL 11 /rom/flash access time /
254
255	/* Bit-field values for MCCR2. */
256	#define CFG_TSWAIT 0x5 /* Transaction Start Wait States timer */
257	#if defined (CONFIG_133MHZ_DRAM)
258	#define CFG_REFINT 1300 /* no of clock cycles between CBR */
259	#else /* refresh cycles */
260	#define CFG_REFINT 750
261	#endif
262
263	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */
264	#if defined (CONFIG_133MHZ_DRAM)
265	#define CFG_BSTOPRE 1023
266	#else
267	#define CFG_BSTOPRE 250
268	#endif
269
270	/* Bit-field values for MCCR3. */
271	/* the following are for SDRAM only */
272
273	#if defined (CONFIG_133MHZ_DRAM)
274	#define CFG_REFREC 9 /* Refresh to activate interval */
275	#else
276	#define CFG_REFREC 5 /* Refresh to activate interval */
277	#endif
278	#if defined (CONFIG_MPC8240)
279	#define CFG_RDLAT 2 /* data latency from read command */
280	#endif
281
282	/* Bit-field values for MCCR4. */
283	#if defined (CONFIG_133MHZ_DRAM)
284	#define CFG_PRETOACT 3 /* Precharge to activate interval */
285	#define CFG_ACTTOPRE 7 /* Activate to Precharge interval */
286	#define CFG_ACTORW 5 /* Activate to R/W */
287	#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
288	#else
289	#if 0
290	#define CFG_PRETOACT 2 /* Precharge to activate interval */
291	#define CFG_ACTTOPRE 3 /* Activate to Precharge interval */
292	#define CFG_ACTORW 3 /* Activate to R/W */
293	#define CFG_SDMODE_CAS_LAT 2 /* SDMODE CAS latency */
294	#endif
295	#define CFG_PRETOACT 2 /* Precharge to activate interval */
296	#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */
297	#define CFG_ACTORW 3 /* Activate to R/W */
298	#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
299	#endif
300	#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */
301	#define CFG_SDMODE_BURSTLEN 2 /* SDMODE Burst length 2=4, 3=8 */
302	#define CFG_REGDIMM 0
303	#if defined (CONFIG_MPC8240)
304	#define CFG_REGISTERD_TYPE_BUFFER 0
305	#elif defined (CONFIG_MPC8245)
306	#define CFG_REGISTERD_TYPE_BUFFER 1
307	#define CFG_EXTROM 0
308	#else
309	#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
310	#endif
311
312
313	/*-----------------------------------------------------------------------
314	memory bank settings
315	* only bits 20-29 are actually used from these vales to set the
316	* start/end address the upper two bits will be 0, and the lower 20
317	* bits will be set to 0x00000 for a start address, or 0xfffff for an
318	* end address
319	*/
320	#define CFG_BANK0_START 0x00000000
321	#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1)
322	#define CFG_BANK0_ENABLE 1
323	#define CFG_BANK1_START 0x3ff00000
324	#define CFG_BANK1_END 0x3fffffff
325	#define CFG_BANK1_ENABLE 0
326	#define CFG_BANK2_START 0x3ff00000
327	#define CFG_BANK2_END 0x3fffffff
328	#define CFG_BANK2_ENABLE 0
329	#define CFG_BANK3_START 0x3ff00000
330	#define CFG_BANK3_END 0x3fffffff
331	#define CFG_BANK3_ENABLE 0
332	#define CFG_BANK4_START 0x00000000
333	#define CFG_BANK4_END 0x00000000
334	#define CFG_BANK4_ENABLE 0
335	#define CFG_BANK5_START 0x00000000
336	#define CFG_BANK5_END 0x00000000
337	#define CFG_BANK5_ENABLE 0
338	#define CFG_BANK6_START 0x00000000
339	#define CFG_BANK6_END 0x00000000
340	#define CFG_BANK6_ENABLE 0
341	#define CFG_BANK7_START 0x00000000
342	#define CFG_BANK7_END 0x00000000
343	#define CFG_BANK7_ENABLE 0
344
345	/*-----------------------------------------------------------------------
346	* Memory bank enable bitmask, specifying which of the banks defined above
347	are actually present. MSB is for bank #7, LSB is for bank #0.
348	*/
349	#define CFG_BANK_ENABLE 0x01
350
351	#if defined (CONFIG_MPC8240)
352	#define CFG_ODCR 0xDF /* configures line driver impedances, */
353	/* see 8240 book for bit definitions */
354	#elif defined (CONFIG_MPC8245)
355	#if defined (CONFIG_133MHZ_DRAM)
356	#define CFG_ODCR 0xFE /* configures line driver impedances - 133MHz */
357	#else
358	#define CFG_ODCR 0xDE /* configures line driver impedances - 66MHz */
359	#endif
360	#else
361	#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
362	#endif
363
364	#define CFG_PGMAX 0x32 /* how long the 8240 retains the */
365	/* currently accessed page in memory */
366	/* see 8240 book for details */
367
368	/*-----------------------------------------------------------------------
369	* Block Address Translation (BAT) register settings.
370	*/
371	/* SDRAM 0 - 256MB */
372	#define CFG_IBAT0L (CFG_SDRAM_BASE \| BATL_PP_10 \| BATL_MEMCOHERENCE)
373	#define CFG_IBAT0U (CFG_SDRAM_BASE \| BATU_BL_256M \| BATU_VS \| BATU_VP)
374
375	/* stack in DCACHE @ 1GB (no backing mem) */
376	#define CFG_IBAT1L (CFG_INIT_RAM_ADDR \| BATL_PP_10 \| BATL_MEMCOHERENCE)
377	#define CFG_IBAT1U (CFG_INIT_RAM_ADDR \| BATU_BL_128K \| BATU_VS \| BATU_VP)
378
379	/* PCI memory */
380	#define CFG_IBAT2L (0x80000000 \| BATL_PP_10 \| BATL_CACHEINHIBIT)
381	#define CFG_IBAT2U (0x80000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
382
383	/* Flash, config addrs, etc */
384	#define CFG_IBAT3L (0xF0000000 \| BATL_PP_10 \| BATL_CACHEINHIBIT)
385	#define CFG_IBAT3U (0xF0000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
386
387	#define CFG_DBAT0L CFG_IBAT0L
388	#define CFG_DBAT0U CFG_IBAT0U
389	#define CFG_DBAT1L CFG_IBAT1L
390	#define CFG_DBAT1U CFG_IBAT1U
391	#define CFG_DBAT2L CFG_IBAT2L
392	#define CFG_DBAT2U CFG_IBAT2U
393	#define CFG_DBAT3L CFG_IBAT3L
394	#define CFG_DBAT3U CFG_IBAT3U
395
396
397	/*-----------------------------------------------------------------------
398	* Cache Configuration
399	*/
400	#define CFG_CACHELINE_SIZE 32
401	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
402	# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
403	#endif
404
405
406	/*-----------------------------------------------------------------------
407	* Internal Definitions
408	*
409	* Boot Flags
410	*/
411	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
412	#define BOOTFLAG_WARM 0x02 /* Software reboot */
413
414
415	/* values according to the manual */
416	#define CONFIG_DRAM_50MHZ 1
417	#define CONFIG_SDRAM_50MHZ
418
419	#undef NR_8259_INTS
420	#define NR_8259_INTS 1
421
422	/*-----------------------------------------------------------------------
423	* IDE/ATA stuff
424	*/
425	#define CFG_IDE_MAXBUS 1 /* max. 2 IDE busses */
426	#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS1) / max. 2 drives per IDE bus */
427
428	#define CFG_ATA_BASE_ADDR CFG_ISA_IO /* base address */
429	#define CFG_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
430	#define CFG_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */
431	#define CFG_ATA_DATA_OFFSET 0 /* data reg offset */
432	#define CFG_ATA_REG_OFFSET 0 /* reg offset */
433	#define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */
434
435	#define CONFIG_ATAPI
436
437	#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
438	#undef CONFIG_IDE_LED /* no led for ide supported */
439	#undef CONFIG_IDE_RESET /* reset for ide supported... */
440	#undef CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
441
442	/*-----------------------------------------------------------------------
443	* DISK Partition support
444	*/
445	#define CONFIG_DOS_PARTITION
446
447	/*-----------------------------------------------------------------------
448	* For booting Linux, the board info and command line data
449	* have to be in the first 8 MB of memory, since this is
450	* the maximum mapped by the Linux kernel during initialization.
451	*/
452	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
453
454	#endif /* __CONFIG_H */