[u-boot.git] / arch / arm / mach-k3 / common.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * K3: Common Architecture initialization
 *
 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
 *	Lokesh Vutla <[email protected]>
 */

#include <common.h>
#include <cpu_func.h>
#include <spl.h>
#include "common.h"
#include <dm.h>
#include <remoteproc.h>
#include <linux/soc/ti/ti_sci_protocol.h>
#include <fdt_support.h>
#include <asm/arch/sys_proto.h>
#include <asm/hardware.h>
#include <asm/io.h>

struct ti_sci_handle *get_ti_sci_handle(void)
{
	struct udevice *dev;
	int ret;

	ret = uclass_get_device_by_driver(UCLASS_FIRMWARE,
					  DM_GET_DRIVER(ti_sci), &dev);
	if (ret)
		panic("Failed to get SYSFW (%d)\n", ret);

	return (struct ti_sci_handle *)ti_sci_get_handle_from_sysfw(dev);
}

DECLARE_GLOBAL_DATA_PTR;

#ifdef CONFIG_K3_EARLY_CONS
int early_console_init(void)
{
	struct udevice *dev;
	int ret;

	gd->baudrate = CONFIG_BAUDRATE;

	ret = uclass_get_device_by_seq(UCLASS_SERIAL, CONFIG_K3_EARLY_CONS_IDX,
				       &dev);
	if (ret) {
		printf("Error getting serial dev for early console! (%d)\n",
		       ret);
		return ret;
	}

	gd->cur_serial_dev = dev;
	gd->flags |= GD_FLG_SERIAL_READY;
	gd->have_console = 1;

	return 0;
}
#endif

#ifdef CONFIG_SYS_K3_SPL_ATF
void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
{
	struct ti_sci_handle *ti_sci = get_ti_sci_handle();
	int ret;

	/* Release all the exclusive devices held by SPL before starting ATF */
	ti_sci->ops.dev_ops.release_exclusive_devices(ti_sci);

	/*
	 * It is assumed that remoteproc device 1 is the corresponding
	 * Cortex-A core which runs ATF. Make sure DT reflects the same.
	 */
	ret = rproc_dev_init(1);
	if (ret)
		panic("%s: ATF failed to initialize on rproc (%d)\n", __func__,
		      ret);

	ret = rproc_load(1, spl_image->entry_point, 0x200);
	if (ret)
		panic("%s: ATF failed to load on rproc (%d)\n", __func__, ret);

	/* Add an extra newline to differentiate the ATF logs from SPL */
	printf("Starting ATF on ARM64 core...\n\n");

	ret = rproc_start(1);
	if (ret)
		panic("%s: ATF failed to start on rproc (%d)\n", __func__, ret);

	debug("Releasing resources...\n");
	release_resources_for_core_shutdown();

	debug("Finalizing core shutdown...\n");
	while (1)
		asm volatile("wfe");
}
#endif

#if defined(CONFIG_OF_LIBFDT)
int fdt_fixup_msmc_ram(void *blob, char *parent_path, char *node_name)
{
	u64 msmc_start = 0, msmc_end = 0, msmc_size, reg[2];
	struct ti_sci_handle *ti_sci = get_ti_sci_handle();
	int ret, node, subnode, len, prev_node;
	u32 range[4], addr, size;
	const fdt32_t *sub_reg;

	ti_sci->ops.core_ops.query_msmc(ti_sci, &msmc_start, &msmc_end);
	msmc_size = msmc_end - msmc_start + 1;
	debug("%s: msmc_start = 0x%llx, msmc_size = 0x%llx\n", __func__,
	      msmc_start, msmc_size);

	/* find or create "msmc_sram node */
	ret = fdt_path_offset(blob, parent_path);
	if (ret < 0)
		return ret;

	node = fdt_find_or_add_subnode(blob, ret, node_name);
	if (node < 0)
		return node;

	ret = fdt_setprop_string(blob, node, "compatible", "mmio-sram");
	if (ret < 0)
		return ret;

	reg[0] = cpu_to_fdt64(msmc_start);
	reg[1] = cpu_to_fdt64(msmc_size);
	ret = fdt_setprop(blob, node, "reg", reg, sizeof(reg));
	if (ret < 0)
		return ret;

	fdt_setprop_cell(blob, node, "#address-cells", 1);
	fdt_setprop_cell(blob, node, "#size-cells", 1);

	range[0] = 0;
	range[1] = cpu_to_fdt32(msmc_start >> 32);
	range[2] = cpu_to_fdt32(msmc_start & 0xffffffff);
	range[3] = cpu_to_fdt32(msmc_size);
	ret = fdt_setprop(blob, node, "ranges", range, sizeof(range));
	if (ret < 0)
		return ret;

	subnode = fdt_first_subnode(blob, node);
	prev_node = 0;

	/* Look for invalid subnodes and delete them */
	while (subnode >= 0) {
		sub_reg = fdt_getprop(blob, subnode, "reg", &len);
		addr = fdt_read_number(sub_reg, 1);
		sub_reg++;
		size = fdt_read_number(sub_reg, 1);
		debug("%s: subnode = %d, addr = 0x%x. size = 0x%x\n", __func__,
		      subnode, addr, size);
		if (addr + size > msmc_size ||
		    !strncmp(fdt_get_name(blob, subnode, &len), "sysfw", 5) ||
		    !strncmp(fdt_get_name(blob, subnode, &len), "l3cache", 7)) {
			fdt_del_node(blob, subnode);
			debug("%s: deleting subnode %d\n", __func__, subnode);
			if (!prev_node)
				subnode = fdt_first_subnode(blob, node);
			else
				subnode = fdt_next_subnode(blob, prev_node);
		} else {
			prev_node = subnode;
			subnode = fdt_next_subnode(blob, prev_node);
		}
	}

	return 0;
}

int fdt_disable_node(void *blob, char *node_path)
{
	int offs;
	int ret;

	offs = fdt_path_offset(blob, node_path);
	if (offs < 0) {
		printf("Node %s not found.\n", node_path);
		return offs;
	}
	ret = fdt_setprop_string(blob, offs, "status", "disabled");
	if (ret < 0) {
		printf("Could not add status property to node %s: %s\n",
		       node_path, fdt_strerror(ret));
		return ret;
	}
	return 0;
}

#endif

#ifndef CONFIG_SYSRESET
void reset_cpu(ulong ignored)
{
}
#endif

#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
	u32 soc, rev;
	char *name;

	soc = (readl(CTRLMMR_WKUP_JTAG_DEVICE_ID) &
		DEVICE_ID_FAMILY_MASK) >> DEVICE_ID_FAMILY_SHIFT;
	rev = (readl(CTRLMMR_WKUP_JTAG_ID) &
		JTAG_ID_VARIANT_MASK) >> JTAG_ID_VARIANT_SHIFT;

	printf("SoC:   ");
	switch (soc) {
	case AM654:
		name = "AM654";
		break;
	case J721E:
		name = "J721E";
		break;
	default:
		name = "Unknown Silicon";
	};

	printf("%s SR ", name);
	switch (rev) {
	case REV_PG1_0:
		name = "1.0";
		break;
	case REV_PG2_0:
		name = "2.0";
		break;
	default:
		name = "Unknown Revision";
	};
	printf("%s\n", name);

	return 0;
}
#endif

#ifdef CONFIG_ARM64
void board_prep_linux(bootm_headers_t *images)
{
	debug("Linux kernel Image start = 0x%lx end = 0x%lx\n",
	      images->os.start, images->os.end);
	__asm_flush_dcache_range(images->os.start,
				 ROUND(images->os.end,
				       CONFIG_SYS_CACHELINE_SIZE));
}
#endif

#ifdef CONFIG_CPU_V7R
void disable_linefill_optimization(void)
{
	u32 actlr;

	/*
	 * On K3 devices there are 2 conditions where R5F can deadlock:
	 * 1.When software is performing series of store operations to
	 *   cacheable write back/write allocate memory region and later
	 *   on software execute barrier operation (DSB or DMB). R5F may
	 *   hang at the barrier instruction.
	 * 2.When software is performing a mix of load and store operations
	 *   within a tight loop and store operations are all writing to
	 *   cacheable write back/write allocates memory regions, R5F may
	 *   hang at one of the load instruction.
	 *
	 * To avoid the above two conditions disable linefill optimization
	 * inside Cortex R5F.
	 */
	asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (actlr));
	actlr |= (1 << 13); /* Set DLFO bit  */
	asm("mcr p15, 0, %0, c1, c0, 1" : : "r" (actlr));
}
#endif

void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size)
{
	struct ti_sci_msg_fwl_region region;
	struct ti_sci_fwl_ops *fwl_ops;
	struct ti_sci_handle *ti_sci;
	size_t i, j;

	ti_sci = get_ti_sci_handle();
	fwl_ops = &ti_sci->ops.fwl_ops;
	for (i = 0; i < fwl_data_size; i++) {
		for (j = 0; j <  fwl_data[i].regions; j++) {
			region.fwl_id = fwl_data[i].fwl_id;
			region.region = j;
			region.n_permission_regs = 3;

			fwl_ops->get_fwl_region(ti_sci, &region);

			if (region.control != 0) {
				pr_debug("Attempting to disable firewall %5d (%25s)\n",
					 region.fwl_id, fwl_data[i].name);
				region.control = 0;

				if (fwl_ops->set_fwl_region(ti_sci, &region))
					pr_err("Could not disable firewall %5d (%25s)\n",
					       region.fwl_id, fwl_data[i].name);
			}
		}
	}
}
Commit	Line	Data
a3501a4a LV	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* K3: Common Architecture initialization
	4	*
	5	* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
	6	* Lokesh Vutla <[email protected]>
	7	*/
	8
	9	#include <common.h>
9a3b4ceb	10	#include <cpu_func.h>
a3501a4a LV	11	#include <spl.h>
	12	#include "common.h"
	13	#include <dm.h>
	14	#include <remoteproc.h>
6ce424a9	15	#include <linux/soc/ti/ti_sci_protocol.h>
a9a84480	16	#include <fdt_support.h>
f9380a73	17	#include <asm/arch/sys_proto.h>
f8ca9121 LV	18	#include <asm/hardware.h>
f8ca9121 LV	19	#include <asm/io.h>
6ce424a9 LV	20
	21	struct ti_sci_handle *get_ti_sci_handle(void)
	22	{
	23	struct udevice *dev;
	24	int ret;
	25
e69ffdb7 LV	26	ret = uclass_get_device_by_driver(UCLASS_FIRMWARE,
e69ffdb7 LV	27	DM_GET_DRIVER(ti_sci), &dev);
6ce424a9 LV	28	if (ret)
	29	panic("Failed to get SYSFW (%d)\n", ret);
	30
	31	return (struct ti_sci_handle *)ti_sci_get_handle_from_sysfw(dev);
	32	}
a3501a4a	33
e630afe1 AD	34	DECLARE_GLOBAL_DATA_PTR;
	35
	36	#ifdef CONFIG_K3_EARLY_CONS
	37	int early_console_init(void)
	38	{
	39	struct udevice *dev;
	40	int ret;
	41
	42	gd->baudrate = CONFIG_BAUDRATE;
	43
	44	ret = uclass_get_device_by_seq(UCLASS_SERIAL, CONFIG_K3_EARLY_CONS_IDX,
	45	&dev);
	46	if (ret) {
	47	printf("Error getting serial dev for early console! (%d)\n",
	48	ret);
	49	return ret;
	50	}
	51
	52	gd->cur_serial_dev = dev;
	53	gd->flags \|= GD_FLG_SERIAL_READY;
	54	gd->have_console = 1;
	55
	56	return 0;
	57	}
	58	#endif
	59
a3501a4a LV	60	#ifdef CONFIG_SYS_K3_SPL_ATF
	61	void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
	62	{
c0669d28	63	struct ti_sci_handle *ti_sci = get_ti_sci_handle();
a3501a4a LV	64	int ret;
a3501a4a LV	65
c0669d28 LV	66	/* Release all the exclusive devices held by SPL before starting ATF */
	67	ti_sci->ops.dev_ops.release_exclusive_devices(ti_sci);
	68
a3501a4a LV	69	/*
a3501a4a LV	70	* It is assumed that remoteproc device 1 is the corresponding
4a1fa524	71	* Cortex-A core which runs ATF. Make sure DT reflects the same.
a3501a4a LV	72	*/
a3501a4a LV	73	ret = rproc_dev_init(1);
4a1fa524 AD	74	if (ret)
	75	panic("%s: ATF failed to initialize on rproc (%d)\n", __func__,
	76	ret);
a3501a4a LV	77
a3501a4a LV	78	ret = rproc_load(1, spl_image->entry_point, 0x200);
4a1fa524 AD	79	if (ret)
4a1fa524 AD	80	panic("%s: ATF failed to load on rproc (%d)\n", __func__, ret);
a3501a4a	81
4a1fa524	82	/* Add an extra newline to differentiate the ATF logs from SPL */
a3501a4a LV	83	printf("Starting ATF on ARM64 core...\n\n");
	84
	85	ret = rproc_start(1);
4a1fa524 AD	86	if (ret)
4a1fa524 AD	87	panic("%s: ATF failed to start on rproc (%d)\n", __func__, ret);
a3501a4a	88
f9380a73 AD	89	debug("Releasing resources...\n");
	90	release_resources_for_core_shutdown();
	91
	92	debug("Finalizing core shutdown...\n");
a3501a4a LV	93	while (1)
	94	asm volatile("wfe");
	95	}
	96	#endif
a9a84480 LV	97
	98	#if defined(CONFIG_OF_LIBFDT)
	99	int fdt_fixup_msmc_ram(void blob, char parent_path, char *node_name)
	100	{
	101	u64 msmc_start = 0, msmc_end = 0, msmc_size, reg[2];
	102	struct ti_sci_handle *ti_sci = get_ti_sci_handle();
	103	int ret, node, subnode, len, prev_node;
	104	u32 range[4], addr, size;
	105	const fdt32_t *sub_reg;
	106
	107	ti_sci->ops.core_ops.query_msmc(ti_sci, &msmc_start, &msmc_end);
	108	msmc_size = msmc_end - msmc_start + 1;
	109	debug("%s: msmc_start = 0x%llx, msmc_size = 0x%llx\n", __func__,
	110	msmc_start, msmc_size);
	111
	112	/* find or create "msmc_sram node */
	113	ret = fdt_path_offset(blob, parent_path);
	114	if (ret < 0)
	115	return ret;
	116
	117	node = fdt_find_or_add_subnode(blob, ret, node_name);
	118	if (node < 0)
	119	return node;
	120
	121	ret = fdt_setprop_string(blob, node, "compatible", "mmio-sram");
	122	if (ret < 0)
	123	return ret;
	124
	125	reg[0] = cpu_to_fdt64(msmc_start);
	126	reg[1] = cpu_to_fdt64(msmc_size);
	127	ret = fdt_setprop(blob, node, "reg", reg, sizeof(reg));
	128	if (ret < 0)
	129	return ret;
	130
	131	fdt_setprop_cell(blob, node, "#address-cells", 1);
	132	fdt_setprop_cell(blob, node, "#size-cells", 1);
	133
	134	range[0] = 0;
	135	range[1] = cpu_to_fdt32(msmc_start >> 32);
	136	range[2] = cpu_to_fdt32(msmc_start & 0xffffffff);
	137	range[3] = cpu_to_fdt32(msmc_size);
	138	ret = fdt_setprop(blob, node, "ranges", range, sizeof(range));
	139	if (ret < 0)
	140	return ret;
	141
	142	subnode = fdt_first_subnode(blob, node);
	143	prev_node = 0;
	144
	145	/* Look for invalid subnodes and delete them */
	146	while (subnode >= 0) {
	147	sub_reg = fdt_getprop(blob, subnode, "reg", &len);
	148	addr = fdt_read_number(sub_reg, 1);
	149	sub_reg++;
	150	size = fdt_read_number(sub_reg, 1);
	151	debug("%s: subnode = %d, addr = 0x%x. size = 0x%x\n", __func__,
	152	subnode, addr, size);
	153	if (addr + size > msmc_size \|\|
	154	!strncmp(fdt_get_name(blob, subnode, &len), "sysfw", 5) \|\|
	155	!strncmp(fdt_get_name(blob, subnode, &len), "l3cache", 7)) {
	156	fdt_del_node(blob, subnode);
	157	debug("%s: deleting subnode %d\n", __func__, subnode);
	158	if (!prev_node)
	159	subnode = fdt_first_subnode(blob, node);
	160	else
161	subnode = fdt_next_subnode(blob, prev_node);
162	} else {
163	prev_node = subnode;
164	subnode = fdt_next_subnode(blob, prev_node);
165	}
166	}
167
168	return 0;
169	}
29c9db4d AD	170
	171	int fdt_disable_node(void blob, char node_path)
	172	{
	173	int offs;
	174	int ret;
	175
	176	offs = fdt_path_offset(blob, node_path);
	177	if (offs < 0) {
28b90a46 AD	178	printf("Node %s not found.\n", node_path);
28b90a46 AD	179	return offs;
29c9db4d AD	180	}
	181	ret = fdt_setprop_string(blob, offs, "status", "disabled");
	182	if (ret < 0) {
	183	printf("Could not add status property to node %s: %s\n",
	184	node_path, fdt_strerror(ret));
	185	return ret;
	186	}
	187	return 0;
	188	}
	189
a9a84480	190	#endif
c2562d7c LV	191
	192	#ifndef CONFIG_SYSRESET
	193	void reset_cpu(ulong ignored)
	194	{
	195	}
	196	#endif
f8ca9121 LV	197
	198	#if defined(CONFIG_DISPLAY_CPUINFO)
	199	int print_cpuinfo(void)
	200	{
	201	u32 soc, rev;
	202	char *name;
	203
	204	soc = (readl(CTRLMMR_WKUP_JTAG_DEVICE_ID) &
	205	DEVICE_ID_FAMILY_MASK) >> DEVICE_ID_FAMILY_SHIFT;
	206	rev = (readl(CTRLMMR_WKUP_JTAG_ID) &
	207	JTAG_ID_VARIANT_MASK) >> JTAG_ID_VARIANT_SHIFT;
	208
	209	printf("SoC: ");
	210	switch (soc) {
	211	case AM654:
	212	name = "AM654";
	213	break;
	214	case J721E:
	215	name = "J721E";
	216	break;
	217	default:
	218	name = "Unknown Silicon";
	219	};
	220
b9c268c9	221	printf("%s SR ", name);
f8ca9121 LV	222	switch (rev) {
	223	case REV_PG1_0:
	224	name = "1.0";
	225	break;
	226	case REV_PG2_0:
	227	name = "2.0";
	228	break;
	229	default:
	230	name = "Unknown Revision";
	231	};
	232	printf("%s\n", name);
	233
	234	return 0;
	235	}
	236	#endif
e938b225 LV	237
	238	#ifdef CONFIG_ARM64
	239	void board_prep_linux(bootm_headers_t *images)
	240	{
	241	debug("Linux kernel Image start = 0x%lx end = 0x%lx\n",
	242	images->os.start, images->os.end);
	243	__asm_flush_dcache_range(images->os.start,
	244	ROUND(images->os.end,
	245	CONFIG_SYS_CACHELINE_SIZE));
	246	}
	247	#endif
40109f4d LV	248
	249	#ifdef CONFIG_CPU_V7R
	250	void disable_linefill_optimization(void)
	251	{
	252	u32 actlr;
	253
	254	/*
	255	* On K3 devices there are 2 conditions where R5F can deadlock:
	256	* 1.When software is performing series of store operations to
	257	* cacheable write back/write allocate memory region and later
	258	* on software execute barrier operation (DSB or DMB). R5F may
	259	* hang at the barrier instruction.
	260	* 2.When software is performing a mix of load and store operations
	261	* within a tight loop and store operations are all writing to
	262	* cacheable write back/write allocates memory regions, R5F may
	263	* hang at one of the load instruction.
	264	*
	265	* To avoid the above two conditions disable linefill optimization
	266	* inside Cortex R5F.
	267	*/
	268	asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (actlr));
	269	actlr \|= (1 << 13); /* Set DLFO bit */
	270	asm("mcr p15, 0, %0, c1, c0, 1" : : "r" (actlr));
	271	}
	272	#endif
ea70da14 AD	273
	274	void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size)
	275	{
	276	struct ti_sci_msg_fwl_region region;
	277	struct ti_sci_fwl_ops *fwl_ops;
	278	struct ti_sci_handle *ti_sci;
	279	size_t i, j;
	280
	281	ti_sci = get_ti_sci_handle();
	282	fwl_ops = &ti_sci->ops.fwl_ops;
	283	for (i = 0; i < fwl_data_size; i++) {
	284	for (j = 0; j < fwl_data[i].regions; j++) {
	285	region.fwl_id = fwl_data[i].fwl_id;
	286	region.region = j;
	287	region.n_permission_regs = 3;
	288
	289	fwl_ops->get_fwl_region(ti_sci, &region);
	290
	291	if (region.control != 0) {
	292	pr_debug("Attempting to disable firewall %5d (%25s)\n",
	293	region.fwl_id, fwl_data[i].name);
	294	region.control = 0;
	295
	296	if (fwl_ops->set_fwl_region(ti_sci, &region))
	297	pr_err("Could not disable firewall %5d (%25s)\n",
	298	region.fwl_id, fwl_data[i].name);
	299	}
	300	}
	301	}
	302	}