[u-boot.git] / arch / arm / mach-k3 / common.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * K3: Common Architecture initialization
 *
 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
 *	Lokesh Vutla <[email protected]>
 */

#include <common.h>
#include <spl.h>
#include "common.h"
#include <dm.h>
#include <remoteproc.h>
#include <linux/soc/ti/ti_sci_protocol.h>
#include <fdt_support.h>
#include <asm/arch/sys_proto.h>
#include <asm/hardware.h>
#include <asm/io.h>

struct ti_sci_handle *get_ti_sci_handle(void)
{
	struct udevice *dev;
	int ret;

	ret = uclass_get_device_by_driver(UCLASS_FIRMWARE,
					  DM_GET_DRIVER(ti_sci), &dev);
	if (ret)
		panic("Failed to get SYSFW (%d)\n", ret);

	return (struct ti_sci_handle *)ti_sci_get_handle_from_sysfw(dev);
}

DECLARE_GLOBAL_DATA_PTR;

#ifdef CONFIG_K3_EARLY_CONS
int early_console_init(void)
{
	struct udevice *dev;
	int ret;

	gd->baudrate = CONFIG_BAUDRATE;

	ret = uclass_get_device_by_seq(UCLASS_SERIAL, CONFIG_K3_EARLY_CONS_IDX,
				       &dev);
	if (ret) {
		printf("Error getting serial dev for early console! (%d)\n",
		       ret);
		return ret;
	}

	gd->cur_serial_dev = dev;
	gd->flags |= GD_FLG_SERIAL_READY;
	gd->have_console = 1;

	return 0;
}
#endif

#ifdef CONFIG_SYS_K3_SPL_ATF
void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
{
	struct ti_sci_handle *ti_sci = get_ti_sci_handle();
	int ret;

	/* Release all the exclusive devices held by SPL before starting ATF */
	ti_sci->ops.dev_ops.release_exclusive_devices(ti_sci);

	/*
	 * It is assumed that remoteproc device 1 is the corresponding
	 * Cortex-A core which runs ATF. Make sure DT reflects the same.
	 */
	ret = rproc_dev_init(1);
	if (ret)
		panic("%s: ATF failed to initialize on rproc (%d)\n", __func__,
		      ret);

	ret = rproc_load(1, spl_image->entry_point, 0x200);
	if (ret)
		panic("%s: ATF failed to load on rproc (%d)\n", __func__, ret);

	/* Add an extra newline to differentiate the ATF logs from SPL */
	printf("Starting ATF on ARM64 core...\n\n");

	ret = rproc_start(1);
	if (ret)
		panic("%s: ATF failed to start on rproc (%d)\n", __func__, ret);

	debug("Releasing resources...\n");
	release_resources_for_core_shutdown();

	debug("Finalizing core shutdown...\n");
	while (1)
		asm volatile("wfe");
}
#endif

#if defined(CONFIG_OF_LIBFDT)
int fdt_fixup_msmc_ram(void *blob, char *parent_path, char *node_name)
{
	u64 msmc_start = 0, msmc_end = 0, msmc_size, reg[2];
	struct ti_sci_handle *ti_sci = get_ti_sci_handle();
	int ret, node, subnode, len, prev_node;
	u32 range[4], addr, size;
	const fdt32_t *sub_reg;

	ti_sci->ops.core_ops.query_msmc(ti_sci, &msmc_start, &msmc_end);
	msmc_size = msmc_end - msmc_start + 1;
	debug("%s: msmc_start = 0x%llx, msmc_size = 0x%llx\n", __func__,
	      msmc_start, msmc_size);

	/* find or create "msmc_sram node */
	ret = fdt_path_offset(blob, parent_path);
	if (ret < 0)
		return ret;

	node = fdt_find_or_add_subnode(blob, ret, node_name);
	if (node < 0)
		return node;

	ret = fdt_setprop_string(blob, node, "compatible", "mmio-sram");
	if (ret < 0)
		return ret;

	reg[0] = cpu_to_fdt64(msmc_start);
	reg[1] = cpu_to_fdt64(msmc_size);
	ret = fdt_setprop(blob, node, "reg", reg, sizeof(reg));
	if (ret < 0)
		return ret;

	fdt_setprop_cell(blob, node, "#address-cells", 1);
	fdt_setprop_cell(blob, node, "#size-cells", 1);

	range[0] = 0;
	range[1] = cpu_to_fdt32(msmc_start >> 32);
	range[2] = cpu_to_fdt32(msmc_start & 0xffffffff);
	range[3] = cpu_to_fdt32(msmc_size);
	ret = fdt_setprop(blob, node, "ranges", range, sizeof(range));
	if (ret < 0)
		return ret;

	subnode = fdt_first_subnode(blob, node);
	prev_node = 0;

	/* Look for invalid subnodes and delete them */
	while (subnode >= 0) {
		sub_reg = fdt_getprop(blob, subnode, "reg", &len);
		addr = fdt_read_number(sub_reg, 1);
		sub_reg++;
		size = fdt_read_number(sub_reg, 1);
		debug("%s: subnode = %d, addr = 0x%x. size = 0x%x\n", __func__,
		      subnode, addr, size);
		if (addr + size > msmc_size ||
		    !strncmp(fdt_get_name(blob, subnode, &len), "sysfw", 5) ||
		    !strncmp(fdt_get_name(blob, subnode, &len), "l3cache", 7)) {
			fdt_del_node(blob, subnode);
			debug("%s: deleting subnode %d\n", __func__, subnode);
			if (!prev_node)
				subnode = fdt_first_subnode(blob, node);
			else
				subnode = fdt_next_subnode(blob, prev_node);
		} else {
			prev_node = subnode;
			subnode = fdt_next_subnode(blob, prev_node);
		}
	}

	return 0;
}

int fdt_disable_node(void *blob, char *node_path)
{
	int offs;
	int ret;

	offs = fdt_path_offset(blob, node_path);
	if (offs < 0) {
		debug("Node %s not found.\n", node_path);
		return 0;
	}
	ret = fdt_setprop_string(blob, offs, "status", "disabled");
	if (ret < 0) {
		printf("Could not add status property to node %s: %s\n",
		       node_path, fdt_strerror(ret));
		return ret;
	}
	return 0;
}

#endif

#ifndef CONFIG_SYSRESET
void reset_cpu(ulong ignored)
{
}
#endif

#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
	u32 soc, rev;
	char *name;

	soc = (readl(CTRLMMR_WKUP_JTAG_DEVICE_ID) &
		DEVICE_ID_FAMILY_MASK) >> DEVICE_ID_FAMILY_SHIFT;
	rev = (readl(CTRLMMR_WKUP_JTAG_ID) &
		JTAG_ID_VARIANT_MASK) >> JTAG_ID_VARIANT_SHIFT;

	printf("SoC:   ");
	switch (soc) {
	case AM654:
		name = "AM654";
		break;
	case J721E:
		name = "J721E";
		break;
	default:
		name = "Unknown Silicon";
	};

	printf("%s PG ", name);
	switch (rev) {
	case REV_PG1_0:
		name = "1.0";
		break;
	case REV_PG2_0:
		name = "2.0";
		break;
	default:
		name = "Unknown Revision";
	};
	printf("%s\n", name);

	return 0;
}
#endif

#ifdef CONFIG_ARM64
void board_prep_linux(bootm_headers_t *images)
{
	debug("Linux kernel Image start = 0x%lx end = 0x%lx\n",
	      images->os.start, images->os.end);
	__asm_flush_dcache_range(images->os.start,
				 ROUND(images->os.end,
				       CONFIG_SYS_CACHELINE_SIZE));
}
#endif

#ifdef CONFIG_CPU_V7R
void disable_linefill_optimization(void)
{
	u32 actlr;

	/*
	 * On K3 devices there are 2 conditions where R5F can deadlock:
	 * 1.When software is performing series of store operations to
	 *   cacheable write back/write allocate memory region and later
	 *   on software execute barrier operation (DSB or DMB). R5F may
	 *   hang at the barrier instruction.
	 * 2.When software is performing a mix of load and store operations
	 *   within a tight loop and store operations are all writing to
	 *   cacheable write back/write allocates memory regions, R5F may
	 *   hang at one of the load instruction.
	 *
	 * To avoid the above two conditions disable linefill optimization
	 * inside Cortex R5F.
	 */
	asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (actlr));
	actlr |= (1 << 13); /* Set DLFO bit  */
	asm("mcr p15, 0, %0, c1, c0, 1" : : "r" (actlr));
}
#endif
Commit	Line	Data
a3501a4a LV	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* K3: Common Architecture initialization
	4	*
	5	* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
	6	* Lokesh Vutla <[email protected]>
	7	*/
	8
	9	#include <common.h>
	10	#include <spl.h>
	11	#include "common.h"
	12	#include <dm.h>
	13	#include <remoteproc.h>
6ce424a9	14	#include <linux/soc/ti/ti_sci_protocol.h>
a9a84480	15	#include <fdt_support.h>
f9380a73	16	#include <asm/arch/sys_proto.h>
f8ca9121 LV	17	#include <asm/hardware.h>
f8ca9121 LV	18	#include <asm/io.h>
6ce424a9 LV	19
	20	struct ti_sci_handle *get_ti_sci_handle(void)
	21	{
	22	struct udevice *dev;
	23	int ret;
	24
e69ffdb7 LV	25	ret = uclass_get_device_by_driver(UCLASS_FIRMWARE,
e69ffdb7 LV	26	DM_GET_DRIVER(ti_sci), &dev);
6ce424a9 LV	27	if (ret)
	28	panic("Failed to get SYSFW (%d)\n", ret);
	29
	30	return (struct ti_sci_handle *)ti_sci_get_handle_from_sysfw(dev);
	31	}
a3501a4a	32
e630afe1 AD	33	DECLARE_GLOBAL_DATA_PTR;
	34
	35	#ifdef CONFIG_K3_EARLY_CONS
	36	int early_console_init(void)
	37	{
	38	struct udevice *dev;
	39	int ret;
	40
	41	gd->baudrate = CONFIG_BAUDRATE;
	42
	43	ret = uclass_get_device_by_seq(UCLASS_SERIAL, CONFIG_K3_EARLY_CONS_IDX,
	44	&dev);
	45	if (ret) {
	46	printf("Error getting serial dev for early console! (%d)\n",
	47	ret);
	48	return ret;
	49	}
	50
	51	gd->cur_serial_dev = dev;
	52	gd->flags \|= GD_FLG_SERIAL_READY;
	53	gd->have_console = 1;
	54
	55	return 0;
	56	}
	57	#endif
	58
a3501a4a LV	59	#ifdef CONFIG_SYS_K3_SPL_ATF
	60	void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
	61	{
c0669d28	62	struct ti_sci_handle *ti_sci = get_ti_sci_handle();
a3501a4a LV	63	int ret;
a3501a4a LV	64
c0669d28 LV	65	/* Release all the exclusive devices held by SPL before starting ATF */
	66	ti_sci->ops.dev_ops.release_exclusive_devices(ti_sci);
	67
a3501a4a LV	68	/*
a3501a4a LV	69	* It is assumed that remoteproc device 1 is the corresponding
4a1fa524	70	* Cortex-A core which runs ATF. Make sure DT reflects the same.
a3501a4a LV	71	*/
a3501a4a LV	72	ret = rproc_dev_init(1);
4a1fa524 AD	73	if (ret)
	74	panic("%s: ATF failed to initialize on rproc (%d)\n", __func__,
	75	ret);
a3501a4a LV	76
a3501a4a LV	77	ret = rproc_load(1, spl_image->entry_point, 0x200);
4a1fa524 AD	78	if (ret)
4a1fa524 AD	79	panic("%s: ATF failed to load on rproc (%d)\n", __func__, ret);
a3501a4a	80
4a1fa524	81	/* Add an extra newline to differentiate the ATF logs from SPL */
a3501a4a LV	82	printf("Starting ATF on ARM64 core...\n\n");
	83
	84	ret = rproc_start(1);
4a1fa524 AD	85	if (ret)
4a1fa524 AD	86	panic("%s: ATF failed to start on rproc (%d)\n", __func__, ret);
a3501a4a	87
f9380a73 AD	88	debug("Releasing resources...\n");
	89	release_resources_for_core_shutdown();
	90
	91	debug("Finalizing core shutdown...\n");
a3501a4a LV	92	while (1)
	93	asm volatile("wfe");
	94	}
	95	#endif
a9a84480 LV	96
	97	#if defined(CONFIG_OF_LIBFDT)
	98	int fdt_fixup_msmc_ram(void blob, char parent_path, char *node_name)
	99	{
	100	u64 msmc_start = 0, msmc_end = 0, msmc_size, reg[2];
	101	struct ti_sci_handle *ti_sci = get_ti_sci_handle();
	102	int ret, node, subnode, len, prev_node;
	103	u32 range[4], addr, size;
	104	const fdt32_t *sub_reg;
	105
	106	ti_sci->ops.core_ops.query_msmc(ti_sci, &msmc_start, &msmc_end);
	107	msmc_size = msmc_end - msmc_start + 1;
	108	debug("%s: msmc_start = 0x%llx, msmc_size = 0x%llx\n", __func__,
	109	msmc_start, msmc_size);
	110
	111	/* find or create "msmc_sram node */
	112	ret = fdt_path_offset(blob, parent_path);
	113	if (ret < 0)
	114	return ret;
	115
	116	node = fdt_find_or_add_subnode(blob, ret, node_name);
	117	if (node < 0)
	118	return node;
	119
	120	ret = fdt_setprop_string(blob, node, "compatible", "mmio-sram");
	121	if (ret < 0)
	122	return ret;
	123
	124	reg[0] = cpu_to_fdt64(msmc_start);
	125	reg[1] = cpu_to_fdt64(msmc_size);
	126	ret = fdt_setprop(blob, node, "reg", reg, sizeof(reg));
	127	if (ret < 0)
	128	return ret;
	129
	130	fdt_setprop_cell(blob, node, "#address-cells", 1);
	131	fdt_setprop_cell(blob, node, "#size-cells", 1);
	132
	133	range[0] = 0;
	134	range[1] = cpu_to_fdt32(msmc_start >> 32);
	135	range[2] = cpu_to_fdt32(msmc_start & 0xffffffff);
	136	range[3] = cpu_to_fdt32(msmc_size);
	137	ret = fdt_setprop(blob, node, "ranges", range, sizeof(range));
	138	if (ret < 0)
	139	return ret;
	140
	141	subnode = fdt_first_subnode(blob, node);
	142	prev_node = 0;
	143
	144	/* Look for invalid subnodes and delete them */
	145	while (subnode >= 0) {
	146	sub_reg = fdt_getprop(blob, subnode, "reg", &len);
	147	addr = fdt_read_number(sub_reg, 1);
	148	sub_reg++;
	149	size = fdt_read_number(sub_reg, 1);
	150	debug("%s: subnode = %d, addr = 0x%x. size = 0x%x\n", __func__,
	151	subnode, addr, size);
	152	if (addr + size > msmc_size \|\|
	153	!strncmp(fdt_get_name(blob, subnode, &len), "sysfw", 5) \|\|
	154	!strncmp(fdt_get_name(blob, subnode, &len), "l3cache", 7)) {
	155	fdt_del_node(blob, subnode);
	156	debug("%s: deleting subnode %d\n", __func__, subnode);
	157	if (!prev_node)
	158	subnode = fdt_first_subnode(blob, node);
	159	else
160	subnode = fdt_next_subnode(blob, prev_node);
161	} else {
162	prev_node = subnode;
163	subnode = fdt_next_subnode(blob, prev_node);
164	}
165	}
166
167	return 0;
168	}
29c9db4d AD	169
	170	int fdt_disable_node(void blob, char node_path)
	171	{
	172	int offs;
	173	int ret;
	174
	175	offs = fdt_path_offset(blob, node_path);
	176	if (offs < 0) {
	177	debug("Node %s not found.\n", node_path);
	178	return 0;
	179	}
	180	ret = fdt_setprop_string(blob, offs, "status", "disabled");
	181	if (ret < 0) {
	182	printf("Could not add status property to node %s: %s\n",
	183	node_path, fdt_strerror(ret));
	184	return ret;
	185	}
	186	return 0;
	187	}
	188
a9a84480	189	#endif
c2562d7c LV	190
	191	#ifndef CONFIG_SYSRESET
	192	void reset_cpu(ulong ignored)
	193	{
	194	}
	195	#endif
f8ca9121 LV	196
	197	#if defined(CONFIG_DISPLAY_CPUINFO)
	198	int print_cpuinfo(void)
	199	{
	200	u32 soc, rev;
	201	char *name;
	202
	203	soc = (readl(CTRLMMR_WKUP_JTAG_DEVICE_ID) &
	204	DEVICE_ID_FAMILY_MASK) >> DEVICE_ID_FAMILY_SHIFT;
	205	rev = (readl(CTRLMMR_WKUP_JTAG_ID) &
	206	JTAG_ID_VARIANT_MASK) >> JTAG_ID_VARIANT_SHIFT;
	207
	208	printf("SoC: ");
	209	switch (soc) {
	210	case AM654:
	211	name = "AM654";
	212	break;
	213	case J721E:
	214	name = "J721E";
	215	break;
	216	default:
	217	name = "Unknown Silicon";
	218	};
	219
	220	printf("%s PG ", name);
	221	switch (rev) {
	222	case REV_PG1_0:
	223	name = "1.0";
	224	break;
	225	case REV_PG2_0:
	226	name = "2.0";
	227	break;
	228	default:
	229	name = "Unknown Revision";
	230	};
	231	printf("%s\n", name);
	232
	233	return 0;
	234	}
	235	#endif
e938b225 LV	236
	237	#ifdef CONFIG_ARM64
	238	void board_prep_linux(bootm_headers_t *images)
	239	{
	240	debug("Linux kernel Image start = 0x%lx end = 0x%lx\n",
	241	images->os.start, images->os.end);
	242	__asm_flush_dcache_range(images->os.start,
	243	ROUND(images->os.end,
	244	CONFIG_SYS_CACHELINE_SIZE));
	245	}
	246	#endif
40109f4d LV	247
	248	#ifdef CONFIG_CPU_V7R
	249	void disable_linefill_optimization(void)
	250	{
	251	u32 actlr;
	252
	253	/*
	254	* On K3 devices there are 2 conditions where R5F can deadlock:
	255	* 1.When software is performing series of store operations to
	256	* cacheable write back/write allocate memory region and later
	257	* on software execute barrier operation (DSB or DMB). R5F may
	258	* hang at the barrier instruction.
	259	* 2.When software is performing a mix of load and store operations
	260	* within a tight loop and store operations are all writing to
	261	* cacheable write back/write allocates memory regions, R5F may
	262	* hang at one of the load instruction.
	263	*
	264	* To avoid the above two conditions disable linefill optimization
	265	* inside Cortex R5F.
	266	*/
	267	asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (actlr));
	268	actlr \|= (1 << 13); /* Set DLFO bit */
	269	asm("mcr p15, 0, %0, c1, c0, 1" : : "r" (actlr));
	270	}
	271	#endif