[u-boot.git] / include / configs / MPC8349ITX.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright (C) Freescale Semiconductor, Inc. 2006.
 */

/*
 MPC8349E-mITX and MPC8349E-mITX-GP board configuration file

 Memory map:

 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB)
 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB)
 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB)
 0xE000_0000-0xEFFF_FFFF IMMR (1 MB)
 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB)
 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB)
 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only)
 0xF001_0000-0xF001_FFFF Local bus expansion slot
 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only)
 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory
 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only)

 I2C address list:
						Align.	Board
 Bus	Addr	Part No.	Description	Length	Location
 ----------------------------------------------------------------
 I2C0	0x50	M24256-BWMN6P	Board EEPROM	2	U64

 I2C1	0x20	PCF8574		I2C Expander	0	U8
 I2C1	0x21	PCF8574		I2C Expander	0	U10
 I2C1	0x38	PCF8574A	I2C Expander	0	U8
 I2C1	0x39	PCF8574A	I2C Expander	0	U10
 I2C1	0x51	(DDR)		DDR EEPROM	1	U1
 I2C1	0x68	DS1339		RTC		1	U68

 Note that a given board has *either* a pair of 8574s or a pair of 8574As.
*/

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_MISC_INIT_F

/*
 * On-board devices
 */

#ifdef CONFIG_TARGET_MPC8349ITX
/* The CF card interface on the back of the board */
#define CONFIG_COMPACT_FLASH
#define CONFIG_VSC7385_ENET	/* VSC7385 ethernet support */
#define CONFIG_SYS_USB_HOST	/* use the EHCI USB controller */
#endif

#define CONFIG_RTC_DS1337
#define CONFIG_SYS_I2C

/*
 * Device configurations
 */

/* I2C */
#ifdef CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_FSL_I2C2_SPEED	400000
#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100

#define CONFIG_SYS_SPD_BUS_NUM		1	/* The I2C bus for SPD */
#define CONFIG_SYS_RTC_BUS_NUM		1	/* The I2C bus for RTC */

#define CONFIG_SYS_I2C_8574_ADDR1	0x20	/* I2C1, PCF8574 */
#define CONFIG_SYS_I2C_8574_ADDR2	0x21	/* I2C1, PCF8574 */
#define CONFIG_SYS_I2C_8574A_ADDR1	0x38	/* I2C1, PCF8574A */
#define CONFIG_SYS_I2C_8574A_ADDR2	0x39	/* I2C1, PCF8574A */
#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* I2C0, Board EEPROM */
#define CONFIG_SYS_I2C_RTC_ADDR		0x68	/* I2C1, DS1339 RTC*/
#define SPD_EEPROM_ADDRESS		0x51	/* I2C1, DDR */

/* Don't probe these addresses: */
#define CONFIG_SYS_I2C_NOPROBES	{ {1, CONFIG_SYS_I2C_8574_ADDR1}, \
				 {1, CONFIG_SYS_I2C_8574_ADDR2}, \
				 {1, CONFIG_SYS_I2C_8574A_ADDR1}, \
				 {1, CONFIG_SYS_I2C_8574A_ADDR2} }
/* Bit definitions for the 8574[A] I2C expander */
				/* Board revision, 00=0.0, 01=0.1, 10=1.0 */
#define I2C_8574_REVISION	0x03
#define I2C_8574_CF		0x08	/* 1=Compact flash absent, 0=present */
#define I2C_8574_MPCICLKRN	0x10	/* MiniPCI Clk Run */
#define I2C_8574_PCI66		0x20	/* 0=33MHz PCI, 1=66MHz PCI */
#define I2C_8574_FLASHSIDE	0x40	/* 0=Reset vector from U4, 1=from U7*/

#endif

/* Compact Flash */
#ifdef CONFIG_COMPACT_FLASH

#define CONFIG_SYS_IDE_MAXBUS		1
#define CONFIG_SYS_IDE_MAXDEVICE	1

#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_CF_BASE
#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000
#define CONFIG_SYS_ATA_REG_OFFSET	0
#define CONFIG_SYS_ATA_ALT_OFFSET	0x0200
#define CONFIG_SYS_ATA_STRIDE		2

/* If a CF card is not inserted, time out quickly */
#define ATA_RESET_TIME	1

#endif

/*
 * SATA
 */
#ifdef CONFIG_SATA_SIL3114

#define CONFIG_SYS_SATA_MAX_DEVICE      4
#define CONFIG_LBA48

#endif

#ifdef CONFIG_SYS_USB_HOST
/*
 * Support USB
 */
#define CONFIG_USB_EHCI_FSL

/* Current USB implementation supports the only USB controller,
 * so we have to choose between the MPH or the DR ones */
#if 1
#define CONFIG_HAS_FSL_MPH_USB
#else
#define CONFIG_HAS_FSL_DR_USB
#endif

#endif

/*
 * DDR Setup
 */
#define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_83XX_DDR_USES_CS0
#define CONFIG_SYS_MEMTEST_START	0x1000	/* memtest region */
#define CONFIG_SYS_MEMTEST_END		0x2000

#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN \
					| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)

#define CONFIG_VERY_BIG_RAM
#define CONFIG_MAX_MEM_MAPPED   ((phys_size_t)256 << 20)

#ifdef CONFIG_SYS_I2C
#define CONFIG_SPD_EEPROM		/* use SPD EEPROM for DDR setup*/
#endif

/* No SPD? Then manually set up DDR parameters */
#ifndef CONFIG_SPD_EEPROM
    #define CONFIG_SYS_DDR_SIZE		256	/* Mb */
    #define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
					| CSCONFIG_ROW_BIT_13 \
					| CSCONFIG_COL_BIT_10)

    #define CONFIG_SYS_DDR_TIMING_1	0x26242321
    #define CONFIG_SYS_DDR_TIMING_2	0x00000800  /* P9-45, may need tuning */
#endif

/*
 *Flash on the Local Bus
 */

#define CONFIG_SYS_FLASH_BASE		0xFE000000	/* start of FLASH   */
#define CONFIG_SYS_FLASH_EMPTY_INFO
/* 127 64KB sectors + 8 8KB sectors per device */
#define CONFIG_SYS_MAX_FLASH_SECT	135
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT

/* The ITX has two flash chips, but the ITX-GP has only one.  To support both
boards, we say we have two, but don't display a message if we find only one. */
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
#define CONFIG_SYS_FLASH_BANKS_LIST	\
		{CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
#define CONFIG_SYS_FLASH_SIZE		16	/* FLASH size in MB */

/* Vitesse 7385 */

#ifdef CONFIG_VSC7385_ENET

#define CONFIG_TSEC2

/* The flash address and size of the VSC7385 firmware image */
#define CONFIG_VSC7385_IMAGE		0xFEFFE000
#define CONFIG_VSC7385_IMAGE_SIZE	8192

#endif

/*
 * BRx, ORx, LBLAWBARx, and LBLAWARx
 */


/* Vitesse 7385 */

#define CONFIG_SYS_VSC7385_BASE	0xF8000000

#ifdef CONFIG_VSC7385_ENET


#endif


#define CONFIG_SYS_LED_BASE	0xF9000000


/* Compact Flash */

#ifdef CONFIG_COMPACT_FLASH

#define CONFIG_SYS_CF_BASE	0xF0000000


#endif

/*
 * U-Boot memory configuration
 */
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */

#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#else
#undef	CONFIG_SYS_RAMBOOT
#endif

#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000	/* Initial RAM addr */
#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in RAM*/

#define CONFIG_SYS_GBL_DATA_OFFSET	\
			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
#define CONFIG_SYS_MONITOR_LEN	(512 * 1024) /* Reserve 512 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN	(256 * 1024) /* Reserved for malloc */

/*
 * Local Bus LCRR and LBCR regs
 *    LCRR:  DLL bypass, Clock divider is 4
 * External Local Bus rate is
 *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 */
#define CONFIG_SYS_LBC_LBCR	0x00000000

				/* LB sdram refresh timer, about 6us */
#define CONFIG_SYS_LBC_LSRT	0x32000000
				/* LB refresh timer prescal, 266MHz/32*/
#define CONFIG_SYS_LBC_MRTPR	0x20000000

/*
 * Serial Port
 */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE  \
		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}

#define CONSOLE			ttyS0

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)

/*
 * PCI
 */
#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE

#define CONFIG_MPC83XX_PCI2

/*
 * General PCI
 * Addresses are mapped 1-1.
 */
#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI1_MMIO_BASE	\
			(CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI1_IO_BASE		0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS		0xE2000000
#define CONFIG_SYS_PCI1_IO_SIZE		0x01000000	/* 16M */

#ifdef CONFIG_MPC83XX_PCI2
#define CONFIG_SYS_PCI2_MEM_BASE	\
			(CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE)
#define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BASE
#define CONFIG_SYS_PCI2_MEM_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI2_MMIO_BASE	\
			(CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE)
#define CONFIG_SYS_PCI2_MMIO_PHYS	CONFIG_SYS_PCI2_MMIO_BASE
#define CONFIG_SYS_PCI2_MMIO_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI2_IO_BASE		0x00000000
#define CONFIG_SYS_PCI2_IO_PHYS		\
			(CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE)
#define CONFIG_SYS_PCI2_IO_SIZE		0x01000000	/* 16M */
#endif

#ifndef CONFIG_PCI_PNP
    #define PCI_ENET0_IOADDR	0x00000000
    #define PCI_ENET0_MEMADDR	CONFIG_SYS_PCI2_MEM_BASE
    #define PCI_IDSEL_NUMBER	0x0f	/* IDSEL = AD15 */
#endif

#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */

#endif

/* TSEC */

#ifdef CONFIG_TSEC_ENET
#define CONFIG_TSEC1

#ifdef CONFIG_TSEC1
#define CONFIG_HAS_ETH0
#define CONFIG_TSEC1_NAME  "TSEC0"
#define CONFIG_SYS_TSEC1_OFFSET	0x24000
#define TSEC1_PHY_ADDR		0x1c	/* VSC8201 uses address 0x1c */
#define TSEC1_PHYIDX		0
#define TSEC1_FLAGS		TSEC_GIGABIT
#endif

#ifdef CONFIG_TSEC2
#define CONFIG_HAS_ETH1
#define CONFIG_TSEC2_NAME  "TSEC1"
#define CONFIG_SYS_TSEC2_OFFSET	0x25000

#define TSEC2_PHY_ADDR		4
#define TSEC2_PHYIDX		0
#define TSEC2_FLAGS		TSEC_GIGABIT
#endif

#define CONFIG_ETHPRIME		"Freescale TSEC"

#endif

/*
 * Environment
 */
#define CONFIG_ENV_OVERWRITE

#ifndef CONFIG_SYS_RAMBOOT
  #define CONFIG_ENV_ADDR	\
			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
  #define CONFIG_ENV_SECT_SIZE	0x10000 /* 64K (one sector) for environment */
  #define CONFIG_ENV_SIZE	0x2000
#else
  #define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - 0x1000)
  #define CONFIG_ENV_SIZE	0x2000
#endif

#define CONFIG_LOADS_ECHO	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE

/* Watchdog */
#undef CONFIG_WATCHDOG		/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */

#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
#define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 256 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
				/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)
#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */

/*
 * System performance
 */
#define CONFIG_SYS_SCCR_TSEC1CM	1	/* TSEC1 clock mode (0-3) */
#define CONFIG_SYS_SCCR_TSEC2CM	1	/* TSEC2 & I2C0 clock mode (0-3) */
#define CONFIG_SYS_SCCR_USBMPHCM 3	/* USB MPH controller's clock */
#define CONFIG_SYS_SCCR_USBDRCM	0	/* USB DR controller's clock */

/*
 * System IO Config
 */
/* Needed for gigabit to work on TSEC 1 */
#define CONFIG_SYS_SICRH SICRH_TSOBI1
				/* USB DR as device + USB MPH as host */
#define CONFIG_SYS_SICRL	(SICRL_LDP_A | SICRL_USB1)

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
#endif

/*
 * Environment Configuration
 */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_NETDEV		"eth0"

/* Default path and filenames */
#define CONFIG_ROOTPATH		"/nfsroot/rootfs"
#define CONFIG_BOOTFILE		"uImage"
				/* U-Boot image on TFTP server */
#define CONFIG_UBOOTPATH	"u-boot.bin"

#ifdef CONFIG_TARGET_MPC8349ITX
#define CONFIG_FDTFILE		"mpc8349emitx.dtb"
#else
#define CONFIG_FDTFILE		"mpc8349emitxgp.dtb"
#endif


#define CONFIG_EXTRA_ENV_SETTINGS \
	"console=" __stringify(CONSOLE) "\0"			\
	"netdev=" CONFIG_NETDEV "\0"					\
	"uboot=" CONFIG_UBOOTPATH "\0"					\
	"tftpflash=tftpboot $loadaddr $uboot; "				\
		"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
			" +$filesize; "	\
		"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
			" +$filesize; "	\
		"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
			" $filesize; "	\
		"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
			" +$filesize; "	\
		"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
			" $filesize\0"	\
	"fdtaddr=780000\0"						\
	"fdtfile=" CONFIG_FDTFILE "\0"

#define CONFIG_NFSBOOTCOMMAND						\
	"setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath"	\
	" ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
	" console=$console,$baudrate $othbootargs; "			\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr - $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND						\
	"setenv bootargs root=/dev/ram rw"				\
	" console=$console,$baudrate $othbootargs; "			\
	"tftp $ramdiskaddr $ramdiskfile;"				\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr $ramdiskaddr $fdtaddr"

#endif
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
2ad6b513	2	/*
4c2e3da8	3	* Copyright (C) Freescale Semiconductor, Inc. 2006.
2ad6b513 TT	4	*/
	5
	6	/*
7a78f148	7	MPC8349E-mITX and MPC8349E-mITX-GP board configuration file
2ad6b513 TT	8
	9	Memory map:
	10
	11	0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB)
	12	0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB)
	13	0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB)
	14	0xE000_0000-0xEFFF_FFFF IMMR (1 MB)
	15	0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB)
	16	0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB)
7a78f148	17	0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only)
2ad6b513	18	0xF001_0000-0xF001_FFFF Local bus expansion slot
7a78f148 TT	19	0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only)
	20	0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory
	21	0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only)
2ad6b513 TT	22
2ad6b513 TT	23	I2C address list:
dd520bf3 WD	24	Align. Board
dd520bf3 WD	25	Bus Addr Part No. Description Length Location
2ad6b513	26	----------------------------------------------------------------
dd520bf3	27	I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64
2ad6b513	28
dd520bf3 WD	29	I2C1 0x20 PCF8574 I2C Expander 0 U8
	30	I2C1 0x21 PCF8574 I2C Expander 0 U10
	31	I2C1 0x38 PCF8574A I2C Expander 0 U8
	32	I2C1 0x39 PCF8574A I2C Expander 0 U10
	33	I2C1 0x51 (DDR) DDR EEPROM 1 U1
	34	I2C1 0x68 DS1339 RTC 1 U68
2ad6b513 TT	35
	36	Note that a given board has either a pair of 8574s or a pair of 8574As.
	37	*/
	38
	39	#ifndef __CONFIG_H
	40	#define __CONFIG_H
	41
89c7784e	42	#define CONFIG_MISC_INIT_F
7a78f148	43
89c7784e TT	44	/*
	45	* On-board devices
	46	*/
2ad6b513	47
4cb06d3e	48	#ifdef CONFIG_TARGET_MPC8349ITX
396abba2 JH	49	/* The CF card interface on the back of the board */
396abba2 JH	50	#define CONFIG_COMPACT_FLASH
89c7784e	51	#define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */
c31e1326	52	#define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */
7a78f148	53	#endif
2ad6b513	54
7a78f148	55	#define CONFIG_RTC_DS1337
00f792e0	56	#define CONFIG_SYS_I2C
2ad6b513	57
7a78f148 TT	58	/*
	59	* Device configurations
	60	*/
	61
	62	/* I2C */
00f792e0 HS	63	#ifdef CONFIG_SYS_I2C
	64	#define CONFIG_SYS_I2C_FSL
	65	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	66	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	67	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	68	#define CONFIG_SYS_FSL_I2C2_SPEED 400000
	69	#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
	70	#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
2ad6b513	71
6d0f6bcf	72	#define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */
b7be63ab	73	#define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */
6d0f6bcf JCPV	74
	75	#define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */
	76	#define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */
	77	#define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */
	78	#define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */
	79	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */
396abba2 JH	80	#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/
396abba2 JH	81	#define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */
2ad6b513	82
2ad6b513	83	/* Don't probe these addresses: */
396abba2	84	#define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \
6d0f6bcf JCPV	85	{1, CONFIG_SYS_I2C_8574_ADDR2}, \
6d0f6bcf JCPV	86	{1, CONFIG_SYS_I2C_8574A_ADDR1}, \
396abba2	87	{1, CONFIG_SYS_I2C_8574A_ADDR2} }
2ad6b513	88	/* Bit definitions for the 8574[A] I2C expander */
396abba2 JH	89	/* Board revision, 00=0.0, 01=0.1, 10=1.0 */
396abba2 JH	90	#define I2C_8574_REVISION 0x03
2ad6b513 TT	91	#define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */
	92	#define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */
	93	#define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */
	94	#define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/
	95
2ad6b513 TT	96	#endif
2ad6b513 TT	97
7a78f148 TT	98	/* Compact Flash */
7a78f148 TT	99	#ifdef CONFIG_COMPACT_FLASH
2ad6b513	100
6d0f6bcf JCPV	101	#define CONFIG_SYS_IDE_MAXBUS 1
6d0f6bcf JCPV	102	#define CONFIG_SYS_IDE_MAXDEVICE 1
2ad6b513	103
6d0f6bcf JCPV	104	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
	105	#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE
	106	#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000
	107	#define CONFIG_SYS_ATA_REG_OFFSET 0
	108	#define CONFIG_SYS_ATA_ALT_OFFSET 0x0200
	109	#define CONFIG_SYS_ATA_STRIDE 2
2ad6b513	110
396abba2 JH	111	/* If a CF card is not inserted, time out quickly */
396abba2 JH	112	#define ATA_RESET_TIME 1
2ad6b513	113
c9e34fe2 VG	114	#endif
	115
	116	/*
	117	* SATA
	118	*/
	119	#ifdef CONFIG_SATA_SIL3114
	120
	121	#define CONFIG_SYS_SATA_MAX_DEVICE 4
c9e34fe2	122	#define CONFIG_LBA48
2ad6b513	123
7a78f148	124	#endif
2ad6b513	125
c31e1326 VG	126	#ifdef CONFIG_SYS_USB_HOST
	127	/*
	128	* Support USB
	129	*/
c31e1326 VG	130	#define CONFIG_USB_EHCI_FSL
	131
	132	/* Current USB implementation supports the only USB controller,
	133	* so we have to choose between the MPH or the DR ones */
	134	#if 1
	135	#define CONFIG_HAS_FSL_MPH_USB
	136	#else
	137	#define CONFIG_HAS_FSL_DR_USB
	138	#endif
	139
	140	#endif
	141
2ad6b513	142	/*
7a78f148	143	* DDR Setup
2ad6b513	144	*/
396abba2	145	#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
6d0f6bcf JCPV	146	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
	147	#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
	148	#define CONFIG_SYS_83XX_DDR_USES_CS0
396abba2	149	#define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */
6d0f6bcf JCPV	150	#define CONFIG_SYS_MEMTEST_END 0x2000
6d0f6bcf JCPV	151
396abba2 JH	152	#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
396abba2 JH	153	\| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
f64702b7	154
b7be63ab VG	155	#define CONFIG_VERY_BIG_RAM
	156	#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20)
	157
00f792e0	158	#ifdef CONFIG_SYS_I2C
7a78f148 TT	159	#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
	160	#endif
	161
396abba2 JH	162	/* No SPD? Then manually set up DDR parameters */
	163	#ifndef CONFIG_SPD_EEPROM
	164	#define CONFIG_SYS_DDR_SIZE 256 /* Mb */
2e651b24	165	#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
396abba2 JH	166	\| CSCONFIG_ROW_BIT_13 \
396abba2 JH	167	\| CSCONFIG_COL_BIT_10)
2ad6b513	168
6d0f6bcf JCPV	169	#define CONFIG_SYS_DDR_TIMING_1 0x26242321
6d0f6bcf JCPV	170	#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */
2ad6b513 TT	171	#endif
2ad6b513 TT	172
7a78f148 TT	173	/*
	174	*Flash on the Local Bus
	175	*/
	176
6d0f6bcf JCPV	177	#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
6d0f6bcf JCPV	178	#define CONFIG_SYS_FLASH_EMPTY_INFO
396abba2 JH	179	/* 127 64KB sectors + 8 8KB sectors per device */
396abba2 JH	180	#define CONFIG_SYS_MAX_FLASH_SECT 135
6d0f6bcf JCPV	181	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	182	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	183	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
7a78f148 TT	184
	185	/* The ITX has two flash chips, but the ITX-GP has only one. To support both
	186	boards, we say we have two, but don't display a message if we find only one. */
6d0f6bcf	187	#define CONFIG_SYS_FLASH_QUIET_TEST
396abba2 JH	188	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
	189	#define CONFIG_SYS_FLASH_BANKS_LIST \
	190	{CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
	191	#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */
7a78f148	192
89c7784e TT	193	/* Vitesse 7385 */
	194
	195	#ifdef CONFIG_VSC7385_ENET
	196
	197	#define CONFIG_TSEC2
	198
	199	/* The flash address and size of the VSC7385 firmware image */
	200	#define CONFIG_VSC7385_IMAGE 0xFEFFE000
	201	#define CONFIG_VSC7385_IMAGE_SIZE 8192
	202
	203	#endif
	204
7a78f148 TT	205	/*
	206	* BRx, ORx, LBLAWBARx, and LBLAWARx
	207	*/
	208
a8f97539	209
7a78f148	210	/* Vitesse 7385 */
2ad6b513	211
6d0f6bcf	212	#define CONFIG_SYS_VSC7385_BASE 0xF8000000
2ad6b513	213
89c7784e TT	214	#ifdef CONFIG_VSC7385_ENET
89c7784e TT	215
a8f97539	216
7a78f148	217	#endif
2ad6b513	218
7a78f148	219
396abba2	220	#define CONFIG_SYS_LED_BASE 0xF9000000
a8f97539	221
7a78f148 TT	222
7a78f148 TT	223	/* Compact Flash */
2ad6b513 TT	224
	225	#ifdef CONFIG_COMPACT_FLASH
	226
396abba2	227	#define CONFIG_SYS_CF_BASE 0xF0000000
2ad6b513	228
2ad6b513	229
2ad6b513 TT	230	#endif
2ad6b513 TT	231
7a78f148 TT	232	/*
	233	* U-Boot memory configuration
	234	*/
14d0a02a	235	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
2ad6b513	236
6d0f6bcf JCPV	237	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	238	#define CONFIG_SYS_RAMBOOT
2ad6b513	239	#else
6d0f6bcf	240	#undef CONFIG_SYS_RAMBOOT
2ad6b513 TT	241	#endif
2ad6b513 TT	242
6d0f6bcf	243	#define CONFIG_SYS_INIT_RAM_LOCK
396abba2 JH	244	#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
396abba2 JH	245	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
2ad6b513	246
396abba2 JH	247	#define CONFIG_SYS_GBL_DATA_OFFSET \
396abba2 JH	248	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	249	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
2ad6b513	250
6d0f6bcf	251	/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
16c8c170	252	#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
c8a90646	253	#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
2ad6b513 TT	254
	255	/*
	256	* Local Bus LCRR and LBCR regs
	257	* LCRR: DLL bypass, Clock divider is 4
	258	* External Local Bus rate is
	259	* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
	260	*/
6d0f6bcf	261	#define CONFIG_SYS_LBC_LBCR 0x00000000
2ad6b513	262
396abba2 JH	263	/* LB sdram refresh timer, about 6us */
	264	#define CONFIG_SYS_LBC_LSRT 0x32000000
	265	/* LB refresh timer prescal, 266MHz/32*/
	266	#define CONFIG_SYS_LBC_MRTPR 0x20000000
2ad6b513	267
2ad6b513 TT	268	/*
	269	* Serial Port
	270	*/
6d0f6bcf JCPV	271	#define CONFIG_SYS_NS16550_SERIAL
	272	#define CONFIG_SYS_NS16550_REG_SIZE 1
	273	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
2ad6b513	274
6d0f6bcf	275	#define CONFIG_SYS_BAUDRATE_TABLE \
396abba2	276	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
7a78f148	277
83302fb8	278	#define CONSOLE ttyS0
2ad6b513	279
6d0f6bcf JCPV	280	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
6d0f6bcf JCPV	281	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
2ad6b513	282
7a78f148 TT	283	/*
	284	* PCI
	285	*/
2ad6b513	286	#ifdef CONFIG_PCI
842033e6	287	#define CONFIG_PCI_INDIRECT_BRIDGE
2ad6b513 TT	288
	289	#define CONFIG_MPC83XX_PCI2
	290
	291	/*
	292	* General PCI
	293	* Addresses are mapped 1-1.
	294	*/
6d0f6bcf JCPV	295	#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
	296	#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
	297	#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
396abba2 JH	298	#define CONFIG_SYS_PCI1_MMIO_BASE \
396abba2 JH	299	(CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
6d0f6bcf JCPV	300	#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
6d0f6bcf JCPV	301	#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
396abba2 JH	302	#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
	303	#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
	304	#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */
2ad6b513 TT	305
2ad6b513 TT	306	#ifdef CONFIG_MPC83XX_PCI2
396abba2 JH	307	#define CONFIG_SYS_PCI2_MEM_BASE \
396abba2 JH	308	(CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE)
6d0f6bcf JCPV	309	#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
6d0f6bcf JCPV	310	#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
396abba2 JH	311	#define CONFIG_SYS_PCI2_MMIO_BASE \
396abba2 JH	312	(CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE)
6d0f6bcf JCPV	313	#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
6d0f6bcf JCPV	314	#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
396abba2 JH	315	#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
	316	#define CONFIG_SYS_PCI2_IO_PHYS \
	317	(CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE)
	318	#define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */
2ad6b513 TT	319	#endif
2ad6b513 TT	320
2ad6b513 TT	321	#ifndef CONFIG_PCI_PNP
2ad6b513 TT	322	#define PCI_ENET0_IOADDR 0x00000000
6d0f6bcf	323	#define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE
2ad6b513 TT	324	#define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */
	325	#endif
	326
	327	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
	328
	329	#endif
	330
	331	/* TSEC */
	332
	333	#ifdef CONFIG_TSEC_ENET
255a3577	334	#define CONFIG_TSEC1
2ad6b513	335
255a3577	336	#ifdef CONFIG_TSEC1
10327dc5	337	#define CONFIG_HAS_ETH0
255a3577	338	#define CONFIG_TSEC1_NAME "TSEC0"
6d0f6bcf	339	#define CONFIG_SYS_TSEC1_OFFSET 0x24000
dd520bf3	340	#define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */
2ad6b513	341	#define TSEC1_PHYIDX 0
3a79013e	342	#define TSEC1_FLAGS TSEC_GIGABIT
2ad6b513 TT	343	#endif
2ad6b513 TT	344
255a3577	345	#ifdef CONFIG_TSEC2
7a78f148	346	#define CONFIG_HAS_ETH1
255a3577	347	#define CONFIG_TSEC2_NAME "TSEC1"
6d0f6bcf	348	#define CONFIG_SYS_TSEC2_OFFSET 0x25000
89c7784e	349
2ad6b513 TT	350	#define TSEC2_PHY_ADDR 4
2ad6b513 TT	351	#define TSEC2_PHYIDX 0
3a79013e	352	#define TSEC2_FLAGS TSEC_GIGABIT
2ad6b513 TT	353	#endif
	354
	355	#define CONFIG_ETHPRIME "Freescale TSEC"
	356
	357	#endif
	358
2ad6b513 TT	359	/*
	360	* Environment
	361	*/
7a78f148 TT	362	#define CONFIG_ENV_OVERWRITE
7a78f148 TT	363
6d0f6bcf	364	#ifndef CONFIG_SYS_RAMBOOT
396abba2 JH	365	#define CONFIG_ENV_ADDR \
396abba2 JH	366	(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
0e8d1586	367	#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */
396abba2	368	#define CONFIG_ENV_SIZE 0x2000
2ad6b513	369	#else
396abba2 JH	370	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
396abba2 JH	371	#define CONFIG_ENV_SIZE 0x2000
2ad6b513 TT	372	#endif
	373
	374	#define CONFIG_LOADS_ECHO /* echo on for serial download */
6d0f6bcf	375	#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
2ad6b513	376
659e2f67 JL	377	/*
	378	* BOOTP options
	379	*/
	380	#define CONFIG_BOOTP_BOOTFILESIZE
659e2f67	381
2ad6b513	382	/* Watchdog */
2ad6b513	383	#undef CONFIG_WATCHDOG /* watchdog disabled */
2ad6b513 TT	384
	385	/*
	386	* Miscellaneous configurable options
	387	*/
7a78f148	388
6d0f6bcf	389	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
05f91a65	390	#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
7a78f148	391
2ad6b513 TT	392	/*
2ad6b513 TT	393	* For booting Linux, the board info and command line data
9f530d59	394	* have to be in the first 256 MB of memory, since this is
2ad6b513 TT	395	* the maximum mapped by the Linux kernel during initialization.
2ad6b513 TT	396	*/
396abba2 JH	397	/* Initial Memory map for Linux*/
396abba2 JH	398	#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
63865278	399	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
2ad6b513	400
7a78f148 TT	401	/*
	402	* System performance
	403	*/
6d0f6bcf JCPV	404	#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
6d0f6bcf JCPV	405	#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
c31e1326 VG	406	#define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */
c31e1326 VG	407	#define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */
2ad6b513	408
7a78f148 TT	409	/*
	410	* System IO Config
	411	*/
396abba2 JH	412	/* Needed for gigabit to work on TSEC 1 */
	413	#define CONFIG_SYS_SICRH SICRH_TSOBI1
	414	/* USB DR as device + USB MPH as host */
	415	#define CONFIG_SYS_SICRL (SICRL_LDP_A \| SICRL_USB1)
2ad6b513	416
8ea5499a	417	#if defined(CONFIG_CMD_KGDB)
2ad6b513	418	#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
2ad6b513 TT	419	#endif
2ad6b513 TT	420
2ad6b513 TT	421	/*
	422	* Environment Configuration
	423	*/
	424	#define CONFIG_ENV_OVERWRITE
	425
396abba2	426	#define CONFIG_NETDEV "eth0"
2ad6b513	427
7a78f148	428	/* Default path and filenames */
8b3637c6	429	#define CONFIG_ROOTPATH "/nfsroot/rootfs"
b3f44c21	430	#define CONFIG_BOOTFILE "uImage"
396abba2 JH	431	/* U-Boot image on TFTP server */
396abba2 JH	432	#define CONFIG_UBOOTPATH "u-boot.bin"
2ad6b513	433
4cb06d3e	434	#ifdef CONFIG_TARGET_MPC8349ITX
396abba2	435	#define CONFIG_FDTFILE "mpc8349emitx.dtb"
2ad6b513	436	#else
396abba2	437	#define CONFIG_FDTFILE "mpc8349emitxgp.dtb"
2ad6b513 TT	438	#endif
2ad6b513 TT	439
7a78f148	440
dd520bf3	441	#define CONFIG_EXTRA_ENV_SETTINGS \
83302fb8	442	"console=" __stringify(CONSOLE) "\0" \
396abba2 JH	443	"netdev=" CONFIG_NETDEV "\0" \
396abba2 JH	444	"uboot=" CONFIG_UBOOTPATH "\0" \
53677ef1	445	"tftpflash=tftpboot $loadaddr $uboot; " \
5368c55d MV	446	"protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
	447	" +$filesize; " \
	448	"erase " __stringify(CONFIG_SYS_TEXT_BASE) \
	449	" +$filesize; " \
	450	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
	451	" $filesize; " \
	452	"protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
	453	" +$filesize; " \
	454	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
	455	" $filesize\0" \
05f91a65	456	"fdtaddr=780000\0" \
396abba2	457	"fdtfile=" CONFIG_FDTFILE "\0"
bf0b542d	458
dd520bf3	459	#define CONFIG_NFSBOOTCOMMAND \
7a78f148	460	"setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \
396abba2	461	" ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
7a78f148 TT	462	" console=$console,$baudrate $othbootargs; " \
	463	"tftp $loadaddr $bootfile;" \
	464	"tftp $fdtaddr $fdtfile;" \
	465	"bootm $loadaddr - $fdtaddr"
bf0b542d	466
dd520bf3	467	#define CONFIG_RAMBOOTCOMMAND \
7a78f148 TT	468	"setenv bootargs root=/dev/ram rw" \
	469	" console=$console,$baudrate $othbootargs; " \
	470	"tftp $ramdiskaddr $ramdiskfile;" \
	471	"tftp $loadaddr $bootfile;" \
	472	"tftp $fdtaddr $fdtfile;" \
	473	"bootm $loadaddr $ramdiskaddr $fdtaddr"
2ad6b513	474
2ad6b513	475	#endif