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2ad6b513 TT |
1 | /* |
2 | * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. | |
3 | * | |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | /* | |
7a78f148 | 24 | MPC8349E-mITX and MPC8349E-mITX-GP board configuration file |
2ad6b513 TT |
25 | |
26 | Memory map: | |
27 | ||
28 | 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB) | |
29 | 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB) | |
30 | 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB) | |
31 | 0xE000_0000-0xEFFF_FFFF IMMR (1 MB) | |
32 | 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB) | |
33 | 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB) | |
7a78f148 | 34 | 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only) |
2ad6b513 | 35 | 0xF001_0000-0xF001_FFFF Local bus expansion slot |
7a78f148 TT |
36 | 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only) |
37 | 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory | |
38 | 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only) | |
2ad6b513 TT |
39 | |
40 | I2C address list: | |
dd520bf3 WD |
41 | Align. Board |
42 | Bus Addr Part No. Description Length Location | |
2ad6b513 | 43 | ---------------------------------------------------------------- |
dd520bf3 | 44 | I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64 |
2ad6b513 | 45 | |
dd520bf3 WD |
46 | I2C1 0x20 PCF8574 I2C Expander 0 U8 |
47 | I2C1 0x21 PCF8574 I2C Expander 0 U10 | |
48 | I2C1 0x38 PCF8574A I2C Expander 0 U8 | |
49 | I2C1 0x39 PCF8574A I2C Expander 0 U10 | |
50 | I2C1 0x51 (DDR) DDR EEPROM 1 U1 | |
51 | I2C1 0x68 DS1339 RTC 1 U68 | |
2ad6b513 TT |
52 | |
53 | Note that a given board has *either* a pair of 8574s or a pair of 8574As. | |
54 | */ | |
55 | ||
56 | #ifndef __CONFIG_H | |
57 | #define __CONFIG_H | |
58 | ||
7a78f148 TT |
59 | #if (TEXT_BASE == 0xFE000000) |
60 | #define CFG_LOWBOOT | |
61 | #endif | |
2ad6b513 TT |
62 | |
63 | /* | |
64 | * High Level Configuration Options | |
65 | */ | |
66 | #define CONFIG_MPC834X /* MPC834x family (8343, 8347, 8349) */ | |
67 | #define CONFIG_MPC8349 /* MPC8349 specific */ | |
68 | ||
7a78f148 TT |
69 | #define CFG_IMMR 0xE0000000 /* The IMMR is relocated to here */ |
70 | ||
71 | ||
72 | /* On-board devices */ | |
2ad6b513 | 73 | |
7a78f148 | 74 | #ifdef CONFIG_MPC8349ITX |
2ad6b513 | 75 | #define CONFIG_COMPACT_FLASH /* The CF card interface on the back of the board */ |
7a78f148 TT |
76 | #define CONFIG_VSC7385 /* The Vitesse 7385 5-port switch */ |
77 | #endif | |
2ad6b513 | 78 | |
7a78f148 TT |
79 | #define CONFIG_PCI |
80 | #define CONFIG_RTC_DS1337 | |
2ad6b513 | 81 | #define CONFIG_HARD_I2C |
7a78f148 | 82 | #define CONFIG_TSEC_ENET /* TSEC Ethernet support */ |
2ad6b513 | 83 | |
7a78f148 TT |
84 | /* |
85 | * Device configurations | |
86 | */ | |
87 | ||
88 | /* I2C */ | |
2ad6b513 TT |
89 | #ifdef CONFIG_HARD_I2C |
90 | ||
91 | #define CONFIG_MISC_INIT_F | |
92 | #define CONFIG_MISC_INIT_R | |
93 | ||
be5e6181 | 94 | #define CONFIG_FSL_I2C |
2ad6b513 TT |
95 | #define CONFIG_I2C_MULTI_BUS |
96 | #define CONFIG_I2C_CMD_TREE | |
dd520bf3 WD |
97 | #define CFG_I2C_OFFSET 0x3000 |
98 | #define CFG_I2C2_OFFSET 0x3100 | |
be5e6181 | 99 | #define CFG_SPD_BUS_NUM 1 /* The I2C bus for SPD */ |
2ad6b513 | 100 | |
be5e6181 TT |
101 | #define CFG_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */ |
102 | #define CFG_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */ | |
103 | #define CFG_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */ | |
104 | #define CFG_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */ | |
dd520bf3 | 105 | #define CFG_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */ |
be5e6181 TT |
106 | #define CFG_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/ |
107 | #define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */ | |
2ad6b513 TT |
108 | |
109 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ | |
110 | #define CFG_I2C_SLAVE 0x7F | |
111 | ||
112 | /* Don't probe these addresses: */ | |
dd520bf3 | 113 | #define CFG_I2C_NOPROBES {{1, CFG_I2C_8574_ADDR1}, \ |
2ad6b513 TT |
114 | {1, CFG_I2C_8574_ADDR2}, \ |
115 | {1, CFG_I2C_8574A_ADDR1}, \ | |
116 | {1, CFG_I2C_8574A_ADDR2}} | |
117 | /* Bit definitions for the 8574[A] I2C expander */ | |
118 | #define I2C_8574_REVISION 0x03 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */ | |
119 | #define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */ | |
120 | #define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */ | |
121 | #define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */ | |
122 | #define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/ | |
123 | ||
124 | #undef CONFIG_SOFT_I2C | |
125 | ||
126 | #endif | |
127 | ||
7a78f148 TT |
128 | /* Compact Flash */ |
129 | #ifdef CONFIG_COMPACT_FLASH | |
2ad6b513 | 130 | |
7a78f148 TT |
131 | #define CFG_IDE_MAXBUS 1 |
132 | #define CFG_IDE_MAXDEVICE 1 | |
2ad6b513 | 133 | |
7a78f148 TT |
134 | #define CFG_ATA_IDE0_OFFSET 0x0000 |
135 | #define CFG_ATA_BASE_ADDR CFG_CF_BASE | |
136 | #define CFG_ATA_DATA_OFFSET 0x0000 | |
137 | #define CFG_ATA_REG_OFFSET 0 | |
138 | #define CFG_ATA_ALT_OFFSET 0x0200 | |
139 | #define CFG_ATA_STRIDE 2 | |
2ad6b513 | 140 | |
7a78f148 | 141 | #define ATA_RESET_TIME 1 /* If a CF card is not inserted, time out quickly */ |
2ad6b513 | 142 | |
7a78f148 | 143 | #define CONFIG_DOS_PARTITION |
2ad6b513 | 144 | |
7a78f148 | 145 | #endif |
2ad6b513 TT |
146 | |
147 | /* | |
7a78f148 | 148 | * DDR Setup |
2ad6b513 | 149 | */ |
7a78f148 TT |
150 | #define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ |
151 | #define CFG_SDRAM_BASE CFG_DDR_BASE | |
152 | #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE | |
2ad6b513 | 153 | #define CFG_83XX_DDR_USES_CS0 |
7a78f148 TT |
154 | #define CFG_MEMTEST_START 0x1000 /* memtest region */ |
155 | #define CFG_MEMTEST_END 0x2000 | |
2ad6b513 | 156 | |
7a78f148 TT |
157 | #ifdef CONFIG_HARD_I2C |
158 | #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ | |
159 | #endif | |
160 | ||
161 | #ifndef CONFIG_SPD_EEPROM /* No SPD? Then manually set up DDR parameters */ | |
2ad6b513 TT |
162 | #define CFG_DDR_SIZE 256 /* Mb */ |
163 | #define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) | |
164 | ||
165 | #define CFG_DDR_TIMING_1 0x26242321 | |
166 | #define CFG_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ | |
167 | #endif | |
168 | ||
7a78f148 TT |
169 | /* |
170 | *Flash on the Local Bus | |
171 | */ | |
172 | ||
2ad6b513 TT |
173 | #define CFG_FLASH_CFI /* use the Common Flash Interface */ |
174 | #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ | |
175 | #define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ | |
be5e6181 | 176 | #define CFG_FLASH_EMPTY_INFO |
7a78f148 TT |
177 | #define CFG_MAX_FLASH_SECT 135 /* 127 64KB sectors + 8 8KB sectors per device */ |
178 | #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
179 | #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
180 | #define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT | |
181 | ||
182 | /* The ITX has two flash chips, but the ITX-GP has only one. To support both | |
183 | boards, we say we have two, but don't display a message if we find only one. */ | |
184 | #define CFG_FLASH_QUIET_TEST | |
185 | #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ | |
186 | #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE + 0x800000} | |
187 | #define CFG_FLASH_SIZE 16 /* FLASH size in MB */ | |
188 | #define CFG_FLASH_SIZE_SHIFT 4 /* log2 of the above value */ | |
189 | ||
190 | /* | |
191 | * BRx, ORx, LBLAWBARx, and LBLAWARx | |
192 | */ | |
193 | ||
194 | /* Flash */ | |
2ad6b513 TT |
195 | |
196 | #define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_V) | |
197 | #define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ | |
198 | OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ | |
199 | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) | |
7a78f148 TT |
200 | #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE |
201 | #define CFG_LBLAWAR0_PRELIM (LBLAWAR_EN | (0x13 + CFG_FLASH_SIZE_SHIFT)) | |
2ad6b513 | 202 | |
7a78f148 | 203 | /* Vitesse 7385 */ |
2ad6b513 | 204 | |
7a78f148 | 205 | #ifdef CONFIG_VSC7385 |
2ad6b513 | 206 | |
7a78f148 | 207 | #define CFG_VSC7385_BASE 0xF8000000 |
2ad6b513 | 208 | |
7a78f148 TT |
209 | #define CFG_BR1_PRELIM (CFG_VSC7385_BASE | BR_PS_8 | BR_V) |
210 | #define CFG_OR1_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ | |
211 | OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \ | |
212 | OR_GPCM_EHTR | OR_GPCM_EAD) | |
2ad6b513 | 213 | |
7a78f148 TT |
214 | #define CFG_LBLAWBAR1_PRELIM CFG_VSC7385_BASE |
215 | #define CFG_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) | |
2ad6b513 | 216 | |
7a78f148 | 217 | #endif |
2ad6b513 | 218 | |
7a78f148 TT |
219 | /* LED */ |
220 | ||
221 | #define CFG_LED_BASE 0xF9000000 | |
2ad6b513 | 222 | #define CFG_BR2_PRELIM (CFG_LED_BASE | BR_PS_8 | BR_V) |
7a78f148 TT |
223 | #define CFG_OR2_PRELIM (OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | \ |
224 | OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_TRLX | \ | |
225 | OR_GPCM_EHTR | OR_GPCM_EAD) | |
226 | ||
227 | /* Compact Flash */ | |
2ad6b513 TT |
228 | |
229 | #ifdef CONFIG_COMPACT_FLASH | |
230 | ||
dd520bf3 | 231 | #define CFG_CF_BASE 0xF0000000 |
2ad6b513 | 232 | |
dd520bf3 WD |
233 | #define CFG_BR3_PRELIM (CFG_CF_BASE | BR_PS_16 | BR_MS_UPMA | BR_V) |
234 | #define CFG_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) | |
2ad6b513 | 235 | |
7a78f148 TT |
236 | #define CFG_LBLAWBAR3_PRELIM CFG_CF_BASE |
237 | #define CFG_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) | |
2ad6b513 TT |
238 | |
239 | #endif | |
240 | ||
7a78f148 TT |
241 | /* |
242 | * U-Boot memory configuration | |
243 | */ | |
dd520bf3 | 244 | #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ |
2ad6b513 | 245 | |
2ad6b513 TT |
246 | #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) |
247 | #define CFG_RAMBOOT | |
248 | #else | |
dd520bf3 | 249 | #undef CFG_RAMBOOT |
2ad6b513 TT |
250 | #endif |
251 | ||
252 | #define CONFIG_L1_INIT_RAM | |
253 | #define CFG_INIT_RAM_LOCK | |
7a78f148 TT |
254 | #define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ |
255 | #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ | |
2ad6b513 | 256 | |
7a78f148 | 257 | #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ |
2ad6b513 TT |
258 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
259 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
260 | ||
dd520bf3 WD |
261 | #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
262 | #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ | |
2ad6b513 TT |
263 | |
264 | /* | |
265 | * Local Bus LCRR and LBCR regs | |
266 | * LCRR: DLL bypass, Clock divider is 4 | |
267 | * External Local Bus rate is | |
268 | * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV | |
269 | */ | |
270 | #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) | |
271 | #define CFG_LBC_LBCR 0x00000000 | |
272 | ||
2ad6b513 TT |
273 | #define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ |
274 | #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32*/ | |
275 | ||
2ad6b513 TT |
276 | /* |
277 | * Serial Port | |
278 | */ | |
279 | #define CONFIG_CONS_INDEX 1 | |
280 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
281 | #define CFG_NS16550 | |
282 | #define CFG_NS16550_SERIAL | |
283 | #define CFG_NS16550_REG_SIZE 1 | |
284 | #define CFG_NS16550_CLK get_bus_freq(0) | |
285 | ||
286 | #define CFG_BAUDRATE_TABLE \ | |
7a78f148 TT |
287 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
288 | ||
289 | #define CONFIG_BAUDRATE 115200 | |
2ad6b513 | 290 | |
d239d74b TT |
291 | #define CFG_NS16550_COM1 (CFG_IMMR + 0x4500) |
292 | #define CFG_NS16550_COM2 (CFG_IMMR + 0x4600) | |
2ad6b513 | 293 | |
bf0b542d | 294 | /* pass open firmware flat tree */ |
7a78f148 TT |
295 | #define CONFIG_OF_FLAT_TREE |
296 | #define CONFIG_OF_BOARD_SETUP | |
bf0b542d KP |
297 | |
298 | /* maximum size of the flat tree (8K) */ | |
299 | #define OF_FLAT_TREE_MAX_SIZE 8192 | |
300 | ||
301 | #define OF_CPU "PowerPC,8349@0" | |
302 | #define OF_SOC "soc8349@e0000000" | |
303 | #define OF_TBCLK (bd->bi_busfreq / 4) | |
304 | #define OF_STDOUT_PATH "/soc8349@e0000000/serial@4500" | |
2ad6b513 | 305 | |
7a78f148 TT |
306 | /* |
307 | * PCI | |
308 | */ | |
2ad6b513 TT |
309 | #ifdef CONFIG_PCI |
310 | ||
311 | #define CONFIG_MPC83XX_PCI2 | |
312 | ||
313 | /* | |
314 | * General PCI | |
315 | * Addresses are mapped 1-1. | |
316 | */ | |
317 | #define CFG_PCI1_MEM_BASE 0x80000000 | |
318 | #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE | |
319 | #define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ | |
320 | #define CFG_PCI1_MMIO_BASE (CFG_PCI1_MEM_BASE + CFG_PCI1_MEM_SIZE) | |
321 | #define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE | |
322 | #define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ | |
323 | #define CFG_PCI1_IO_BASE 0x00000000 | |
324 | #define CFG_PCI1_IO_PHYS 0xE2000000 | |
325 | #define CFG_PCI1_IO_SIZE 0x01000000 /* 16M */ | |
326 | ||
327 | #ifdef CONFIG_MPC83XX_PCI2 | |
328 | #define CFG_PCI2_MEM_BASE (CFG_PCI1_MMIO_BASE + CFG_PCI1_MMIO_SIZE) | |
329 | #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE | |
330 | #define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ | |
331 | #define CFG_PCI2_MMIO_BASE (CFG_PCI2_MEM_BASE + CFG_PCI2_MEM_SIZE) | |
332 | #define CFG_PCI2_MMIO_PHYS CFG_PCI2_MMIO_BASE | |
333 | #define CFG_PCI2_MMIO_SIZE 0x10000000 /* 256M */ | |
334 | #define CFG_PCI2_IO_BASE 0x00000000 | |
335 | #define CFG_PCI2_IO_PHYS (CFG_PCI1_IO_PHYS + CFG_PCI1_IO_SIZE) | |
336 | #define CFG_PCI2_IO_SIZE 0x01000000 /* 16M */ | |
337 | #endif | |
338 | ||
339 | #define _IO_BASE 0x00000000 /* points to PCI I/O space */ | |
340 | ||
341 | #define CONFIG_NET_MULTI | |
dd520bf3 | 342 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
2ad6b513 TT |
343 | |
344 | #ifdef CONFIG_RTL8139 | |
345 | /* This macro is used by RTL8139 but not defined in PPC architecture */ | |
346 | #define KSEG1ADDR(x) (x) | |
347 | #endif | |
348 | ||
349 | #ifndef CONFIG_PCI_PNP | |
350 | #define PCI_ENET0_IOADDR 0x00000000 | |
351 | #define PCI_ENET0_MEMADDR CFG_PCI2_MEM_BASE | |
352 | #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */ | |
353 | #endif | |
354 | ||
355 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
356 | ||
357 | #endif | |
358 | ||
7a78f148 TT |
359 | #define PCI_66M |
360 | #ifdef PCI_66M | |
361 | #define CONFIG_83XX_CLKIN 66666666 /* in Hz */ | |
362 | #else | |
363 | #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ | |
364 | #endif | |
365 | ||
2ad6b513 TT |
366 | /* TSEC */ |
367 | ||
368 | #ifdef CONFIG_TSEC_ENET | |
369 | ||
2ad6b513 | 370 | #define CONFIG_NET_MULTI |
2ad6b513 TT |
371 | #define CONFIG_MII |
372 | #define CONFIG_PHY_GIGE /* In case CFG_CMD_MII is specified */ | |
373 | ||
374 | #define CONFIG_MPC83XX_TSEC1 | |
375 | ||
376 | #ifdef CONFIG_MPC83XX_TSEC1 | |
377 | #define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" | |
dd520bf3 WD |
378 | #define CFG_TSEC1_OFFSET 0x24000 |
379 | #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ | |
2ad6b513 TT |
380 | #define TSEC1_PHYIDX 0 |
381 | #endif | |
382 | ||
383 | #ifdef CONFIG_MPC83XX_TSEC2 | |
7a78f148 | 384 | #define CONFIG_HAS_ETH1 |
2ad6b513 | 385 | #define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" |
dd520bf3 | 386 | #define CFG_TSEC2_OFFSET 0x25000 |
2ad6b513 TT |
387 | #define CONFIG_UNKNOWN_TSEC /* TSEC2 is proprietary */ |
388 | #define TSEC2_PHY_ADDR 4 | |
389 | #define TSEC2_PHYIDX 0 | |
390 | #endif | |
391 | ||
392 | #define CONFIG_ETHPRIME "Freescale TSEC" | |
393 | ||
394 | #endif | |
395 | ||
2ad6b513 TT |
396 | /* |
397 | * Environment | |
398 | */ | |
7a78f148 TT |
399 | #define CONFIG_ENV_OVERWRITE |
400 | ||
2ad6b513 TT |
401 | #ifndef CFG_RAMBOOT |
402 | #define CFG_ENV_IS_IN_FLASH | |
7a78f148 TT |
403 | #define CFG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */ |
404 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE + (4 * CFG_ENV_SECT_SIZE)) | |
2ad6b513 TT |
405 | #define CFG_ENV_SIZE 0x2000 |
406 | #else | |
407 | #define CFG_NO_FLASH /* Flash is not usable now */ | |
408 | #define CFG_ENV_IS_NOWHERE /* Store ENV in memory only */ | |
409 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) | |
410 | #define CFG_ENV_SIZE 0x2000 | |
411 | #endif | |
412 | ||
413 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ | |
414 | #define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */ | |
415 | ||
416 | /* CONFIG_COMMANDS */ | |
417 | ||
418 | #ifdef CONFIG_COMPACT_FLASH | |
419 | #define CONFIG_COMMANDS_CF (CFG_CMD_IDE | CFG_CMD_FAT) | |
420 | #else | |
421 | #define CONFIG_COMMANDS_CF 0 | |
422 | #endif | |
423 | ||
424 | #ifdef CONFIG_PCI | |
425 | #define CONFIG_COMMANDS_PCI CFG_CMD_PCI | |
426 | #else | |
427 | #define CONFIG_COMMANDS_PCI 0 | |
428 | #endif | |
429 | ||
430 | #ifdef CONFIG_HARD_I2C | |
431 | #define CONFIG_COMMANDS_I2C CFG_CMD_I2C | |
432 | #else | |
433 | #define CONFIG_COMMANDS_I2C 0 | |
434 | #endif | |
435 | ||
dd520bf3 | 436 | #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ |
2ad6b513 | 437 | CONFIG_COMMANDS_CF | \ |
dd520bf3 WD |
438 | CFG_CMD_NET | \ |
439 | CFG_CMD_PING | \ | |
440 | CONFIG_COMMANDS_I2C | \ | |
441 | CONFIG_COMMANDS_PCI | \ | |
442 | CFG_CMD_SDRAM | \ | |
2ad6b513 TT |
443 | CFG_CMD_DATE | \ |
444 | CFG_CMD_CACHE | \ | |
445 | CFG_CMD_IRQ) | |
446 | #include <cmd_confdefs.h> | |
447 | ||
448 | /* Watchdog */ | |
449 | ||
450 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
2ad6b513 TT |
451 | |
452 | /* | |
453 | * Miscellaneous configurable options | |
454 | */ | |
dd520bf3 | 455 | #define CFG_LONGHELP /* undef to save memory */ |
7a78f148 TT |
456 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
457 | #define CFG_HUSH_PARSER /* Use the HUSH parser */ | |
458 | #define CFG_PROMPT_HUSH_PS2 "> " | |
459 | ||
2ad6b513 | 460 | #define CFG_LOAD_ADDR 0x2000000 /* default load address */ |
7a78f148 TT |
461 | #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ |
462 | ||
463 | #ifdef CONFIG_MPC8349ITX | |
464 | #define CFG_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */ | |
465 | #else | |
466 | #define CFG_PROMPT "MPC8349E-mITX-GP> " /* Monitor Command Prompt */ | |
467 | #endif | |
2ad6b513 TT |
468 | |
469 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
470 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ | |
471 | #else | |
472 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
473 | #endif | |
474 | ||
dd520bf3 | 475 | #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */ |
2ad6b513 TT |
476 | #define CFG_MAXARGS 16 /* max number of command args */ |
477 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
478 | #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ | |
479 | ||
480 | /* | |
481 | * For booting Linux, the board info and command line data | |
482 | * have to be in the first 8 MB of memory, since this is | |
483 | * the maximum mapped by the Linux kernel during initialization. | |
484 | */ | |
485 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ | |
486 | ||
7a78f148 TT |
487 | /* |
488 | * Cache Configuration | |
489 | */ | |
2ad6b513 TT |
490 | #define CFG_DCACHE_SIZE 32768 |
491 | #define CFG_CACHELINE_SIZE 32 | |
492 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
493 | #define CFG_CACHELINE_SHIFT 5 /* log2 of the above value */ | |
494 | #endif | |
495 | ||
2ad6b513 TT |
496 | #define CFG_HRCW_LOW (\ |
497 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ | |
498 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
499 | HRCWL_CSB_TO_CLKIN_4X1 |\ | |
500 | HRCWL_VCO_1X2 |\ | |
501 | HRCWL_CORE_TO_CSB_2X1) | |
502 | ||
7a78f148 | 503 | #ifdef CFG_LOWBOOT |
2ad6b513 TT |
504 | #define CFG_HRCW_HIGH (\ |
505 | HRCWH_PCI_HOST |\ | |
7a78f148 | 506 | HRCWH_32_BIT_PCI |\ |
2ad6b513 | 507 | HRCWH_PCI1_ARBITER_ENABLE |\ |
7a78f148 | 508 | HRCWH_PCI2_ARBITER_ENABLE |\ |
2ad6b513 TT |
509 | HRCWH_CORE_ENABLE |\ |
510 | HRCWH_FROM_0X00000100 |\ | |
511 | HRCWH_BOOTSEQ_DISABLE |\ | |
512 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
513 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
514 | HRCWH_TSEC1M_IN_GMII |\ | |
515 | HRCWH_TSEC2M_IN_GMII ) | |
516 | #else | |
517 | #define CFG_HRCW_HIGH (\ | |
518 | HRCWH_PCI_HOST |\ | |
519 | HRCWH_32_BIT_PCI |\ | |
520 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
7a78f148 | 521 | HRCWH_PCI2_ARBITER_ENABLE |\ |
2ad6b513 TT |
522 | HRCWH_CORE_ENABLE |\ |
523 | HRCWH_FROM_0XFFF00100 |\ | |
524 | HRCWH_BOOTSEQ_DISABLE |\ | |
525 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
526 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
527 | HRCWH_TSEC1M_IN_GMII |\ | |
528 | HRCWH_TSEC2M_IN_GMII ) | |
529 | #endif | |
530 | ||
7a78f148 TT |
531 | /* |
532 | * System performance | |
533 | */ | |
2ad6b513 TT |
534 | #define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ |
535 | #define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ | |
536 | #define CFG_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ | |
537 | #define CFG_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ | |
538 | #define CFG_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ | |
be5e6181 | 539 | #define CFG_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ |
2ad6b513 | 540 | |
7a78f148 TT |
541 | /* |
542 | * System IO Config | |
543 | */ | |
2ad6b513 | 544 | #define CFG_SICRH SICRH_TSOBI1 /* Needed for gigabit to work on TSEC 1 */ |
98883332 | 545 | #define CFG_SICRL (SICRL_LDP_A | SICRL_USB1) |
2ad6b513 | 546 | |
7a78f148 TT |
547 | #define CFG_HID0_INIT 0x000000000 |
548 | #define CFG_HID0_FINAL CFG_HID0_INIT | |
2ad6b513 | 549 | |
dd520bf3 | 550 | #define CFG_HID2 HID2_HBE |
2ad6b513 | 551 | |
7a78f148 | 552 | /* DDR */ |
2ad6b513 TT |
553 | #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
554 | #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
555 | ||
7a78f148 | 556 | /* PCI */ |
2ad6b513 TT |
557 | #ifdef CONFIG_PCI |
558 | #define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) | |
559 | #define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
560 | #define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
561 | #define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
562 | #else | |
563 | #define CFG_IBAT1L 0 | |
564 | #define CFG_IBAT1U 0 | |
565 | #define CFG_IBAT2L 0 | |
566 | #define CFG_IBAT2U 0 | |
567 | #endif | |
568 | ||
569 | #ifdef CONFIG_MPC83XX_PCI2 | |
570 | #define CFG_IBAT3L (CFG_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) | |
571 | #define CFG_IBAT3U (CFG_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
572 | #define CFG_IBAT4L (CFG_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
573 | #define CFG_IBAT4U (CFG_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
574 | #else | |
575 | #define CFG_IBAT3L 0 | |
576 | #define CFG_IBAT3U 0 | |
577 | #define CFG_IBAT4L 0 | |
578 | #define CFG_IBAT4U 0 | |
579 | #endif | |
580 | ||
581 | /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ | |
d239d74b TT |
582 | #define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
583 | #define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) | |
2ad6b513 TT |
584 | |
585 | /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ | |
586 | #define CFG_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE) | |
587 | #define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) | |
588 | ||
589 | #define CFG_IBAT7L 0 | |
590 | #define CFG_IBAT7U 0 | |
591 | ||
592 | #define CFG_DBAT0L CFG_IBAT0L | |
593 | #define CFG_DBAT0U CFG_IBAT0U | |
594 | #define CFG_DBAT1L CFG_IBAT1L | |
595 | #define CFG_DBAT1U CFG_IBAT1U | |
596 | #define CFG_DBAT2L CFG_IBAT2L | |
597 | #define CFG_DBAT2U CFG_IBAT2U | |
598 | #define CFG_DBAT3L CFG_IBAT3L | |
599 | #define CFG_DBAT3U CFG_IBAT3U | |
600 | #define CFG_DBAT4L CFG_IBAT4L | |
601 | #define CFG_DBAT4U CFG_IBAT4U | |
602 | #define CFG_DBAT5L CFG_IBAT5L | |
603 | #define CFG_DBAT5U CFG_IBAT5U | |
604 | #define CFG_DBAT6L CFG_IBAT6L | |
605 | #define CFG_DBAT6U CFG_IBAT6U | |
606 | #define CFG_DBAT7L CFG_IBAT7L | |
607 | #define CFG_DBAT7U CFG_IBAT7U | |
608 | ||
609 | /* | |
610 | * Internal Definitions | |
611 | * | |
612 | * Boot Flags | |
613 | */ | |
614 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
615 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
616 | ||
617 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
618 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ | |
619 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
620 | #endif | |
621 | ||
622 | ||
623 | /* | |
624 | * Environment Configuration | |
625 | */ | |
626 | #define CONFIG_ENV_OVERWRITE | |
627 | ||
628 | #ifdef CONFIG_MPC83XX_TSEC1 | |
629 | #define CONFIG_ETHADDR 00:E0:0C:00:8C:01 | |
630 | #endif | |
631 | ||
632 | #ifdef CONFIG_MPC83XX_TSEC2 | |
2ad6b513 TT |
633 | #define CONFIG_ETH1ADDR 00:E0:0C:00:8C:02 |
634 | #endif | |
635 | ||
bf0b542d KP |
636 | #define CONFIG_IPADDR 192.168.1.253 |
637 | #define CONFIG_SERVERIP 192.168.1.1 | |
638 | #define CONFIG_GATEWAYIP 192.168.1.1 | |
2ad6b513 | 639 | #define CONFIG_NETMASK 255.255.252.0 |
98883332 | 640 | #define CONFIG_NETDEV eth0 |
2ad6b513 | 641 | |
7a78f148 | 642 | #ifdef CONFIG_MPC8349ITX |
2ad6b513 | 643 | #define CONFIG_HOSTNAME mpc8349emitx |
7a78f148 TT |
644 | #else |
645 | #define CONFIG_HOSTNAME mpc8349emitxgp | |
be5e6181 TT |
646 | #endif |
647 | ||
7a78f148 TT |
648 | /* Default path and filenames */ |
649 | #define CONFIG_ROOTPATH /nfsroot/rootfs | |
650 | #define CONFIG_BOOTFILE uImage | |
651 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ | |
2ad6b513 | 652 | |
7a78f148 TT |
653 | #ifdef CONFIG_MPC8349ITX |
654 | #define CONFIG_FDTFILE mpc8349emitx.dtb | |
2ad6b513 | 655 | #else |
7a78f148 | 656 | #define CONFIG_FDTFILE mpc8349emitxgp.dtb |
2ad6b513 TT |
657 | #endif |
658 | ||
7a78f148 TT |
659 | #define CONFIG_BOOTDELAY 0 |
660 | ||
2ad6b513 TT |
661 | #define XMK_STR(x) #x |
662 | #define MK_STR(x) XMK_STR(x) | |
663 | ||
98883332 TT |
664 | #define CONFIG_BOOTARGS \ |
665 | "root=/dev/nfs rw" \ | |
666 | " nfsroot=" MK_STR(CONFIG_SERVERIP) ":" MK_STR(CONFIG_ROOTPATH) \ | |
7a78f148 | 667 | " ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \ |
98883332 TT |
668 | MK_STR(CONFIG_GATEWAYIP) ":" MK_STR(CONFIG_NETMASK) ":" \ |
669 | MK_STR(CONFIG_HOSTNAME) ":" MK_STR(CONFIG_NETDEV) ":off" \ | |
670 | " console=ttyS0," MK_STR(CONFIG_BAUDRATE) | |
671 | ||
dd520bf3 | 672 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
7a78f148 TT |
673 | "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ |
674 | "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ | |
675 | "tftpflash=tftpboot $loadaddr $uboot; " \ | |
676 | "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ | |
677 | "erase " MK_STR(TEXT_BASE) " +$filesize; " \ | |
678 | "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ | |
679 | "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ | |
680 | "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ | |
dd520bf3 | 681 | "fdtaddr=400000\0" \ |
7a78f148 | 682 | "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" |
bf0b542d | 683 | |
dd520bf3 | 684 | #define CONFIG_NFSBOOTCOMMAND \ |
7a78f148 TT |
685 | "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \ |
686 | " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
687 | " console=$console,$baudrate $othbootargs; " \ | |
688 | "tftp $loadaddr $bootfile;" \ | |
689 | "tftp $fdtaddr $fdtfile;" \ | |
690 | "bootm $loadaddr - $fdtaddr" | |
bf0b542d | 691 | |
dd520bf3 | 692 | #define CONFIG_RAMBOOTCOMMAND \ |
7a78f148 TT |
693 | "setenv bootargs root=/dev/ram rw" \ |
694 | " console=$console,$baudrate $othbootargs; " \ | |
695 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
696 | "tftp $loadaddr $bootfile;" \ | |
697 | "tftp $fdtaddr $fdtfile;" \ | |
698 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
2ad6b513 TT |
699 | |
700 | #undef MK_STR | |
701 | #undef XMK_STR | |
702 | ||
703 | #endif |