[u-boot.git] / drivers / net / designware.c

/*
 * (C) Copyright 2010
 * Vipin Kumar, ST Micoelectronics, [email protected].
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * Designware ethernet IP driver for U-Boot
 */

#include <common.h>
#include <errno.h>
#include <miiphy.h>
#include <malloc.h>
#include <linux/compiler.h>
#include <linux/err.h>
#include <asm/io.h>
#include "designware.h"

#if !defined(CONFIG_PHYLIB)
# error "DesignWare Ether MAC requires PHYLIB - missing CONFIG_PHYLIB"
#endif

static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
{
	struct eth_mac_regs *mac_p = bus->priv;
	ulong start;
	u16 miiaddr;
	int timeout = CONFIG_MDIO_TIMEOUT;

	miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
		  ((reg << MIIREGSHIFT) & MII_REGMSK);

	writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);

	start = get_timer(0);
	while (get_timer(start) < timeout) {
		if (!(readl(&mac_p->miiaddr) & MII_BUSY))
			return readl(&mac_p->miidata);
		udelay(10);
	};

	return -ETIMEDOUT;
}

static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
			u16 val)
{
	struct eth_mac_regs *mac_p = bus->priv;
	ulong start;
	u16 miiaddr;
	int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT;

	writel(val, &mac_p->miidata);
	miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
		  ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;

	writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);

	start = get_timer(0);
	while (get_timer(start) < timeout) {
		if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
			ret = 0;
			break;
		}
		udelay(10);
	};

	return ret;
}

static int dw_mdio_init(const char *name, struct eth_mac_regs *mac_regs_p)
{
	struct mii_dev *bus = mdio_alloc();

	if (!bus) {
		printf("Failed to allocate MDIO bus\n");
		return -ENOMEM;
	}

	bus->read = dw_mdio_read;
	bus->write = dw_mdio_write;
	snprintf(bus->name, sizeof(bus->name), name);

	bus->priv = (void *)mac_regs_p;

	return mdio_register(bus);
}

static void tx_descs_init(struct dw_eth_dev *priv)
{
	struct eth_dma_regs *dma_p = priv->dma_regs_p;
	struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0];
	char *txbuffs = &priv->txbuffs[0];
	struct dmamacdescr *desc_p;
	u32 idx;

	for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
		desc_p = &desc_table_p[idx];
		desc_p->dmamac_addr = &txbuffs[idx * CONFIG_ETH_BUFSIZE];
		desc_p->dmamac_next = &desc_table_p[idx + 1];

#if defined(CONFIG_DW_ALTDESCRIPTOR)
		desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
				DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | \
				DESC_TXSTS_TXCHECKINSCTRL | \
				DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS);

		desc_p->txrx_status |= DESC_TXSTS_TXCHAIN;
		desc_p->dmamac_cntl = 0;
		desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA);
#else
		desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN;
		desc_p->txrx_status = 0;
#endif
	}

	/* Correcting the last pointer of the chain */
	desc_p->dmamac_next = &desc_table_p[0];

	/* Flush all Tx buffer descriptors at once */
	flush_dcache_range((unsigned int)priv->tx_mac_descrtable,
			   (unsigned int)priv->tx_mac_descrtable +
			   sizeof(priv->tx_mac_descrtable));

	writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
	priv->tx_currdescnum = 0;
}

static void rx_descs_init(struct dw_eth_dev *priv)
{
	struct eth_dma_regs *dma_p = priv->dma_regs_p;
	struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0];
	char *rxbuffs = &priv->rxbuffs[0];
	struct dmamacdescr *desc_p;
	u32 idx;

	/* Before passing buffers to GMAC we need to make sure zeros
	 * written there right after "priv" structure allocation were
	 * flushed into RAM.
	 * Otherwise there's a chance to get some of them flushed in RAM when
	 * GMAC is already pushing data to RAM via DMA. This way incoming from
	 * GMAC data will be corrupted. */
	flush_dcache_range((unsigned int)rxbuffs, (unsigned int)rxbuffs +
			   RX_TOTAL_BUFSIZE);

	for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
		desc_p = &desc_table_p[idx];
		desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE];
		desc_p->dmamac_next = &desc_table_p[idx + 1];

		desc_p->dmamac_cntl =
			(MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | \
				      DESC_RXCTRL_RXCHAIN;

		desc_p->txrx_status = DESC_RXSTS_OWNBYDMA;
	}

	/* Correcting the last pointer of the chain */
	desc_p->dmamac_next = &desc_table_p[0];

	/* Flush all Rx buffer descriptors at once */
	flush_dcache_range((unsigned int)priv->rx_mac_descrtable,
			   (unsigned int)priv->rx_mac_descrtable +
			   sizeof(priv->rx_mac_descrtable));

	writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
	priv->rx_currdescnum = 0;
}

static int _dw_write_hwaddr(struct dw_eth_dev *priv, u8 *mac_id)
{
	struct eth_mac_regs *mac_p = priv->mac_regs_p;
	u32 macid_lo, macid_hi;

	macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
		   (mac_id[3] << 24);
	macid_hi = mac_id[4] + (mac_id[5] << 8);

	writel(macid_hi, &mac_p->macaddr0hi);
	writel(macid_lo, &mac_p->macaddr0lo);

	return 0;
}

static void dw_adjust_link(struct eth_mac_regs *mac_p,
			   struct phy_device *phydev)
{
	u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN;

	if (!phydev->link) {
		printf("%s: No link.\n", phydev->dev->name);
		return;
	}

	if (phydev->speed != 1000)
		conf |= MII_PORTSELECT;

	if (phydev->speed == 100)
		conf |= FES_100;

	if (phydev->duplex)
		conf |= FULLDPLXMODE;

	writel(conf, &mac_p->conf);

	printf("Speed: %d, %s duplex%s\n", phydev->speed,
	       (phydev->duplex) ? "full" : "half",
	       (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
}

static void _dw_eth_halt(struct dw_eth_dev *priv)
{
	struct eth_mac_regs *mac_p = priv->mac_regs_p;
	struct eth_dma_regs *dma_p = priv->dma_regs_p;

	writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf);
	writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode);

	phy_shutdown(priv->phydev);
}

static int _dw_eth_init(struct dw_eth_dev *priv, u8 *enetaddr)
{
	struct eth_mac_regs *mac_p = priv->mac_regs_p;
	struct eth_dma_regs *dma_p = priv->dma_regs_p;
	unsigned int start;
	int ret;

	writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode);

	start = get_timer(0);
	while (readl(&dma_p->busmode) & DMAMAC_SRST) {
		if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) {
			printf("DMA reset timeout\n");
			return -ETIMEDOUT;
		}

		mdelay(100);
	};

	/* Soft reset above clears HW address registers.
	 * So we have to set it here once again */
	_dw_write_hwaddr(priv, enetaddr);

	rx_descs_init(priv);
	tx_descs_init(priv);

	writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode);

#ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE
	writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD,
	       &dma_p->opmode);
#else
	writel(readl(&dma_p->opmode) | FLUSHTXFIFO,
	       &dma_p->opmode);
#endif

	writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode);

#ifdef CONFIG_DW_AXI_BURST_LEN
	writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus);
#endif

	/* Start up the PHY */
	ret = phy_startup(priv->phydev);
	if (ret) {
		printf("Could not initialize PHY %s\n",
		       priv->phydev->dev->name);
		return ret;
	}

	dw_adjust_link(mac_p, priv->phydev);

	if (!priv->phydev->link)
		return -EIO;

	writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf);

	return 0;
}

static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length)
{
	struct eth_dma_regs *dma_p = priv->dma_regs_p;
	u32 desc_num = priv->tx_currdescnum;
	struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
	uint32_t desc_start = (uint32_t)desc_p;
	uint32_t desc_end = desc_start +
		roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
	uint32_t data_start = (uint32_t)desc_p->dmamac_addr;
	uint32_t data_end = data_start +
		roundup(length, ARCH_DMA_MINALIGN);
	/*
	 * Strictly we only need to invalidate the "txrx_status" field
	 * for the following check, but on some platforms we cannot
	 * invalidate only 4 bytes, so we flush the entire descriptor,
	 * which is 16 bytes in total. This is safe because the
	 * individual descriptors in the array are each aligned to
	 * ARCH_DMA_MINALIGN and padded appropriately.
	 */
	invalidate_dcache_range(desc_start, desc_end);

	/* Check if the descriptor is owned by CPU */
	if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
		printf("CPU not owner of tx frame\n");
		return -EPERM;
	}

	memcpy(desc_p->dmamac_addr, packet, length);

	/* Flush data to be sent */
	flush_dcache_range(data_start, data_end);

#if defined(CONFIG_DW_ALTDESCRIPTOR)
	desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
	desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & \
			       DESC_TXCTRL_SIZE1MASK;

	desc_p->txrx_status &= ~(DESC_TXSTS_MSK);
	desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA;
#else
	desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) & \
			       DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | \
			       DESC_TXCTRL_TXFIRST;

	desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
#endif

	/* Flush modified buffer descriptor */
	flush_dcache_range(desc_start, desc_end);

	/* Test the wrap-around condition. */
	if (++desc_num >= CONFIG_TX_DESCR_NUM)
		desc_num = 0;

	priv->tx_currdescnum = desc_num;

	/* Start the transmission */
	writel(POLL_DATA, &dma_p->txpolldemand);

	return 0;
}

static int _dw_eth_recv(struct dw_eth_dev *priv)
{
	u32 status, desc_num = priv->rx_currdescnum;
	struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
	int length = 0;
	uint32_t desc_start = (uint32_t)desc_p;
	uint32_t desc_end = desc_start +
		roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
	uint32_t data_start = (uint32_t)desc_p->dmamac_addr;
	uint32_t data_end;

	/* Invalidate entire buffer descriptor */
	invalidate_dcache_range(desc_start, desc_end);

	status = desc_p->txrx_status;

	/* Check  if the owner is the CPU */
	if (!(status & DESC_RXSTS_OWNBYDMA)) {

		length = (status & DESC_RXSTS_FRMLENMSK) >> \
			 DESC_RXSTS_FRMLENSHFT;

		/* Invalidate received data */
		data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
		invalidate_dcache_range(data_start, data_end);

		net_process_received_packet(desc_p->dmamac_addr, length);

		/*
		 * Make the current descriptor valid again and go to
		 * the next one
		 */
		desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA;

		/* Flush only status field - others weren't changed */
		flush_dcache_range(desc_start, desc_end);

		/* Test the wrap-around condition. */
		if (++desc_num >= CONFIG_RX_DESCR_NUM)
			desc_num = 0;
	}

	priv->rx_currdescnum = desc_num;

	return length;
}

static int dw_phy_init(struct dw_eth_dev *priv, void *dev)
{
	struct phy_device *phydev;
	int mask = 0xffffffff;

#ifdef CONFIG_PHY_ADDR
	mask = 1 << CONFIG_PHY_ADDR;
#endif

	phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
	if (!phydev)
		return -ENODEV;

	phy_connect_dev(phydev, dev);

	phydev->supported &= PHY_GBIT_FEATURES;
	phydev->advertising = phydev->supported;

	priv->phydev = phydev;
	phy_config(phydev);

	return 0;
}

static int dw_eth_init(struct eth_device *dev, bd_t *bis)
{
	return _dw_eth_init(dev->priv, dev->enetaddr);
}

static int dw_eth_send(struct eth_device *dev, void *packet, int length)
{
	return _dw_eth_send(dev->priv, packet, length);
}

static int dw_eth_recv(struct eth_device *dev)
{
	return _dw_eth_recv(dev->priv);
}

static void dw_eth_halt(struct eth_device *dev)
{
	return _dw_eth_halt(dev->priv);
}

static int dw_write_hwaddr(struct eth_device *dev)
{
	return _dw_write_hwaddr(dev->priv, dev->enetaddr);
}

int designware_initialize(ulong base_addr, u32 interface)
{
	struct eth_device *dev;
	struct dw_eth_dev *priv;

	dev = (struct eth_device *) malloc(sizeof(struct eth_device));
	if (!dev)
		return -ENOMEM;

	/*
	 * Since the priv structure contains the descriptors which need a strict
	 * buswidth alignment, memalign is used to allocate memory
	 */
	priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN,
					      sizeof(struct dw_eth_dev));
	if (!priv) {
		free(dev);
		return -ENOMEM;
	}

	memset(dev, 0, sizeof(struct eth_device));
	memset(priv, 0, sizeof(struct dw_eth_dev));

	sprintf(dev->name, "dwmac.%lx", base_addr);
	dev->iobase = (int)base_addr;
	dev->priv = priv;

	priv->dev = dev;
	priv->mac_regs_p = (struct eth_mac_regs *)base_addr;
	priv->dma_regs_p = (struct eth_dma_regs *)(base_addr +
			DW_DMA_BASE_OFFSET);

	dev->init = dw_eth_init;
	dev->send = dw_eth_send;
	dev->recv = dw_eth_recv;
	dev->halt = dw_eth_halt;
	dev->write_hwaddr = dw_write_hwaddr;

	eth_register(dev);

	priv->interface = interface;

	dw_mdio_init(dev->name, priv->mac_regs_p);
	priv->bus = miiphy_get_dev_by_name(dev->name);

	return dw_phy_init(priv, dev);
}
Commit	Line	Data
5b1b1883 VK	1	/*
	2	* (C) Copyright 2010
	3	* Vipin Kumar, ST Micoelectronics, [email protected].
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
5b1b1883 VK	6	*/
	7
	8	/*
64dcd25f	9	* Designware ethernet IP driver for U-Boot
5b1b1883 VK	10	*/
	11
	12	#include <common.h>
64dcd25f	13	#include <errno.h>
5b1b1883 VK	14	#include <miiphy.h>
5b1b1883 VK	15	#include <malloc.h>
ef76025a	16	#include <linux/compiler.h>
5b1b1883 VK	17	#include <linux/err.h>
	18	#include <asm/io.h>
	19	#include "designware.h"
	20
92a190aa AB	21	#if !defined(CONFIG_PHYLIB)
	22	# error "DesignWare Ether MAC requires PHYLIB - missing CONFIG_PHYLIB"
	23	#endif
	24
	25	static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
	26	{
	27	struct eth_mac_regs *mac_p = bus->priv;
	28	ulong start;
	29	u16 miiaddr;
	30	int timeout = CONFIG_MDIO_TIMEOUT;
	31
	32	miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) \|
	33	((reg << MIIREGSHIFT) & MII_REGMSK);
	34
	35	writel(miiaddr \| MII_CLKRANGE_150_250M \| MII_BUSY, &mac_p->miiaddr);
	36
	37	start = get_timer(0);
	38	while (get_timer(start) < timeout) {
	39	if (!(readl(&mac_p->miiaddr) & MII_BUSY))
	40	return readl(&mac_p->miidata);
	41	udelay(10);
	42	};
	43
64dcd25f	44	return -ETIMEDOUT;
92a190aa AB	45	}
	46
	47	static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
	48	u16 val)
	49	{
	50	struct eth_mac_regs *mac_p = bus->priv;
	51	ulong start;
	52	u16 miiaddr;
64dcd25f	53	int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT;
92a190aa AB	54
	55	writel(val, &mac_p->miidata);
	56	miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) \|
	57	((reg << MIIREGSHIFT) & MII_REGMSK) \| MII_WRITE;
	58
	59	writel(miiaddr \| MII_CLKRANGE_150_250M \| MII_BUSY, &mac_p->miiaddr);
	60
	61	start = get_timer(0);
	62	while (get_timer(start) < timeout) {
	63	if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
	64	ret = 0;
	65	break;
	66	}
	67	udelay(10);
	68	};
	69
	70	return ret;
	71	}
	72
64dcd25f	73	static int dw_mdio_init(const char name, struct eth_mac_regs mac_regs_p)
92a190aa AB	74	{
	75	struct mii_dev *bus = mdio_alloc();
	76
	77	if (!bus) {
	78	printf("Failed to allocate MDIO bus\n");
64dcd25f	79	return -ENOMEM;
92a190aa AB	80	}
	81
	82	bus->read = dw_mdio_read;
	83	bus->write = dw_mdio_write;
64dcd25f	84	snprintf(bus->name, sizeof(bus->name), name);
92a190aa AB	85
	86	bus->priv = (void *)mac_regs_p;
	87
	88	return mdio_register(bus);
	89	}
13edd170	90
64dcd25f	91	static void tx_descs_init(struct dw_eth_dev *priv)
5b1b1883	92	{
5b1b1883 VK	93	struct eth_dma_regs *dma_p = priv->dma_regs_p;
	94	struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0];
	95	char *txbuffs = &priv->txbuffs[0];
	96	struct dmamacdescr *desc_p;
	97	u32 idx;
	98
	99	for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
	100	desc_p = &desc_table_p[idx];
	101	desc_p->dmamac_addr = &txbuffs[idx * CONFIG_ETH_BUFSIZE];
	102	desc_p->dmamac_next = &desc_table_p[idx + 1];
	103
	104	#if defined(CONFIG_DW_ALTDESCRIPTOR)
	105	desc_p->txrx_status &= ~(DESC_TXSTS_TXINT \| DESC_TXSTS_TXLAST \|
	106	DESC_TXSTS_TXFIRST \| DESC_TXSTS_TXCRCDIS \| \
	107	DESC_TXSTS_TXCHECKINSCTRL \| \
	108	DESC_TXSTS_TXRINGEND \| DESC_TXSTS_TXPADDIS);
	109
	110	desc_p->txrx_status \|= DESC_TXSTS_TXCHAIN;
	111	desc_p->dmamac_cntl = 0;
	112	desc_p->txrx_status &= ~(DESC_TXSTS_MSK \| DESC_TXSTS_OWNBYDMA);
	113	#else
	114	desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN;
	115	desc_p->txrx_status = 0;
	116	#endif
	117	}
	118
	119	/* Correcting the last pointer of the chain */
	120	desc_p->dmamac_next = &desc_table_p[0];
	121
50b0df81 AB	122	/* Flush all Tx buffer descriptors at once */
	123	flush_dcache_range((unsigned int)priv->tx_mac_descrtable,
	124	(unsigned int)priv->tx_mac_descrtable +
	125	sizeof(priv->tx_mac_descrtable));
	126
5b1b1883	127	writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
74cb708d	128	priv->tx_currdescnum = 0;
5b1b1883 VK	129	}
5b1b1883 VK	130
64dcd25f	131	static void rx_descs_init(struct dw_eth_dev *priv)
5b1b1883	132	{
5b1b1883 VK	133	struct eth_dma_regs *dma_p = priv->dma_regs_p;
	134	struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0];
	135	char *rxbuffs = &priv->rxbuffs[0];
	136	struct dmamacdescr *desc_p;
	137	u32 idx;
	138
50b0df81 AB	139	/* Before passing buffers to GMAC we need to make sure zeros
	140	* written there right after "priv" structure allocation were
	141	* flushed into RAM.
	142	* Otherwise there's a chance to get some of them flushed in RAM when
	143	* GMAC is already pushing data to RAM via DMA. This way incoming from
	144	* GMAC data will be corrupted. */
	145	flush_dcache_range((unsigned int)rxbuffs, (unsigned int)rxbuffs +
	146	RX_TOTAL_BUFSIZE);
	147
5b1b1883 VK	148	for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
	149	desc_p = &desc_table_p[idx];
	150	desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE];
	151	desc_p->dmamac_next = &desc_table_p[idx + 1];
	152
	153	desc_p->dmamac_cntl =
	154	(MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) \| \
	155	DESC_RXCTRL_RXCHAIN;
	156
	157	desc_p->txrx_status = DESC_RXSTS_OWNBYDMA;
	158	}
	159
	160	/* Correcting the last pointer of the chain */
	161	desc_p->dmamac_next = &desc_table_p[0];
	162
50b0df81 AB	163	/* Flush all Rx buffer descriptors at once */
	164	flush_dcache_range((unsigned int)priv->rx_mac_descrtable,
	165	(unsigned int)priv->rx_mac_descrtable +
	166	sizeof(priv->rx_mac_descrtable));
	167
5b1b1883	168	writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
74cb708d	169	priv->rx_currdescnum = 0;
5b1b1883 VK	170	}
5b1b1883 VK	171
64dcd25f	172	static int _dw_write_hwaddr(struct dw_eth_dev priv, u8 mac_id)
5b1b1883	173	{
92a190aa AB	174	struct eth_mac_regs *mac_p = priv->mac_regs_p;
92a190aa AB	175	u32 macid_lo, macid_hi;
92a190aa AB	176
	177	macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
	178	(mac_id[3] << 24);
	179	macid_hi = mac_id[4] + (mac_id[5] << 8);
	180
	181	writel(macid_hi, &mac_p->macaddr0hi);
	182	writel(macid_lo, &mac_p->macaddr0lo);
	183
	184	return 0;
5b1b1883 VK	185	}
5b1b1883 VK	186
92a190aa AB	187	static void dw_adjust_link(struct eth_mac_regs *mac_p,
92a190aa AB	188	struct phy_device *phydev)
5b1b1883	189	{
92a190aa	190	u32 conf = readl(&mac_p->conf) \| FRAMEBURSTENABLE \| DISABLERXOWN;
5b1b1883	191
92a190aa AB	192	if (!phydev->link) {
	193	printf("%s: No link.\n", phydev->dev->name);
	194	return;
	195	}
5b1b1883	196
92a190aa AB	197	if (phydev->speed != 1000)
92a190aa AB	198	conf \|= MII_PORTSELECT;
7091915a	199
92a190aa AB	200	if (phydev->speed == 100)
92a190aa AB	201	conf \|= FES_100;
5b1b1883	202
92a190aa AB	203	if (phydev->duplex)
92a190aa AB	204	conf \|= FULLDPLXMODE;
cafabe19	205
92a190aa	206	writel(conf, &mac_p->conf);
5b1b1883	207
92a190aa AB	208	printf("Speed: %d, %s duplex%s\n", phydev->speed,
	209	(phydev->duplex) ? "full" : "half",
	210	(phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
5b1b1883 VK	211	}
5b1b1883 VK	212
64dcd25f	213	static void _dw_eth_halt(struct dw_eth_dev *priv)
5b1b1883	214	{
5b1b1883	215	struct eth_mac_regs *mac_p = priv->mac_regs_p;
92a190aa	216	struct eth_dma_regs *dma_p = priv->dma_regs_p;
5b1b1883	217
92a190aa AB	218	writel(readl(&mac_p->conf) & ~(RXENABLE \| TXENABLE), &mac_p->conf);
92a190aa AB	219	writel(readl(&dma_p->opmode) & ~(RXSTART \| TXSTART), &dma_p->opmode);
5b1b1883	220
92a190aa	221	phy_shutdown(priv->phydev);
5b1b1883 VK	222	}
5b1b1883 VK	223
64dcd25f	224	static int _dw_eth_init(struct dw_eth_dev priv, u8 enetaddr)
5b1b1883	225	{
5b1b1883 VK	226	struct eth_mac_regs *mac_p = priv->mac_regs_p;
5b1b1883 VK	227	struct eth_dma_regs *dma_p = priv->dma_regs_p;
92a190aa	228	unsigned int start;
64dcd25f	229	int ret;
5b1b1883	230
92a190aa	231	writel(readl(&dma_p->busmode) \| DMAMAC_SRST, &dma_p->busmode);
13edd170	232
92a190aa AB	233	start = get_timer(0);
92a190aa AB	234	while (readl(&dma_p->busmode) & DMAMAC_SRST) {
875143f3 AB	235	if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) {
875143f3 AB	236	printf("DMA reset timeout\n");
64dcd25f	237	return -ETIMEDOUT;
875143f3	238	}
ef76025a	239
92a190aa AB	240	mdelay(100);
92a190aa AB	241	};
5b1b1883	242
92a190aa AB	243	/* Soft reset above clears HW address registers.
92a190aa AB	244	* So we have to set it here once again */
64dcd25f	245	_dw_write_hwaddr(priv, enetaddr);
c7f6dbe7	246
64dcd25f SG	247	rx_descs_init(priv);
64dcd25f SG	248	tx_descs_init(priv);
5b1b1883	249
49692c5f	250	writel(FIXEDBURST \| PRIORXTX_41 \| DMA_PBL, &dma_p->busmode);
5b1b1883	251
d2279221	252	#ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE
92a190aa AB	253	writel(readl(&dma_p->opmode) \| FLUSHTXFIFO \| STOREFORWARD,
92a190aa AB	254	&dma_p->opmode);
d2279221 SZ	255	#else
	256	writel(readl(&dma_p->opmode) \| FLUSHTXFIFO,
	257	&dma_p->opmode);
	258	#endif
5b1b1883	259
92a190aa	260	writel(readl(&dma_p->opmode) \| RXSTART \| TXSTART, &dma_p->opmode);
9afc1af0	261
2ddaf13b SZ	262	#ifdef CONFIG_DW_AXI_BURST_LEN
	263	writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus);
	264	#endif
	265
92a190aa	266	/* Start up the PHY */
64dcd25f SG	267	ret = phy_startup(priv->phydev);
64dcd25f SG	268	if (ret) {
92a190aa AB	269	printf("Could not initialize PHY %s\n",
92a190aa AB	270	priv->phydev->dev->name);
64dcd25f	271	return ret;
9afc1af0 VK	272	}
9afc1af0 VK	273
92a190aa	274	dw_adjust_link(mac_p, priv->phydev);
5b1b1883	275
92a190aa	276	if (!priv->phydev->link)
64dcd25f	277	return -EIO;
5b1b1883	278
aa51005c	279	writel(readl(&mac_p->conf) \| RXENABLE \| TXENABLE, &mac_p->conf);
5b1b1883 VK	280
	281	return 0;
	282	}
	283
64dcd25f	284	static int _dw_eth_send(struct dw_eth_dev priv, void packet, int length)
5b1b1883	285	{
5b1b1883 VK	286	struct eth_dma_regs *dma_p = priv->dma_regs_p;
	287	u32 desc_num = priv->tx_currdescnum;
	288	struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
96cec17d MV	289	uint32_t desc_start = (uint32_t)desc_p;
	290	uint32_t desc_end = desc_start +
	291	roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
	292	uint32_t data_start = (uint32_t)desc_p->dmamac_addr;
	293	uint32_t data_end = data_start +
	294	roundup(length, ARCH_DMA_MINALIGN);
964ea7c1 IC	295	/*
	296	* Strictly we only need to invalidate the "txrx_status" field
	297	* for the following check, but on some platforms we cannot
96cec17d MV	298	* invalidate only 4 bytes, so we flush the entire descriptor,
	299	* which is 16 bytes in total. This is safe because the
	300	* individual descriptors in the array are each aligned to
	301	* ARCH_DMA_MINALIGN and padded appropriately.
964ea7c1	302	*/
96cec17d	303	invalidate_dcache_range(desc_start, desc_end);
50b0df81	304
5b1b1883 VK	305	/* Check if the descriptor is owned by CPU */
	306	if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
	307	printf("CPU not owner of tx frame\n");
64dcd25f	308	return -EPERM;
5b1b1883 VK	309	}
5b1b1883 VK	310
96cec17d	311	memcpy(desc_p->dmamac_addr, packet, length);
5b1b1883	312
50b0df81	313	/* Flush data to be sent */
96cec17d	314	flush_dcache_range(data_start, data_end);
50b0df81	315
5b1b1883 VK	316	#if defined(CONFIG_DW_ALTDESCRIPTOR)
	317	desc_p->txrx_status \|= DESC_TXSTS_TXFIRST \| DESC_TXSTS_TXLAST;
	318	desc_p->dmamac_cntl \|= (length << DESC_TXCTRL_SIZE1SHFT) & \
	319	DESC_TXCTRL_SIZE1MASK;
	320
	321	desc_p->txrx_status &= ~(DESC_TXSTS_MSK);
	322	desc_p->txrx_status \|= DESC_TXSTS_OWNBYDMA;
	323	#else
	324	desc_p->dmamac_cntl \|= ((length << DESC_TXCTRL_SIZE1SHFT) & \
	325	DESC_TXCTRL_SIZE1MASK) \| DESC_TXCTRL_TXLAST \| \
	326	DESC_TXCTRL_TXFIRST;
	327
	328	desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
	329	#endif
	330
50b0df81	331	/* Flush modified buffer descriptor */
96cec17d	332	flush_dcache_range(desc_start, desc_end);
50b0df81	333
5b1b1883 VK	334	/* Test the wrap-around condition. */
	335	if (++desc_num >= CONFIG_TX_DESCR_NUM)
	336	desc_num = 0;
	337
	338	priv->tx_currdescnum = desc_num;
	339
	340	/* Start the transmission */
	341	writel(POLL_DATA, &dma_p->txpolldemand);
	342
	343	return 0;
	344	}
	345
64dcd25f	346	static int _dw_eth_recv(struct dw_eth_dev *priv)
5b1b1883	347	{
50b0df81	348	u32 status, desc_num = priv->rx_currdescnum;
5b1b1883	349	struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
5b1b1883	350	int length = 0;
96cec17d MV	351	uint32_t desc_start = (uint32_t)desc_p;
	352	uint32_t desc_end = desc_start +
	353	roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
	354	uint32_t data_start = (uint32_t)desc_p->dmamac_addr;
	355	uint32_t data_end;
5b1b1883	356
50b0df81	357	/* Invalidate entire buffer descriptor */
96cec17d	358	invalidate_dcache_range(desc_start, desc_end);
50b0df81 AB	359
	360	status = desc_p->txrx_status;
	361
5b1b1883 VK	362	/* Check if the owner is the CPU */
	363	if (!(status & DESC_RXSTS_OWNBYDMA)) {
	364
	365	length = (status & DESC_RXSTS_FRMLENMSK) >> \
	366	DESC_RXSTS_FRMLENSHFT;
	367
50b0df81	368	/* Invalidate received data */
96cec17d MV	369	data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
96cec17d MV	370	invalidate_dcache_range(data_start, data_end);
50b0df81	371
1fd92db8	372	net_process_received_packet(desc_p->dmamac_addr, length);
5b1b1883 VK	373
	374	/*
	375	* Make the current descriptor valid again and go to
	376	* the next one
	377	*/
	378	desc_p->txrx_status \|= DESC_RXSTS_OWNBYDMA;
	379
50b0df81	380	/* Flush only status field - others weren't changed */
96cec17d	381	flush_dcache_range(desc_start, desc_end);
50b0df81	382
5b1b1883 VK	383	/* Test the wrap-around condition. */
	384	if (++desc_num >= CONFIG_RX_DESCR_NUM)
	385	desc_num = 0;
	386	}
	387
	388	priv->rx_currdescnum = desc_num;
	389
	390	return length;
	391	}
	392
64dcd25f	393	static int dw_phy_init(struct dw_eth_dev priv, void dev)
5b1b1883	394	{
92a190aa AB	395	struct phy_device *phydev;
92a190aa AB	396	int mask = 0xffffffff;
cafabe19	397
92a190aa AB	398	#ifdef CONFIG_PHY_ADDR
92a190aa AB	399	mask = 1 << CONFIG_PHY_ADDR;
5b1b1883 VK	400	#endif
5b1b1883 VK	401
92a190aa AB	402	phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
92a190aa AB	403	if (!phydev)
64dcd25f	404	return -ENODEV;
5b1b1883	405
15e82e53 IC	406	phy_connect_dev(phydev, dev);
15e82e53 IC	407
92a190aa AB	408	phydev->supported &= PHY_GBIT_FEATURES;
92a190aa AB	409	phydev->advertising = phydev->supported;
5b1b1883	410
92a190aa AB	411	priv->phydev = phydev;
92a190aa AB	412	phy_config(phydev);
ef76025a	413
64dcd25f SG	414	return 0;
	415	}
	416
	417	static int dw_eth_init(struct eth_device dev, bd_t bis)
	418	{
	419	return _dw_eth_init(dev->priv, dev->enetaddr);
	420	}
	421
	422	static int dw_eth_send(struct eth_device dev, void packet, int length)
	423	{
	424	return _dw_eth_send(dev->priv, packet, length);
	425	}
	426
	427	static int dw_eth_recv(struct eth_device *dev)
	428	{
	429	return _dw_eth_recv(dev->priv);
	430	}
	431
	432	static void dw_eth_halt(struct eth_device *dev)
	433	{
	434	return _dw_eth_halt(dev->priv);
	435	}
	436
	437	static int dw_write_hwaddr(struct eth_device *dev)
	438	{
	439	return _dw_write_hwaddr(dev->priv, dev->enetaddr);
5b1b1883	440	}
5b1b1883	441
92a190aa	442	int designware_initialize(ulong base_addr, u32 interface)
5b1b1883 VK	443	{
	444	struct eth_device *dev;
	445	struct dw_eth_dev *priv;
	446
	447	dev = (struct eth_device *) malloc(sizeof(struct eth_device));
	448	if (!dev)
	449	return -ENOMEM;
	450
	451	/*
	452	* Since the priv structure contains the descriptors which need a strict
	453	* buswidth alignment, memalign is used to allocate memory
	454	*/
1c848a25 IC	455	priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN,
1c848a25 IC	456	sizeof(struct dw_eth_dev));
5b1b1883 VK	457	if (!priv) {
	458	free(dev);
	459	return -ENOMEM;
	460	}
	461
	462	memset(dev, 0, sizeof(struct eth_device));
	463	memset(priv, 0, sizeof(struct dw_eth_dev));
	464
92a190aa	465	sprintf(dev->name, "dwmac.%lx", base_addr);
5b1b1883 VK	466	dev->iobase = (int)base_addr;
	467	dev->priv = priv;
	468
5b1b1883 VK	469	priv->dev = dev;
	470	priv->mac_regs_p = (struct eth_mac_regs *)base_addr;
	471	priv->dma_regs_p = (struct eth_dma_regs *)(base_addr +
	472	DW_DMA_BASE_OFFSET);
5b1b1883	473
5b1b1883 VK	474	dev->init = dw_eth_init;
	475	dev->send = dw_eth_send;
	476	dev->recv = dw_eth_recv;
	477	dev->halt = dw_eth_halt;
	478	dev->write_hwaddr = dw_write_hwaddr;
	479
	480	eth_register(dev);
	481
92a190aa AB	482	priv->interface = interface;
	483
	484	dw_mdio_init(dev->name, priv->mac_regs_p);
	485	priv->bus = miiphy_get_dev_by_name(dev->name);
	486
64dcd25f	487	return dw_phy_init(priv, dev);
5b1b1883	488	}