[u-boot.git] / include / configs / T102xRDB.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2014 Freescale Semiconductor, Inc.
 * Copyright 2020-2021 NXP
 */

/*
 * T1024/T1023 RDB board configuration file
 */

#ifndef __T1024RDB_H
#define __T1024RDB_H

#include <linux/stringify.h>

/* High Level Configuration Options */

#define CFG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS

#ifdef CONFIG_RAMBOOT_PBL
#define RESET_VECTOR_OFFSET		0x27FFC
#define BOOT_PAGE_OFFSET		0x27000

#ifdef CONFIG_MTD_RAW_NAND
#define CFG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
#define CFG_SYS_NAND_U_BOOT_DST	0x30000000
#define CFG_SYS_NAND_U_BOOT_START	0x30000000
#endif

#ifdef CONFIG_SPIFLASH
#define CONFIG_RESET_VECTOR_ADDRESS		0x30000FFC
#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE	(768 << 10)
#define CFG_SYS_SPI_FLASH_U_BOOT_DST		(0x30000000)
#define CFG_SYS_SPI_FLASH_U_BOOT_START	(0x30000000)
#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS	(256 << 10)
#endif

#ifdef CONFIG_SDCARD
#define CONFIG_RESET_VECTOR_ADDRESS	0x30000FFC
#define CFG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
#define CFG_SYS_MMC_U_BOOT_DST	(0x30000000)
#define CFG_SYS_MMC_U_BOOT_START	(0x30000000)
#define CFG_SYS_MMC_U_BOOT_OFFS	(260 << 10)
#endif

#endif /* CONFIG_RAMBOOT_PBL */

#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
#endif

/*
 * for slave u-boot IMAGE instored in master memory space,
 * PHYS must be aligned based on the SIZE
 */
#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
#define CFG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
#ifdef CONFIG_PHYS_64BIT
#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
#else
#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
#endif
/*
 * for slave UCODE and ENV instored in master memory space,
 * PHYS must be aligned based on the SIZE
 */
#ifdef CONFIG_PHYS_64BIT
#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS	 0x3ffe00000ull
#else
#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0xffe00000
#endif
#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE	0x40000 /* 256K */
/* slave core release by master*/
#define CFG_SRIO_PCIE_BOOT_BRR_OFFSET	0xe00e4
#define CFG_SRIO_PCIE_BOOT_RELEASE_MASK	0x00000001 /* release core 0 */

/* PCIe Boot - Slave */
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
		(0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
/* Set 1M boot space for PCIe boot */
#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS	\
		(0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#endif

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CFG_SYS_INIT_L2CSR0		L2CSR0_L2E
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
#endif

/*
 *  Config the L3 Cache as L3 SRAM
 */
#define CFG_SYS_INIT_L3_ADDR		0xFFFC0000
#define SPL_ENV_ADDR			(CONFIG_SPL_GD_ADDR + 4 * 1024)

#ifdef CONFIG_PHYS_64BIT
#define CFG_SYS_DCSRBAR		0xf0000000
#define CFG_SYS_DCSRBAR_PHYS		0xf00000000ull
#endif

/*
 * DDR Setup
 */
#define CONFIG_VERY_BIG_RAM
#define CFG_SYS_DDR_SDRAM_BASE	0x00000000
#define CFG_SYS_SDRAM_BASE		CFG_SYS_DDR_SDRAM_BASE
#if defined(CONFIG_TARGET_T1024RDB)
#define SPD_EEPROM_ADDRESS	0x51
#define CFG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
#elif defined(CONFIG_TARGET_T1023RDB)
#define CFG_SYS_SDRAM_SIZE   2048
#endif

/*
 * IFC Definitions
 */
#define CFG_SYS_FLASH_BASE	0xe8000000
#ifdef CONFIG_PHYS_64BIT
#define CFG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CFG_SYS_FLASH_BASE)
#else
#define CFG_SYS_FLASH_BASE_PHYS	CFG_SYS_FLASH_BASE
#endif

#define CFG_SYS_NOR0_CSPR_EXT	(0xf)
#define CFG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
				CSPR_PORT_SIZE_16 | \
				CSPR_MSEL_NOR | \
				CSPR_V)
#define CFG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)

/* NOR Flash Timing Params */
#if defined(CONFIG_TARGET_T1024RDB)
#define CFG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
#elif defined(CONFIG_TARGET_T1023RDB)
#define CFG_SYS_NOR_CSOR    (CSOR_NOR_ADM_SHIFT(0) | \
				CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
#endif
#define CFG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
				FTIM0_NOR_TEADC(0x5) | \
				FTIM0_NOR_TEAHC(0x5))
#define CFG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
				FTIM1_NOR_TRAD_NOR(0x1A) |\
				FTIM1_NOR_TSEQRAD_NOR(0x13))
#define CFG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
				FTIM2_NOR_TCH(0x4) | \
				FTIM2_NOR_TWPH(0x0E) | \
				FTIM2_NOR_TWP(0x1c))
#define CFG_SYS_NOR_FTIM3	0x0

#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */

#define CFG_SYS_FLASH_BANKS_LIST	{CFG_SYS_FLASH_BASE_PHYS}

#ifdef CONFIG_TARGET_T1024RDB
/* CPLD on IFC */
#define CFG_SYS_CPLD_BASE		0xffdf0000
#define CFG_SYS_CPLD_BASE_PHYS	(0xf00000000ull | CFG_SYS_CPLD_BASE)
#define CFG_SYS_CSPR2_EXT		(0xf)
#define CFG_SYS_CSPR2		(CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE) \
						| CSPR_PORT_SIZE_8 \
						| CSPR_MSEL_GPCM \
						| CSPR_V)
#define CFG_SYS_AMASK2		IFC_AMASK(64*1024)
#define CFG_SYS_CSOR2		0x0

/* CPLD Timing parameters for IFC CS2 */
#define CFG_SYS_CS2_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
						FTIM0_GPCM_TEADC(0x0e) | \
						FTIM0_GPCM_TEAHC(0x0e))
#define CFG_SYS_CS2_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \
						FTIM1_GPCM_TRAD(0x1f))
#define CFG_SYS_CS2_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
						FTIM2_GPCM_TCH(0x8) | \
						FTIM2_GPCM_TWP(0x1f))
#define CFG_SYS_CS2_FTIM3		0x0
#endif

/* NAND Flash on IFC */
#define CFG_SYS_NAND_BASE		0xff800000
#ifdef CONFIG_PHYS_64BIT
#define CFG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CFG_SYS_NAND_BASE)
#else
#define CFG_SYS_NAND_BASE_PHYS	CFG_SYS_NAND_BASE
#endif
#define CFG_SYS_NAND_CSPR_EXT	(0xf)
#define CFG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
				| CSPR_V)
#define CFG_SYS_NAND_AMASK	IFC_AMASK(64*1024)

#if defined(CONFIG_TARGET_T1024RDB)
#define CFG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
				| CSOR_NAND_RAL_3	/* RAL = 3Byes */ \
				| CSOR_NAND_PGS_4K	/* Page Size = 4K */ \
				| CSOR_NAND_SPRZ_224	/* Spare size = 224 */ \
				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
#elif defined(CONFIG_TARGET_T1023RDB)
#define CFG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */ \
				| CSOR_NAND_RAL_3	/* RAL 3Bytes */ \
				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
				| CSOR_NAND_SPRZ_128	/* Spare size = 128 */ \
				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
#endif

/* ONFI NAND Flash mode0 Timing Params */
#define CFG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
					FTIM0_NAND_TWP(0x18)   | \
					FTIM0_NAND_TWCHT(0x07) | \
					FTIM0_NAND_TWH(0x0a))
#define CFG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
					FTIM1_NAND_TWBE(0x39)  | \
					FTIM1_NAND_TRR(0x0e)   | \
					FTIM1_NAND_TRP(0x18))
#define CFG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
					FTIM2_NAND_TREH(0x0a) | \
					FTIM2_NAND_TWHRE(0x1e))
#define CFG_SYS_NAND_FTIM3		0x0

#define CFG_SYS_NAND_BASE_LIST	{ CFG_SYS_NAND_BASE }

#if defined(CONFIG_MTD_RAW_NAND)
#define CFG_SYS_CSPR0_EXT		CFG_SYS_NAND_CSPR_EXT
#define CFG_SYS_CSPR0		CFG_SYS_NAND_CSPR
#define CFG_SYS_AMASK0		CFG_SYS_NAND_AMASK
#define CFG_SYS_CSOR0		CFG_SYS_NAND_CSOR
#define CFG_SYS_CS0_FTIM0		CFG_SYS_NAND_FTIM0
#define CFG_SYS_CS0_FTIM1		CFG_SYS_NAND_FTIM1
#define CFG_SYS_CS0_FTIM2		CFG_SYS_NAND_FTIM2
#define CFG_SYS_CS0_FTIM3		CFG_SYS_NAND_FTIM3
#define CFG_SYS_CSPR1_EXT		CFG_SYS_NOR0_CSPR_EXT
#define CFG_SYS_CSPR1		CFG_SYS_NOR0_CSPR
#define CFG_SYS_AMASK1		CFG_SYS_NOR_AMASK
#define CFG_SYS_CSOR1		CFG_SYS_NOR_CSOR
#define CFG_SYS_CS1_FTIM0		CFG_SYS_NOR_FTIM0
#define CFG_SYS_CS1_FTIM1		CFG_SYS_NOR_FTIM1
#define CFG_SYS_CS1_FTIM2		CFG_SYS_NOR_FTIM2
#define CFG_SYS_CS1_FTIM3		CFG_SYS_NOR_FTIM3
#else
#define CFG_SYS_CSPR0_EXT		CFG_SYS_NOR0_CSPR_EXT
#define CFG_SYS_CSPR0		CFG_SYS_NOR0_CSPR
#define CFG_SYS_AMASK0		CFG_SYS_NOR_AMASK
#define CFG_SYS_CSOR0		CFG_SYS_NOR_CSOR
#define CFG_SYS_CS0_FTIM0		CFG_SYS_NOR_FTIM0
#define CFG_SYS_CS0_FTIM1		CFG_SYS_NOR_FTIM1
#define CFG_SYS_CS0_FTIM2		CFG_SYS_NOR_FTIM2
#define CFG_SYS_CS0_FTIM3		CFG_SYS_NOR_FTIM3
#define CFG_SYS_CSPR1_EXT		CFG_SYS_NAND_CSPR_EXT
#define CFG_SYS_CSPR1		CFG_SYS_NAND_CSPR
#define CFG_SYS_AMASK1		CFG_SYS_NAND_AMASK
#define CFG_SYS_CSOR1		CFG_SYS_NAND_CSOR
#define CFG_SYS_CS1_FTIM0		CFG_SYS_NAND_FTIM0
#define CFG_SYS_CS1_FTIM1		CFG_SYS_NAND_FTIM1
#define CFG_SYS_CS1_FTIM2		CFG_SYS_NAND_FTIM2
#define CFG_SYS_CS1_FTIM3		CFG_SYS_NAND_FTIM3
#endif

/* define to use L1 as initial stack */
#define CONFIG_L1_INIT_RAM
#define CFG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
#ifdef CONFIG_PHYS_64BIT
#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
/* The assembler doesn't like typecast */
#define CFG_SYS_INIT_RAM_ADDR_PHYS \
	((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
	  CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
#else
#define CFG_SYS_INIT_RAM_ADDR_PHYS	0xfe03c000 /* Initial L1 address */
#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR_PHYS
#endif
#define CFG_SYS_INIT_RAM_SIZE		0x00004000

#define CFG_SYS_INIT_SP_OFFSET	(CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

/* Serial Port */
#define CFG_SYS_NS16550_CLK		(get_bus_freq(0)/2)

#define CFG_SYS_BAUDRATE_TABLE	\
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

#define CFG_SYS_NS16550_COM1	(CFG_SYS_CCSRBAR+0x11C500)
#define CFG_SYS_NS16550_COM2	(CFG_SYS_CCSRBAR+0x11C600)
#define CFG_SYS_NS16550_COM3	(CFG_SYS_CCSRBAR+0x11D500)
#define CFG_SYS_NS16550_COM4	(CFG_SYS_CCSRBAR+0x11D600)

/* I2C */

#define I2C_PCA6408_BUS_NUM		1
#define I2C_PCA6408_ADDR		0x20

/* I2C bus multiplexer */
#define I2C_MUX_CH_DEFAULT	0x8

/*
 * RTC configuration
 */
#define RTC
#define CONFIG_RTC_DS1337	1
#define CFG_SYS_I2C_RTC_ADDR	0x68

/*
 * eSPI - Enhanced SPI
 */

/*
 * General PCIe
 * Memory space is mapped 1-1, but I/O space must start from 0.
 */

#ifdef CONFIG_PCI
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#ifdef CONFIG_PCIE1
#define	CFG_SYS_PCIE1_MEM_VIRT	0x80000000
#define	CFG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
#define CFG_SYS_PCIE1_IO_VIRT	0xf8000000
#define CFG_SYS_PCIE1_IO_PHYS	0xff8000000ull
#endif

/* controller 2, Slot 2, tgtid 2, Base address 201000 */
#ifdef CONFIG_PCIE2
#define CFG_SYS_PCIE2_MEM_VIRT	0x90000000
#define CFG_SYS_PCIE2_MEM_PHYS	0xc10000000ull
#define CFG_SYS_PCIE2_IO_VIRT	0xf8010000
#define CFG_SYS_PCIE2_IO_PHYS	0xff8010000ull
#endif

/* controller 3, Slot 1, tgtid 1, Base address 202000 */
#ifdef CONFIG_PCIE3
#define CFG_SYS_PCIE3_MEM_VIRT	0xa0000000
#define CFG_SYS_PCIE3_MEM_PHYS	0xc20000000ull
#endif
#endif	/* CONFIG_PCI */

/*
 * USB
 */

/*
 * SDHC
 */
#ifdef CONFIG_MMC
#define CFG_SYS_FSL_ESDHC_ADDR	CFG_SYS_MPC85xx_ESDHC_ADDR
#endif

/* Qman/Bman */
#ifndef CONFIG_NOBQFMAN
#define CFG_SYS_BMAN_NUM_PORTALS	10
#define CFG_SYS_BMAN_MEM_BASE	0xf4000000
#ifdef CONFIG_PHYS_64BIT
#define CFG_SYS_BMAN_MEM_PHYS	0xff4000000ull
#else
#define CFG_SYS_BMAN_MEM_PHYS	CFG_SYS_BMAN_MEM_BASE
#endif
#define CFG_SYS_BMAN_MEM_SIZE	0x02000000
#define CFG_SYS_BMAN_SP_CENA_SIZE    0x4000
#define CFG_SYS_BMAN_SP_CINH_SIZE    0x1000
#define CFG_SYS_BMAN_CENA_BASE       CFG_SYS_BMAN_MEM_BASE
#define CFG_SYS_BMAN_CENA_SIZE       (CFG_SYS_BMAN_MEM_SIZE >> 1)
#define CFG_SYS_BMAN_CINH_BASE       (CFG_SYS_BMAN_MEM_BASE + \
					CFG_SYS_BMAN_CENA_SIZE)
#define CFG_SYS_BMAN_CINH_SIZE       (CFG_SYS_BMAN_MEM_SIZE >> 1)
#define CFG_SYS_BMAN_SWP_ISDR_REG	0xE08
#define CFG_SYS_QMAN_NUM_PORTALS	10
#define CFG_SYS_QMAN_MEM_BASE	0xf6000000
#ifdef CONFIG_PHYS_64BIT
#define CFG_SYS_QMAN_MEM_PHYS	0xff6000000ull
#else
#define CFG_SYS_QMAN_MEM_PHYS	CFG_SYS_QMAN_MEM_BASE
#endif
#define CFG_SYS_QMAN_MEM_SIZE	0x02000000
#define CFG_SYS_QMAN_SP_CINH_SIZE    0x1000
#define CFG_SYS_QMAN_CENA_SIZE       (CFG_SYS_QMAN_MEM_SIZE >> 1)
#define CFG_SYS_QMAN_CINH_BASE       (CFG_SYS_QMAN_MEM_BASE + \
					CFG_SYS_QMAN_CENA_SIZE)
#define CFG_SYS_QMAN_CINH_SIZE       (CFG_SYS_QMAN_MEM_SIZE >> 1)
#define CFG_SYS_QMAN_SWP_ISDR_REG	0xE08

#endif /* CONFIG_NOBQFMAN */

#ifdef CONFIG_SYS_DPAA_FMAN
#if defined(CONFIG_TARGET_T1024RDB)
#define RGMII_PHY1_ADDR		0x2
#define RGMII_PHY2_ADDR		0x6
#define SGMII_AQR_PHY_ADDR	0x2
#define FM1_10GEC1_PHY_ADDR	0x1
#elif defined(CONFIG_TARGET_T1023RDB)
#define RGMII_PHY1_ADDR		0x1
#define SGMII_RTK_PHY_ADDR	0x3
#define SGMII_AQR_PHY_ADDR	0x2
#endif
#endif

/*
 * Dynamic MTD Partition support with mtdparts
 */

/*
 * Miscellaneous configurable options
 */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 64 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/

/*
 * Environment Configuration
 */
#define CONFIG_ROOTPATH		"/opt/nfsroot"
#define CONFIG_UBOOTPATH	u-boot.bin /* U-Boot image on TFTP server */
#define __USB_PHY_TYPE		utmi

#ifdef CONFIG_ARCH_T1024
#define ARCH_EXTRA_ENV_SETTINGS \
	"bank_intlv=cs0_cs1\0"			\
	"ramdiskfile=t1024rdb/ramdisk.uboot\0"	\
	"fdtfile=t1024rdb/t1024rdb.dtb\0"
#else
#define ARCH_EXTRA_ENV_SETTINGS \
	"bank_intlv=null\0"			\
	"ramdiskfile=t1023rdb/ramdisk.uboot\0"	\
	"fdtfile=t1023rdb/t1023rdb.dtb\0"
#endif

#define	CONFIG_EXTRA_ENV_SETTINGS				\
	ARCH_EXTRA_ENV_SETTINGS					\
	"hwconfig=fsl_ddr:ctlr_intlv=cacheline,"		\
	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"  \
	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
	"ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0"	\
	"bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
	"netdev=eth0\0"						\
	"tftpflash=tftpboot $loadaddr $uboot && "		\
	"protect off $ubootaddr +$filesize && "			\
	"erase $ubootaddr +$filesize && "			\
	"cp.b $loadaddr $ubootaddr $filesize && "		\
	"protect on $ubootaddr +$filesize && "			\
	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
	"consoledev=ttyS0\0"					\
	"ramdiskaddr=2000000\0"					\
	"fdtaddr=1e00000\0"					\
	"bdev=sda3\0"

#include <asm/fsl_secure_boot.h>

#endif	/* __T1024RDB_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
48c6f328 SL	2	/*
48c6f328 SL	3	* Copyright 2014 Freescale Semiconductor, Inc.
a97a071d	4	* Copyright 2020-2021 NXP
48c6f328 SL	5	*/
	6
	7	/*
	8	* T1024/T1023 RDB board configuration file
	9	*/
	10
	11	#ifndef __T1024RDB_H
	12	#define __T1024RDB_H
	13
1af3c7f4 SG	14	#include <linux/stringify.h>
1af3c7f4 SG	15
48c6f328	16	/* High Level Configuration Options */
48c6f328	17
cdc5ed8f	18	#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
48c6f328	19
48c6f328	20	#ifdef CONFIG_RAMBOOT_PBL
48c6f328 SL	21	#define RESET_VECTOR_OFFSET 0x27FFC
48c6f328 SL	22	#define BOOT_PAGE_OFFSET 0x27000
48c6f328	23
88718be3	24	#ifdef CONFIG_MTD_RAW_NAND
4e590945 TR	25	#define CFG_SYS_NAND_U_BOOT_SIZE (768 << 10)
	26	#define CFG_SYS_NAND_U_BOOT_DST 0x30000000
	27	#define CFG_SYS_NAND_U_BOOT_START 0x30000000
48c6f328 SL	28	#endif
	29
	30	#ifdef CONFIG_SPIFLASH
f49b8c1b	31	#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
65cc0e2a TR	32	#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
	33	#define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
	34	#define CFG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
	35	#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
48c6f328 SL	36	#endif
	37
	38	#ifdef CONFIG_SDCARD
f49b8c1b	39	#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
65cc0e2a TR	40	#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10)
	41	#define CFG_SYS_MMC_U_BOOT_DST (0x30000000)
	42	#define CFG_SYS_MMC_U_BOOT_START (0x30000000)
	43	#define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10)
48c6f328 SL	44	#endif
	45
	46	#endif /* CONFIG_RAMBOOT_PBL */
	47
48c6f328 SL	48	#ifndef CONFIG_RESET_VECTOR_ADDRESS
	49	#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
	50	#endif
	51
48c6f328 SL	52	/*
	53	* for slave u-boot IMAGE instored in master memory space,
	54	* PHYS must be aligned based on the SIZE
	55	*/
a322afc9 TR	56	#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
a322afc9 TR	57	#define CFG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
48c6f328	58	#ifdef CONFIG_PHYS_64BIT
a322afc9 TR	59	#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
a322afc9 TR	60	#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
48c6f328	61	#else
a322afc9 TR	62	#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
a322afc9 TR	63	#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
48c6f328 SL	64	#endif
	65	/*
	66	* for slave UCODE and ENV instored in master memory space,
	67	* PHYS must be aligned based on the SIZE
	68	*/
	69	#ifdef CONFIG_PHYS_64BIT
a322afc9 TR	70	#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
a322afc9 TR	71	#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
48c6f328	72	#else
a322afc9 TR	73	#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
a322afc9 TR	74	#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
48c6f328	75	#endif
a322afc9	76	#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
48c6f328	77	/* slave core release by master*/
a322afc9 TR	78	#define CFG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
a322afc9 TR	79	#define CFG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
48c6f328 SL	80
	81	/* PCIe Boot - Slave */
	82	#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
a322afc9 TR	83	#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
	84	#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
	85	(0x300000000ull \| CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
48c6f328	86	/* Set 1M boot space for PCIe boot */
a322afc9 TR	87	#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
	88	#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
	89	(0x300000000ull \| CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
48c6f328	90	#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
48c6f328 SL	91	#endif
48c6f328 SL	92
48c6f328 SL	93	/*
	94	* These can be toggled for performance analysis, otherwise use default.
	95	*/
65cc0e2a	96	#define CFG_SYS_INIT_L2CSR0 L2CSR0_L2E
48c6f328	97	#ifdef CONFIG_DDR_ECC
48c6f328 SL	98	#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
	99	#endif
	100
48c6f328 SL	101	/*
	102	* Config the L3 Cache as L3 SRAM
	103	*/
65cc0e2a	104	#define CFG_SYS_INIT_L3_ADDR 0xFFFC0000
a09fea1d	105	#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
48c6f328 SL	106
48c6f328 SL	107	#ifdef CONFIG_PHYS_64BIT
65cc0e2a TR	108	#define CFG_SYS_DCSRBAR 0xf0000000
65cc0e2a TR	109	#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull
48c6f328 SL	110	#endif
48c6f328 SL	111
48c6f328 SL	112	/*
	113	* DDR Setup
	114	*/
	115	#define CONFIG_VERY_BIG_RAM
65cc0e2a TR	116	#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
65cc0e2a TR	117	#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
960286b6	118	#if defined(CONFIG_TARGET_T1024RDB)
48c6f328	119	#define SPD_EEPROM_ADDRESS 0x51
aa6e94de	120	#define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
9082405d	121	#elif defined(CONFIG_TARGET_T1023RDB)
aa6e94de	122	#define CFG_SYS_SDRAM_SIZE 2048
e8a7f1c3	123	#endif
48c6f328 SL	124
	125	/*
	126	* IFC Definitions
	127	*/
65cc0e2a	128	#define CFG_SYS_FLASH_BASE 0xe8000000
48c6f328	129	#ifdef CONFIG_PHYS_64BIT
65cc0e2a	130	#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull \| CFG_SYS_FLASH_BASE)
48c6f328	131	#else
65cc0e2a	132	#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
48c6f328 SL	133	#endif
48c6f328 SL	134
65cc0e2a TR	135	#define CFG_SYS_NOR0_CSPR_EXT (0xf)
65cc0e2a TR	136	#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) \| \
48c6f328 SL	137	CSPR_PORT_SIZE_16 \| \
	138	CSPR_MSEL_NOR \| \
	139	CSPR_V)
0ed384fd	140	#define CFG_SYS_NOR_AMASK IFC_AMASK(12810241024)
48c6f328 SL	141
48c6f328 SL	142	/* NOR Flash Timing Params */
960286b6	143	#if defined(CONFIG_TARGET_T1024RDB)
0ed384fd	144	#define CFG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
9082405d	145	#elif defined(CONFIG_TARGET_T1023RDB)
0ed384fd	146	#define CFG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) \| \
e8a7f1c3 SL	147	CSOR_NAND_TRHZ_80 \| CSOR_NOR_ADM_SHFT_MODE_EN)
e8a7f1c3 SL	148	#endif
0ed384fd	149	#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) \| \
48c6f328 SL	150	FTIM0_NOR_TEADC(0x5) \| \
48c6f328 SL	151	FTIM0_NOR_TEAHC(0x5))
0ed384fd	152	#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) \| \
48c6f328 SL	153	FTIM1_NOR_TRAD_NOR(0x1A) \|\
48c6f328 SL	154	FTIM1_NOR_TSEQRAD_NOR(0x13))
0ed384fd	155	#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) \| \
48c6f328 SL	156	FTIM2_NOR_TCH(0x4) \| \
	157	FTIM2_NOR_TWPH(0x0E) \| \
	158	FTIM2_NOR_TWP(0x1c))
0ed384fd	159	#define CFG_SYS_NOR_FTIM3 0x0
48c6f328	160
48c6f328 SL	161	#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
48c6f328 SL	162
65cc0e2a	163	#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS}
48c6f328	164
960286b6	165	#ifdef CONFIG_TARGET_T1024RDB
48c6f328	166	/* CPLD on IFC */
65cc0e2a TR	167	#define CFG_SYS_CPLD_BASE 0xffdf0000
	168	#define CFG_SYS_CPLD_BASE_PHYS (0xf00000000ull \| CFG_SYS_CPLD_BASE)
	169	#define CFG_SYS_CSPR2_EXT (0xf)
	170	#define CFG_SYS_CSPR2 (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE) \
48c6f328 SL	171	\| CSPR_PORT_SIZE_8 \
	172	\| CSPR_MSEL_GPCM \
	173	\| CSPR_V)
65cc0e2a TR	174	#define CFG_SYS_AMASK2 IFC_AMASK(64*1024)
65cc0e2a TR	175	#define CFG_SYS_CSOR2 0x0
48c6f328 SL	176
48c6f328 SL	177	/* CPLD Timing parameters for IFC CS2 */
65cc0e2a	178	#define CFG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) \| \
48c6f328 SL	179	FTIM0_GPCM_TEADC(0x0e) \| \
48c6f328 SL	180	FTIM0_GPCM_TEAHC(0x0e))
65cc0e2a	181	#define CFG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) \| \
48c6f328	182	FTIM1_GPCM_TRAD(0x1f))
65cc0e2a	183	#define CFG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) \| \
48c6f328 SL	184	FTIM2_GPCM_TCH(0x8) \| \
48c6f328 SL	185	FTIM2_GPCM_TWP(0x1f))
65cc0e2a	186	#define CFG_SYS_CS2_FTIM3 0x0
e8a7f1c3	187	#endif
48c6f328 SL	188
48c6f328 SL	189	/* NAND Flash on IFC */
4e590945	190	#define CFG_SYS_NAND_BASE 0xff800000
48c6f328	191	#ifdef CONFIG_PHYS_64BIT
4e590945	192	#define CFG_SYS_NAND_BASE_PHYS (0xf00000000ull \| CFG_SYS_NAND_BASE)
48c6f328	193	#else
4e590945	194	#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
48c6f328	195	#endif
4e590945 TR	196	#define CFG_SYS_NAND_CSPR_EXT (0xf)
4e590945 TR	197	#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
48c6f328 SL	198	\| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
	199	\| CSPR_MSEL_NAND /* MSEL = NAND */ \
	200	\| CSPR_V)
4e590945	201	#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024)
48c6f328	202
960286b6	203	#if defined(CONFIG_TARGET_T1024RDB)
4e590945	204	#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
48c6f328 SL	205	\| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
	206	\| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
	207	\| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
	208	\| CSOR_NAND_PGS_4K /* Page Size = 4K */ \
	209	\| CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
	210	\| CSOR_NAND_PB(64)) /Pages Per Block = 64/
9082405d	211	#elif defined(CONFIG_TARGET_T1023RDB)
4e590945	212	#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
7842950f JS	213	\| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
7842950f JS	214	\| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
e8a7f1c3 SL	215	\| CSOR_NAND_RAL_3 /* RAL 3Bytes */ \
	216	\| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
	217	\| CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \
	218	\| CSOR_NAND_PB(64)) /Pages Per Block = 64/
e8a7f1c3	219	#endif
48c6f328	220
48c6f328	221	/* ONFI NAND Flash mode0 Timing Params */
4e590945	222	#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) \| \
48c6f328 SL	223	FTIM0_NAND_TWP(0x18) \| \
	224	FTIM0_NAND_TWCHT(0x07) \| \
	225	FTIM0_NAND_TWH(0x0a))
4e590945	226	#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) \| \
48c6f328 SL	227	FTIM1_NAND_TWBE(0x39) \| \
	228	FTIM1_NAND_TRR(0x0e) \| \
	229	FTIM1_NAND_TRP(0x18))
4e590945	230	#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) \| \
48c6f328 SL	231	FTIM2_NAND_TREH(0x0a) \| \
48c6f328 SL	232	FTIM2_NAND_TWHRE(0x1e))
4e590945	233	#define CFG_SYS_NAND_FTIM3 0x0
48c6f328	234
4e590945	235	#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
48c6f328	236
88718be3	237	#if defined(CONFIG_MTD_RAW_NAND)
65cc0e2a TR	238	#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
	239	#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
	240	#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
	241	#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
	242	#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
	243	#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
	244	#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
	245	#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
	246	#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT
	247	#define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR
	248	#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
	249	#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
	250	#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
	251	#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
	252	#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
	253	#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
48c6f328	254	#else
65cc0e2a TR	255	#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
	256	#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR
	257	#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
	258	#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
	259	#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
	260	#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
	261	#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
	262	#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
	263	#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
	264	#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR
	265	#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK
	266	#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR
	267	#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
	268	#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
	269	#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
	270	#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
48c6f328 SL	271	#endif
48c6f328 SL	272
48c6f328 SL	273	/* define to use L1 as initial stack */
48c6f328 SL	274	#define CONFIG_L1_INIT_RAM
65cc0e2a	275	#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
48c6f328	276	#ifdef CONFIG_PHYS_64BIT
65cc0e2a TR	277	#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
65cc0e2a TR	278	#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
48c6f328	279	/* The assembler doesn't like typecast */
65cc0e2a TR	280	#define CFG_SYS_INIT_RAM_ADDR_PHYS \
	281	((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) \| \
	282	CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
48c6f328	283	#else
65cc0e2a TR	284	#define CFG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
	285	#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
	286	#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR_PHYS
48c6f328	287	#endif
65cc0e2a	288	#define CFG_SYS_INIT_RAM_SIZE 0x00004000
48c6f328	289
65cc0e2a	290	#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
48c6f328	291
48c6f328	292	/* Serial Port */
91092132	293	#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2)
48c6f328	294
65cc0e2a	295	#define CFG_SYS_BAUDRATE_TABLE \
48c6f328 SL	296	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
48c6f328 SL	297
65cc0e2a TR	298	#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500)
	299	#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600)
	300	#define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500)
	301	#define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600)
48c6f328	302
48c6f328	303	/* I2C */
48c6f328	304
ff7ea2d1 SL	305	#define I2C_PCA6408_BUS_NUM 1
ff7ea2d1 SL	306	#define I2C_PCA6408_ADDR 0x20
48c6f328 SL	307
	308	/* I2C bus multiplexer */
	309	#define I2C_MUX_CH_DEFAULT 0x8
	310
	311	/*
	312	* RTC configuration
	313	*/
	314	#define RTC
	315	#define CONFIG_RTC_DS1337 1
65cc0e2a	316	#define CFG_SYS_I2C_RTC_ADDR 0x68
48c6f328 SL	317
	318	/*
	319	* eSPI - Enhanced SPI
	320	*/
48c6f328 SL	321
	322	/*
	323	* General PCIe
	324	* Memory space is mapped 1-1, but I/O space must start from 0.
	325	*/
48c6f328 SL	326
	327	#ifdef CONFIG_PCI
	328	/* controller 1, direct to uli, tgtid 3, Base address 20000 */
	329	#ifdef CONFIG_PCIE1
ecc8d425 TR	330	#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000
	331	#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
	332	#define CFG_SYS_PCIE1_IO_VIRT 0xf8000000
	333	#define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull
48c6f328 SL	334	#endif
	335
	336	/* controller 2, Slot 2, tgtid 2, Base address 201000 */
	337	#ifdef CONFIG_PCIE2
ecc8d425 TR	338	#define CFG_SYS_PCIE2_MEM_VIRT 0x90000000
	339	#define CFG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
	340	#define CFG_SYS_PCIE2_IO_VIRT 0xf8010000
	341	#define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull
48c6f328 SL	342	#endif
	343
	344	/* controller 3, Slot 1, tgtid 1, Base address 202000 */
	345	#ifdef CONFIG_PCIE3
ecc8d425 TR	346	#define CFG_SYS_PCIE3_MEM_VIRT 0xa0000000
ecc8d425 TR	347	#define CFG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
48c6f328	348	#endif
48c6f328 SL	349	#endif /* CONFIG_PCI */
	350
	351	/*
	352	* USB
	353	*/
48c6f328	354
48c6f328 SL	355	/*
	356	* SDHC
	357	*/
48c6f328	358	#ifdef CONFIG_MMC
6cc04547	359	#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
48c6f328 SL	360	#endif
	361
	362	/* Qman/Bman */
	363	#ifndef CONFIG_NOBQFMAN
65cc0e2a TR	364	#define CFG_SYS_BMAN_NUM_PORTALS 10
65cc0e2a TR	365	#define CFG_SYS_BMAN_MEM_BASE 0xf4000000
48c6f328	366	#ifdef CONFIG_PHYS_64BIT
65cc0e2a	367	#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull
48c6f328	368	#else
65cc0e2a	369	#define CFG_SYS_BMAN_MEM_PHYS CFG_SYS_BMAN_MEM_BASE
48c6f328	370	#endif
65cc0e2a TR	371	#define CFG_SYS_BMAN_MEM_SIZE 0x02000000
	372	#define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000
	373	#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000
	374	#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE
	375	#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
	376	#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \
	377	CFG_SYS_BMAN_CENA_SIZE)
	378	#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
	379	#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08
	380	#define CFG_SYS_QMAN_NUM_PORTALS 10
	381	#define CFG_SYS_QMAN_MEM_BASE 0xf6000000
48c6f328	382	#ifdef CONFIG_PHYS_64BIT
65cc0e2a	383	#define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull
48c6f328	384	#else
65cc0e2a	385	#define CFG_SYS_QMAN_MEM_PHYS CFG_SYS_QMAN_MEM_BASE
48c6f328	386	#endif
65cc0e2a TR	387	#define CFG_SYS_QMAN_MEM_SIZE 0x02000000
	388	#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000
	389	#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
	390	#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \
	391	CFG_SYS_QMAN_CENA_SIZE)
	392	#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
	393	#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08
	394
48c6f328 SL	395	#endif /* CONFIG_NOBQFMAN */
	396
	397	#ifdef CONFIG_SYS_DPAA_FMAN
960286b6	398	#if defined(CONFIG_TARGET_T1024RDB)
48c6f328 SL	399	#define RGMII_PHY1_ADDR 0x2
48c6f328 SL	400	#define RGMII_PHY2_ADDR 0x6
e8a7f1c3	401	#define SGMII_AQR_PHY_ADDR 0x2
48c6f328	402	#define FM1_10GEC1_PHY_ADDR 0x1
9082405d	403	#elif defined(CONFIG_TARGET_T1023RDB)
e8a7f1c3 SL	404	#define RGMII_PHY1_ADDR 0x1
	405	#define SGMII_RTK_PHY_ADDR 0x3
	406	#define SGMII_AQR_PHY_ADDR 0x2
	407	#endif
48c6f328 SL	408	#endif
48c6f328 SL	409
48c6f328 SL	410	/*
	411	* Dynamic MTD Partition support with mtdparts
	412	*/
48c6f328	413
48c6f328 SL	414	/*
	415	* Miscellaneous configurable options
	416	*/
48c6f328 SL	417
	418	/*
	419	* For booting Linux, the board info and command line data
	420	* have to be in the first 64 MB of memory, since this is
	421	* the maximum mapped by the Linux kernel during initialization.
	422	*/
65cc0e2a	423	#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
48c6f328	424
48c6f328 SL	425	/*
	426	* Environment Configuration
	427	*/
	428	#define CONFIG_ROOTPATH "/opt/nfsroot"
e8a7f1c3	429	#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
48c6f328 SL	430	#define __USB_PHY_TYPE utmi
48c6f328 SL	431
e5d5f5a8	432	#ifdef CONFIG_ARCH_T1024
47267f82 TR	433	#define ARCH_EXTRA_ENV_SETTINGS \
	434	"bank_intlv=cs0_cs1\0" \
	435	"ramdiskfile=t1024rdb/ramdisk.uboot\0" \
	436	"fdtfile=t1024rdb/t1024rdb.dtb\0"
48c6f328	437	#else
47267f82 TR	438	#define ARCH_EXTRA_ENV_SETTINGS \
	439	"bank_intlv=null\0" \
	440	"ramdiskfile=t1023rdb/ramdisk.uboot\0" \
	441	"fdtfile=t1023rdb/t1023rdb.dtb\0"
48c6f328 SL	442	#endif
	443
	444	#define CONFIG_EXTRA_ENV_SETTINGS \
47267f82	445	ARCH_EXTRA_ENV_SETTINGS \
48c6f328	446	"hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
48c6f328	447	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
48c6f328	448	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
98463903	449	"ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \
48c6f328 SL	450	"bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
	451	"netdev=eth0\0" \
	452	"tftpflash=tftpboot $loadaddr $uboot && " \
	453	"protect off $ubootaddr +$filesize && " \
	454	"erase $ubootaddr +$filesize && " \
	455	"cp.b $loadaddr $ubootaddr $filesize && " \
	456	"protect on $ubootaddr +$filesize && " \
	457	"cmp.b $loadaddr $ubootaddr $filesize\0" \
	458	"consoledev=ttyS0\0" \
	459	"ramdiskaddr=2000000\0" \
b24a4f62	460	"fdtaddr=1e00000\0" \
48c6f328 SL	461	"bdev=sda3\0"
48c6f328 SL	462
48c6f328	463	#include <asm/fsl_secure_boot.h>
ef6c55a2	464
48c6f328	465	#endif /* __T1024RDB_H */