[u-boot.git] / include / configs / T102xRDB.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2014 Freescale Semiconductor, Inc.
 * Copyright 2020-2021 NXP
 */

/*
 * T1024/T1023 RDB board configuration file
 */

#ifndef __T1024RDB_H
#define __T1024RDB_H

#include <linux/stringify.h>

/* High Level Configuration Options */

#define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS

#ifdef CONFIG_RAMBOOT_PBL
#define RESET_VECTOR_OFFSET		0x27FFC
#define BOOT_PAGE_OFFSET		0x27000

#ifdef CONFIG_MTD_RAW_NAND
#define CFG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
#define CFG_SYS_NAND_U_BOOT_DST	0x30000000
#define CFG_SYS_NAND_U_BOOT_START	0x30000000
#endif

#ifdef CONFIG_SPIFLASH
#define CONFIG_RESET_VECTOR_ADDRESS		0x30000FFC
#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE	(768 << 10)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST		(0x30000000)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_START	(0x30000000)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS	(256 << 10)
#endif

#ifdef CONFIG_SDCARD
#define CONFIG_RESET_VECTOR_ADDRESS	0x30000FFC
#define CONFIG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
#define CONFIG_SYS_MMC_U_BOOT_DST	(0x30000000)
#define CONFIG_SYS_MMC_U_BOOT_START	(0x30000000)
#define CONFIG_SYS_MMC_U_BOOT_OFFS	(260 << 10)
#endif

#endif /* CONFIG_RAMBOOT_PBL */

#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
#endif

/* PCIe Boot - Master */
#define CONFIG_SRIO_PCIE_BOOT_MASTER
/*
 * for slave u-boot IMAGE instored in master memory space,
 * PHYS must be aligned based on the SIZE
 */
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
#else
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
#endif
/*
 * for slave UCODE and ENV instored in master memory space,
 * PHYS must be aligned based on the SIZE
 */
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS	 0x3ffe00000ull
#else
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0xffe00000
#endif
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE	0x40000 /* 256K */
/* slave core release by master*/
#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET	0xe00e4
#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK	0x00000001 /* release core 0 */

/* PCIe Boot - Slave */
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
/* Set 1M boot space for PCIe boot */
#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS	\
		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#endif

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_SYS_INIT_L2CSR0		L2CSR0_L2E
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
#endif

/*
 *  Config the L3 Cache as L3 SRAM
 */
#define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
#define SPL_ENV_ADDR			(CONFIG_SPL_GD_ADDR + 4 * 1024)

#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_DCSRBAR		0xf0000000
#define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
#endif

/*
 * DDR Setup
 */
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
#if defined(CONFIG_TARGET_T1024RDB)
#define SPD_EEPROM_ADDRESS	0x51
#define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
#elif defined(CONFIG_TARGET_T1023RDB)
#define CONFIG_SYS_SDRAM_SIZE   2048
#endif

/*
 * IFC Definitions
 */
#define CONFIG_SYS_FLASH_BASE	0xe8000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
#else
#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
#endif

#define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
				CSPR_PORT_SIZE_16 | \
				CSPR_MSEL_NOR | \
				CSPR_V)
#define CFG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)

/* NOR Flash Timing Params */
#if defined(CONFIG_TARGET_T1024RDB)
#define CFG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
#elif defined(CONFIG_TARGET_T1023RDB)
#define CFG_SYS_NOR_CSOR    (CSOR_NOR_ADM_SHIFT(0) | \
				CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
#endif
#define CFG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
				FTIM0_NOR_TEADC(0x5) | \
				FTIM0_NOR_TEAHC(0x5))
#define CFG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
				FTIM1_NOR_TRAD_NOR(0x1A) |\
				FTIM1_NOR_TSEQRAD_NOR(0x13))
#define CFG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
				FTIM2_NOR_TCH(0x4) | \
				FTIM2_NOR_TWPH(0x0E) | \
				FTIM2_NOR_TWP(0x1c))
#define CFG_SYS_NOR_FTIM3	0x0

#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */

#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS}

#ifdef CONFIG_TARGET_T1024RDB
/* CPLD on IFC */
#define CONFIG_SYS_CPLD_BASE		0xffdf0000
#define CONFIG_SYS_CPLD_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_CPLD_BASE)
#define CONFIG_SYS_CSPR2_EXT		(0xf)
#define CONFIG_SYS_CSPR2		(CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
						| CSPR_PORT_SIZE_8 \
						| CSPR_MSEL_GPCM \
						| CSPR_V)
#define CONFIG_SYS_AMASK2		IFC_AMASK(64*1024)
#define CONFIG_SYS_CSOR2		0x0

/* CPLD Timing parameters for IFC CS2 */
#define CONFIG_SYS_CS2_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
						FTIM0_GPCM_TEADC(0x0e) | \
						FTIM0_GPCM_TEAHC(0x0e))
#define CONFIG_SYS_CS2_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \
						FTIM1_GPCM_TRAD(0x1f))
#define CONFIG_SYS_CS2_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
						FTIM2_GPCM_TCH(0x8) | \
						FTIM2_GPCM_TWP(0x1f))
#define CONFIG_SYS_CS2_FTIM3		0x0
#endif

/* NAND Flash on IFC */
#define CFG_SYS_NAND_BASE		0xff800000
#ifdef CONFIG_PHYS_64BIT
#define CFG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CFG_SYS_NAND_BASE)
#else
#define CFG_SYS_NAND_BASE_PHYS	CFG_SYS_NAND_BASE
#endif
#define CFG_SYS_NAND_CSPR_EXT	(0xf)
#define CFG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
				| CSPR_V)
#define CFG_SYS_NAND_AMASK	IFC_AMASK(64*1024)

#if defined(CONFIG_TARGET_T1024RDB)
#define CFG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
				| CSOR_NAND_RAL_3	/* RAL = 3Byes */ \
				| CSOR_NAND_PGS_4K	/* Page Size = 4K */ \
				| CSOR_NAND_SPRZ_224	/* Spare size = 224 */ \
				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
#elif defined(CONFIG_TARGET_T1023RDB)
#define CFG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */ \
				| CSOR_NAND_RAL_3	/* RAL 3Bytes */ \
				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
				| CSOR_NAND_SPRZ_128	/* Spare size = 128 */ \
				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
#endif

/* ONFI NAND Flash mode0 Timing Params */
#define CFG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
					FTIM0_NAND_TWP(0x18)   | \
					FTIM0_NAND_TWCHT(0x07) | \
					FTIM0_NAND_TWH(0x0a))
#define CFG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
					FTIM1_NAND_TWBE(0x39)  | \
					FTIM1_NAND_TRR(0x0e)   | \
					FTIM1_NAND_TRP(0x18))
#define CFG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
					FTIM2_NAND_TREH(0x0a) | \
					FTIM2_NAND_TWHRE(0x1e))
#define CFG_SYS_NAND_FTIM3		0x0

#define CFG_SYS_NAND_BASE_LIST	{ CFG_SYS_NAND_BASE }

#if defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_CSPR0_EXT		CFG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0		CFG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0		CFG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0		CFG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0		CFG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CFG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CFG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CFG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK1		CFG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR1		CFG_SYS_NOR_CSOR
#define CONFIG_SYS_CS1_FTIM0		CFG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CFG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CFG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CFG_SYS_NOR_FTIM3
#else
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK0		CFG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0		CFG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM0		CFG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CFG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CFG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CFG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR1_EXT		CFG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR1		CFG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK1		CFG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR1		CFG_SYS_NAND_CSOR
#define CONFIG_SYS_CS1_FTIM0		CFG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CFG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CFG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CFG_SYS_NAND_FTIM3
#endif

#define CONFIG_HWCONFIG

/* define to use L1 as initial stack */
#define CONFIG_L1_INIT_RAM
#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
/* The assembler doesn't like typecast */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
#else
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS	0xfe03c000 /* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
#endif
#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000

#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

/* Serial Port */
#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)

#define CONFIG_SYS_BAUDRATE_TABLE	\
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)

/* I2C */

#define I2C_PCA6408_BUS_NUM		1
#define I2C_PCA6408_ADDR		0x20

/* I2C bus multiplexer */
#define I2C_MUX_CH_DEFAULT	0x8

/*
 * RTC configuration
 */
#define RTC
#define CONFIG_RTC_DS1337	1
#define CONFIG_SYS_I2C_RTC_ADDR	0x68

/*
 * eSPI - Enhanced SPI
 */

/*
 * General PCIe
 * Memory space is mapped 1-1, but I/O space must start from 0.
 */

#ifdef CONFIG_PCI
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#ifdef CONFIG_PCIE1
#define	CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
#define	CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
#endif

/* controller 2, Slot 2, tgtid 2, Base address 201000 */
#ifdef CONFIG_PCIE2
#define CONFIG_SYS_PCIE2_MEM_VIRT	0x90000000
#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc10000000ull
#define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
#define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
#endif

/* controller 3, Slot 1, tgtid 1, Base address 202000 */
#ifdef CONFIG_PCIE3
#define CONFIG_SYS_PCIE3_MEM_VIRT	0xa0000000
#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc20000000ull
#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
#endif
#endif	/* CONFIG_PCI */

/*
 * USB
 */

/*
 * SDHC
 */
#ifdef CONFIG_MMC
#define CFG_SYS_FSL_ESDHC_ADDR	CFG_SYS_MPC85xx_ESDHC_ADDR
#endif

/* Qman/Bman */
#ifndef CONFIG_NOBQFMAN
#define CONFIG_SYS_BMAN_NUM_PORTALS	10
#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
#else
#define CONFIG_SYS_BMAN_MEM_PHYS	CONFIG_SYS_BMAN_MEM_BASE
#endif
#define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
#define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
#define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
#define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
#define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
					CONFIG_SYS_BMAN_CENA_SIZE)
#define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_BMAN_SWP_ISDR_REG	0xE08
#define CONFIG_SYS_QMAN_NUM_PORTALS	10
#define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
#else
#define CONFIG_SYS_QMAN_MEM_PHYS	CONFIG_SYS_QMAN_MEM_BASE
#endif
#define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
#define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
#define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
					CONFIG_SYS_QMAN_CENA_SIZE)
#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08

#define CONFIG_SYS_DPAA_FMAN
#endif /* CONFIG_NOBQFMAN */

#ifdef CONFIG_SYS_DPAA_FMAN
#if defined(CONFIG_TARGET_T1024RDB)
#define RGMII_PHY1_ADDR		0x2
#define RGMII_PHY2_ADDR		0x6
#define SGMII_AQR_PHY_ADDR	0x2
#define FM1_10GEC1_PHY_ADDR	0x1
#elif defined(CONFIG_TARGET_T1023RDB)
#define RGMII_PHY1_ADDR		0x1
#define SGMII_RTK_PHY_ADDR	0x3
#define SGMII_AQR_PHY_ADDR	0x2
#endif
#endif

/*
 * Dynamic MTD Partition support with mtdparts
 */

/*
 * Miscellaneous configurable options
 */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 64 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/

/*
 * Environment Configuration
 */
#define CONFIG_ROOTPATH		"/opt/nfsroot"
#define CONFIG_UBOOTPATH	u-boot.bin /* U-Boot image on TFTP server */
#define __USB_PHY_TYPE		utmi

#ifdef CONFIG_ARCH_T1024
#define ARCH_EXTRA_ENV_SETTINGS \
	"bank_intlv=cs0_cs1\0"			\
	"ramdiskfile=t1024rdb/ramdisk.uboot\0"	\
	"fdtfile=t1024rdb/t1024rdb.dtb\0"
#else
#define ARCH_EXTRA_ENV_SETTINGS \
	"bank_intlv=null\0"			\
	"ramdiskfile=t1023rdb/ramdisk.uboot\0"	\
	"fdtfile=t1023rdb/t1023rdb.dtb\0"
#endif

#define	CONFIG_EXTRA_ENV_SETTINGS				\
	ARCH_EXTRA_ENV_SETTINGS					\
	"hwconfig=fsl_ddr:ctlr_intlv=cacheline,"		\
	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"  \
	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
	"ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0"	\
	"bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
	"netdev=eth0\0"						\
	"tftpflash=tftpboot $loadaddr $uboot && "		\
	"protect off $ubootaddr +$filesize && "			\
	"erase $ubootaddr +$filesize && "			\
	"cp.b $loadaddr $ubootaddr $filesize && "		\
	"protect on $ubootaddr +$filesize && "			\
	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
	"consoledev=ttyS0\0"					\
	"ramdiskaddr=2000000\0"					\
	"fdtaddr=1e00000\0"					\
	"bdev=sda3\0"

#include <asm/fsl_secure_boot.h>

#endif	/* __T1024RDB_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
48c6f328 SL	2	/*
48c6f328 SL	3	* Copyright 2014 Freescale Semiconductor, Inc.
a97a071d	4	* Copyright 2020-2021 NXP
48c6f328 SL	5	*/
	6
	7	/*
	8	* T1024/T1023 RDB board configuration file
	9	*/
	10
	11	#ifndef __T1024RDB_H
	12	#define __T1024RDB_H
	13
1af3c7f4 SG	14	#include <linux/stringify.h>
1af3c7f4 SG	15
48c6f328	16	/* High Level Configuration Options */
48c6f328	17
51370d56	18	#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
48c6f328	19
48c6f328	20	#ifdef CONFIG_RAMBOOT_PBL
48c6f328 SL	21	#define RESET_VECTOR_OFFSET 0x27FFC
48c6f328 SL	22	#define BOOT_PAGE_OFFSET 0x27000
48c6f328	23
88718be3	24	#ifdef CONFIG_MTD_RAW_NAND
4e590945 TR	25	#define CFG_SYS_NAND_U_BOOT_SIZE (768 << 10)
	26	#define CFG_SYS_NAND_U_BOOT_DST 0x30000000
	27	#define CFG_SYS_NAND_U_BOOT_START 0x30000000
48c6f328 SL	28	#endif
	29
	30	#ifdef CONFIG_SPIFLASH
f49b8c1b	31	#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
48c6f328	32	#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
f49b8c1b	33	#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
f49b8c1b	34	#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
48c6f328	35	#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
48c6f328 SL	36	#endif
	37
	38	#ifdef CONFIG_SDCARD
f49b8c1b	39	#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
48c6f328	40	#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
f49b8c1b	41	#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
f49b8c1b	42	#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
48c6f328	43	#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
48c6f328 SL	44	#endif
	45
	46	#endif /* CONFIG_RAMBOOT_PBL */
	47
48c6f328 SL	48	#ifndef CONFIG_RESET_VECTOR_ADDRESS
	49	#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
	50	#endif
	51
48c6f328 SL	52	/* PCIe Boot - Master */
	53	#define CONFIG_SRIO_PCIE_BOOT_MASTER
	54	/*
	55	* for slave u-boot IMAGE instored in master memory space,
	56	* PHYS must be aligned based on the SIZE
	57	*/
	58	#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
	59	#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
	60	#ifdef CONFIG_PHYS_64BIT
	61	#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
	62	#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
	63	#else
	64	#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
	65	#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
	66	#endif
	67	/*
	68	* for slave UCODE and ENV instored in master memory space,
	69	* PHYS must be aligned based on the SIZE
	70	*/
	71	#ifdef CONFIG_PHYS_64BIT
	72	#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
	73	#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
	74	#else
	75	#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
	76	#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
	77	#endif
	78	#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
	79	/* slave core release by master*/
	80	#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
	81	#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
	82
	83	/* PCIe Boot - Slave */
	84	#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
	85	#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
	86	#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
	87	(0x300000000ull \| CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
	88	/* Set 1M boot space for PCIe boot */
98463903	89	#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
48c6f328 SL	90	#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
	91	(0x300000000ull \| CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
	92	#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
48c6f328 SL	93	#endif
48c6f328 SL	94
48c6f328 SL	95	/*
	96	* These can be toggled for performance analysis, otherwise use default.
	97	*/
48c6f328	98	#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
48c6f328	99	#ifdef CONFIG_DDR_ECC
48c6f328 SL	100	#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
	101	#endif
	102
48c6f328 SL	103	/*
	104	* Config the L3 Cache as L3 SRAM
	105	*/
	106	#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
a09fea1d	107	#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
48c6f328 SL	108
	109	#ifdef CONFIG_PHYS_64BIT
	110	#define CONFIG_SYS_DCSRBAR 0xf0000000
	111	#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
	112	#endif
	113
48c6f328 SL	114	/*
	115	* DDR Setup
	116	*/
	117	#define CONFIG_VERY_BIG_RAM
	118	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
	119	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
960286b6	120	#if defined(CONFIG_TARGET_T1024RDB)
48c6f328	121	#define SPD_EEPROM_ADDRESS 0x51
48c6f328	122	#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
9082405d	123	#elif defined(CONFIG_TARGET_T1023RDB)
e8a7f1c3 SL	124	#define CONFIG_SYS_SDRAM_SIZE 2048
e8a7f1c3 SL	125	#endif
48c6f328 SL	126
	127	/*
	128	* IFC Definitions
	129	*/
	130	#define CONFIG_SYS_FLASH_BASE 0xe8000000
	131	#ifdef CONFIG_PHYS_64BIT
	132	#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull \| CONFIG_SYS_FLASH_BASE)
	133	#else
	134	#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
	135	#endif
	136
	137	#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
	138	#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \| \
	139	CSPR_PORT_SIZE_16 \| \
	140	CSPR_MSEL_NOR \| \
	141	CSPR_V)
0ed384fd	142	#define CFG_SYS_NOR_AMASK IFC_AMASK(12810241024)
48c6f328 SL	143
48c6f328 SL	144	/* NOR Flash Timing Params */
960286b6	145	#if defined(CONFIG_TARGET_T1024RDB)
0ed384fd	146	#define CFG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
9082405d	147	#elif defined(CONFIG_TARGET_T1023RDB)
0ed384fd	148	#define CFG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) \| \
e8a7f1c3 SL	149	CSOR_NAND_TRHZ_80 \| CSOR_NOR_ADM_SHFT_MODE_EN)
e8a7f1c3 SL	150	#endif
0ed384fd	151	#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) \| \
48c6f328 SL	152	FTIM0_NOR_TEADC(0x5) \| \
48c6f328 SL	153	FTIM0_NOR_TEAHC(0x5))
0ed384fd	154	#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) \| \
48c6f328 SL	155	FTIM1_NOR_TRAD_NOR(0x1A) \|\
48c6f328 SL	156	FTIM1_NOR_TSEQRAD_NOR(0x13))
0ed384fd	157	#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) \| \
48c6f328 SL	158	FTIM2_NOR_TCH(0x4) \| \
	159	FTIM2_NOR_TWPH(0x0E) \| \
	160	FTIM2_NOR_TWP(0x1c))
0ed384fd	161	#define CFG_SYS_NOR_FTIM3 0x0
48c6f328	162
48c6f328 SL	163	#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
48c6f328 SL	164
48c6f328 SL	165	#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
48c6f328 SL	166
960286b6	167	#ifdef CONFIG_TARGET_T1024RDB
48c6f328 SL	168	/* CPLD on IFC */
	169	#define CONFIG_SYS_CPLD_BASE 0xffdf0000
	170	#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull \| CONFIG_SYS_CPLD_BASE)
	171	#define CONFIG_SYS_CSPR2_EXT (0xf)
	172	#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
	173	\| CSPR_PORT_SIZE_8 \
	174	\| CSPR_MSEL_GPCM \
	175	\| CSPR_V)
	176	#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
	177	#define CONFIG_SYS_CSOR2 0x0
	178
	179	/* CPLD Timing parameters for IFC CS2 */
	180	#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) \| \
	181	FTIM0_GPCM_TEADC(0x0e) \| \
	182	FTIM0_GPCM_TEAHC(0x0e))
	183	#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) \| \
	184	FTIM1_GPCM_TRAD(0x1f))
	185	#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) \| \
	186	FTIM2_GPCM_TCH(0x8) \| \
	187	FTIM2_GPCM_TWP(0x1f))
	188	#define CONFIG_SYS_CS2_FTIM3 0x0
e8a7f1c3	189	#endif
48c6f328 SL	190
48c6f328 SL	191	/* NAND Flash on IFC */
4e590945	192	#define CFG_SYS_NAND_BASE 0xff800000
48c6f328	193	#ifdef CONFIG_PHYS_64BIT
4e590945	194	#define CFG_SYS_NAND_BASE_PHYS (0xf00000000ull \| CFG_SYS_NAND_BASE)
48c6f328	195	#else
4e590945	196	#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
48c6f328	197	#endif
4e590945 TR	198	#define CFG_SYS_NAND_CSPR_EXT (0xf)
4e590945 TR	199	#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
48c6f328 SL	200	\| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
	201	\| CSPR_MSEL_NAND /* MSEL = NAND */ \
	202	\| CSPR_V)
4e590945	203	#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024)
48c6f328	204
960286b6	205	#if defined(CONFIG_TARGET_T1024RDB)
4e590945	206	#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
48c6f328 SL	207	\| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
	208	\| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
	209	\| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
	210	\| CSOR_NAND_PGS_4K /* Page Size = 4K */ \
	211	\| CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
	212	\| CSOR_NAND_PB(64)) /Pages Per Block = 64/
9082405d	213	#elif defined(CONFIG_TARGET_T1023RDB)
4e590945	214	#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
7842950f JS	215	\| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
7842950f JS	216	\| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
e8a7f1c3 SL	217	\| CSOR_NAND_RAL_3 /* RAL 3Bytes */ \
	218	\| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
	219	\| CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \
	220	\| CSOR_NAND_PB(64)) /Pages Per Block = 64/
e8a7f1c3	221	#endif
48c6f328	222
48c6f328	223	/* ONFI NAND Flash mode0 Timing Params */
4e590945	224	#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) \| \
48c6f328 SL	225	FTIM0_NAND_TWP(0x18) \| \
	226	FTIM0_NAND_TWCHT(0x07) \| \
	227	FTIM0_NAND_TWH(0x0a))
4e590945	228	#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) \| \
48c6f328 SL	229	FTIM1_NAND_TWBE(0x39) \| \
	230	FTIM1_NAND_TRR(0x0e) \| \
	231	FTIM1_NAND_TRP(0x18))
4e590945	232	#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) \| \
48c6f328 SL	233	FTIM2_NAND_TREH(0x0a) \| \
48c6f328 SL	234	FTIM2_NAND_TWHRE(0x1e))
4e590945	235	#define CFG_SYS_NAND_FTIM3 0x0
48c6f328	236
4e590945	237	#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
48c6f328	238
88718be3	239	#if defined(CONFIG_MTD_RAW_NAND)
4e590945 TR	240	#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
	241	#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
	242	#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
	243	#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
	244	#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
	245	#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
	246	#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
	247	#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
48c6f328 SL	248	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
48c6f328 SL	249	#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
0ed384fd TR	250	#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK
	251	#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR
	252	#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
	253	#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
	254	#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
	255	#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
48c6f328 SL	256	#else
	257	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
	258	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
0ed384fd TR	259	#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
	260	#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
	261	#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
	262	#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
	263	#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
	264	#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
4e590945 TR	265	#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
	266	#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR
	267	#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK
	268	#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR
	269	#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
	270	#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
	271	#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
	272	#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
48c6f328 SL	273	#endif
48c6f328 SL	274
48c6f328 SL	275	#define CONFIG_HWCONFIG
	276
	277	/* define to use L1 as initial stack */
	278	#define CONFIG_L1_INIT_RAM
48c6f328 SL	279	#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
	280	#ifdef CONFIG_PHYS_64BIT
	281	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
b3142e2c	282	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
48c6f328 SL	283	/* The assembler doesn't like typecast */
	284	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
	285	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) \| \
	286	CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
	287	#else
b3142e2c	288	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
48c6f328 SL	289	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
	290	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
	291	#endif
	292	#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
	293
4c97c8cd	294	#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
48c6f328	295
48c6f328	296	/* Serial Port */
48c6f328 SL	297	#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
	298
	299	#define CONFIG_SYS_BAUDRATE_TABLE \
	300	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
	301
	302	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
	303	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
	304	#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
	305	#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
48c6f328	306
48c6f328	307	/* I2C */
48c6f328	308
ff7ea2d1 SL	309	#define I2C_PCA6408_BUS_NUM 1
ff7ea2d1 SL	310	#define I2C_PCA6408_ADDR 0x20
48c6f328 SL	311
	312	/* I2C bus multiplexer */
	313	#define I2C_MUX_CH_DEFAULT 0x8
	314
	315	/*
	316	* RTC configuration
	317	*/
	318	#define RTC
	319	#define CONFIG_RTC_DS1337 1
	320	#define CONFIG_SYS_I2C_RTC_ADDR 0x68
	321
	322	/*
	323	* eSPI - Enhanced SPI
	324	*/
48c6f328 SL	325
	326	/*
	327	* General PCIe
	328	* Memory space is mapped 1-1, but I/O space must start from 0.
	329	*/
48c6f328 SL	330
	331	#ifdef CONFIG_PCI
	332	/* controller 1, direct to uli, tgtid 3, Base address 20000 */
	333	#ifdef CONFIG_PCIE1
	334	#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
48c6f328	335	#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
48c6f328	336	#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
48c6f328	337	#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
48c6f328 SL	338	#endif
	339
	340	/* controller 2, Slot 2, tgtid 2, Base address 201000 */
	341	#ifdef CONFIG_PCIE2
	342	#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
48c6f328	343	#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
48c6f328	344	#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
48c6f328	345	#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
48c6f328 SL	346	#endif
	347
	348	/* controller 3, Slot 1, tgtid 1, Base address 202000 */
	349	#ifdef CONFIG_PCIE3
	350	#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
48c6f328	351	#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
48c6f328	352	#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
48c6f328	353	#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
48c6f328	354	#endif
48c6f328 SL	355	#endif /* CONFIG_PCI */
	356
	357	/*
	358	* USB
	359	*/
48c6f328	360
48c6f328 SL	361	/*
	362	* SDHC
	363	*/
48c6f328	364	#ifdef CONFIG_MMC
6cc04547	365	#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
48c6f328 SL	366	#endif
	367
	368	/* Qman/Bman */
	369	#ifndef CONFIG_NOBQFMAN
2a8b3422	370	#define CONFIG_SYS_BMAN_NUM_PORTALS 10
48c6f328 SL	371	#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
	372	#ifdef CONFIG_PHYS_64BIT
	373	#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
	374	#else
	375	#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
	376	#endif
	377	#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
3fa66db4 JL	378	#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
	379	#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
	380	#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
	381	#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
	382	#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
	383	CONFIG_SYS_BMAN_CENA_SIZE)
	384	#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
	385	#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
2a8b3422	386	#define CONFIG_SYS_QMAN_NUM_PORTALS 10
48c6f328 SL	387	#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
	388	#ifdef CONFIG_PHYS_64BIT
	389	#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
	390	#else
	391	#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
	392	#endif
	393	#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
3fa66db4 JL	394	#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
	395	#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
	396	#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
	397	#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
	398	#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
	399	CONFIG_SYS_QMAN_CENA_SIZE)
	400	#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
	401	#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
48c6f328 SL	402
48c6f328 SL	403	#define CONFIG_SYS_DPAA_FMAN
48c6f328 SL	404	#endif /* CONFIG_NOBQFMAN */
	405
	406	#ifdef CONFIG_SYS_DPAA_FMAN
960286b6	407	#if defined(CONFIG_TARGET_T1024RDB)
48c6f328 SL	408	#define RGMII_PHY1_ADDR 0x2
48c6f328 SL	409	#define RGMII_PHY2_ADDR 0x6
e8a7f1c3	410	#define SGMII_AQR_PHY_ADDR 0x2
48c6f328	411	#define FM1_10GEC1_PHY_ADDR 0x1
9082405d	412	#elif defined(CONFIG_TARGET_T1023RDB)
e8a7f1c3 SL	413	#define RGMII_PHY1_ADDR 0x1
	414	#define SGMII_RTK_PHY_ADDR 0x3
	415	#define SGMII_AQR_PHY_ADDR 0x2
	416	#endif
48c6f328 SL	417	#endif
48c6f328 SL	418
48c6f328 SL	419	/*
	420	* Dynamic MTD Partition support with mtdparts
	421	*/
48c6f328	422
48c6f328 SL	423	/*
	424	* Miscellaneous configurable options
	425	*/
48c6f328 SL	426
	427	/*
	428	* For booting Linux, the board info and command line data
	429	* have to be in the first 64 MB of memory, since this is
	430	* the maximum mapped by the Linux kernel during initialization.
	431	*/
	432	#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
48c6f328	433
48c6f328 SL	434	/*
	435	* Environment Configuration
	436	*/
	437	#define CONFIG_ROOTPATH "/opt/nfsroot"
e8a7f1c3	438	#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
48c6f328 SL	439	#define __USB_PHY_TYPE utmi
48c6f328 SL	440
e5d5f5a8	441	#ifdef CONFIG_ARCH_T1024
47267f82 TR	442	#define ARCH_EXTRA_ENV_SETTINGS \
	443	"bank_intlv=cs0_cs1\0" \
	444	"ramdiskfile=t1024rdb/ramdisk.uboot\0" \
	445	"fdtfile=t1024rdb/t1024rdb.dtb\0"
48c6f328	446	#else
47267f82 TR	447	#define ARCH_EXTRA_ENV_SETTINGS \
	448	"bank_intlv=null\0" \
	449	"ramdiskfile=t1023rdb/ramdisk.uboot\0" \
	450	"fdtfile=t1023rdb/t1023rdb.dtb\0"
48c6f328 SL	451	#endif
	452
	453	#define CONFIG_EXTRA_ENV_SETTINGS \
47267f82	454	ARCH_EXTRA_ENV_SETTINGS \
48c6f328	455	"hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
48c6f328	456	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
48c6f328	457	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
98463903	458	"ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \
48c6f328 SL	459	"bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
	460	"netdev=eth0\0" \
	461	"tftpflash=tftpboot $loadaddr $uboot && " \
	462	"protect off $ubootaddr +$filesize && " \
	463	"erase $ubootaddr +$filesize && " \
	464	"cp.b $loadaddr $ubootaddr $filesize && " \
	465	"protect on $ubootaddr +$filesize && " \
	466	"cmp.b $loadaddr $ubootaddr $filesize\0" \
	467	"consoledev=ttyS0\0" \
	468	"ramdiskaddr=2000000\0" \
b24a4f62	469	"fdtaddr=1e00000\0" \
48c6f328 SL	470	"bdev=sda3\0"
48c6f328 SL	471
48c6f328	472	#include <asm/fsl_secure_boot.h>
ef6c55a2	473
48c6f328	474	#endif /* __T1024RDB_H */