[u-boot.git] / board / liebherr / display5 / spl.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2017 DENX Software Engineering
 * Lukasz Majewski, DENX Software Engineering, [email protected]
 */

#include <common.h>
#include <env.h>
#include <spl.h>
#include <linux/libfdt.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/mx6-ddr.h>
#include <asm/arch/mx6-pins.h>
#include "asm/arch/crm_regs.h"
#include <asm/arch/sys_proto.h>
#include <asm/arch/imx-regs.h>
#include "asm/arch/iomux.h"
#include <asm/mach-imx/iomux-v3.h>
#include <asm/gpio.h>
#include <environment.h>
#include <fsl_esdhc_imx.h>
#include <netdev.h>
#include <bootcount.h>
#include <watchdog.h>
#include "common.h"

DECLARE_GLOBAL_DATA_PTR;

static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
	.dram_sdclk_0 = 0x00000030,
	.dram_sdclk_1 = 0x00000030,
	.dram_cas = 0x00000030,
	.dram_ras = 0x00000030,
	.dram_reset = 0x00000030,
	.dram_sdcke0 = 0x00003000,
	.dram_sdcke1 = 0x00003000,
	.dram_sdba2 = 0x00000000,
	.dram_sdodt0 = 0x00000030,
	.dram_sdodt1 = 0x00000030,

	.dram_sdqs0 = 0x00000030,
	.dram_sdqs1 = 0x00000030,
	.dram_sdqs2 = 0x00000030,
	.dram_sdqs3 = 0x00000030,
	.dram_sdqs4 = 0x00000030,
	.dram_sdqs5 = 0x00000030,
	.dram_sdqs6 = 0x00000030,
	.dram_sdqs7 = 0x00000030,

	.dram_dqm0 = 0x00000030,
	.dram_dqm1 = 0x00000030,
	.dram_dqm2 = 0x00000030,
	.dram_dqm3 = 0x00000030,
	.dram_dqm4 = 0x00000030,
	.dram_dqm5 = 0x00000030,
	.dram_dqm6 = 0x00000030,
	.dram_dqm7 = 0x00000030,
};

static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
	.grp_ddr_type = 0x000c0000,
	.grp_ddrmode_ctl = 0x00020000,
	.grp_ddrpke = 0x00000000,
	.grp_addds = 0x00000030,
	.grp_ctlds = 0x00000030,
	.grp_ddrmode = 0x00020000,
	.grp_b0ds = 0x00000030,
	.grp_b1ds = 0x00000030,
	.grp_b2ds = 0x00000030,
	.grp_b3ds = 0x00000030,
	.grp_b4ds = 0x00000030,
	.grp_b5ds = 0x00000030,
	.grp_b6ds = 0x00000030,
	.grp_b7ds = 0x00000030,
};

/* 4x128Mx16.cfg */
static const struct mx6_mmdc_calibration mx6_4x256mx16_mmdc_calib = {
	.p0_mpwldectrl0 = 0x002D0028,
	.p0_mpwldectrl1 = 0x0032002D,
	.p1_mpwldectrl0 = 0x00210036,
	.p1_mpwldectrl1 = 0x0019002E,
	.p0_mpdgctrl0 = 0x4349035C,
	.p0_mpdgctrl1 = 0x0348033D,
	.p1_mpdgctrl0 = 0x43550362,
	.p1_mpdgctrl1 = 0x03520316,
	.p0_mprddlctl = 0x41393940,
	.p1_mprddlctl = 0x3F3A3C47,
	.p0_mpwrdlctl = 0x413A423A,
	.p1_mpwrdlctl = 0x4042483E,
};

/* MT41K128M16JT-125 (2Gb density) */
static const struct mx6_ddr3_cfg mt41k128m16jt_125 = {
	.mem_speed = 1600,
	.density = 2,
	.width = 16,
	.banks = 8,
	.rowaddr = 14,
	.coladdr = 10,
	.pagesz = 2,
	.trcd = 1375,
	.trcmin = 4875,
	.trasmin = 3500,
};

static void ccgr_init(void)
{
	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

	writel(0x00C03F3F, &ccm->CCGR0);
	writel(0x0030FC3F, &ccm->CCGR1);
	writel(0x0FFFCFC0, &ccm->CCGR2);
	writel(0x3FF00000, &ccm->CCGR3);
	writel(0x00FFF300, &ccm->CCGR4);
	writel(0x0F0000C3, &ccm->CCGR5);
	writel(0x000003FF, &ccm->CCGR6);
}

#ifdef CONFIG_MX6_DDRCAL
static void spl_dram_print_cal(struct mx6_ddr_sysinfo const *sysinfo)
{
	struct mx6_mmdc_calibration calibration = {0};

	mmdc_read_calibration(sysinfo, &calibration);

	debug(".p0_mpdgctrl0\t= 0x%08X\n", calibration.p0_mpdgctrl0);
	debug(".p0_mpdgctrl1\t= 0x%08X\n", calibration.p0_mpdgctrl1);
	debug(".p0_mprddlctl\t= 0x%08X\n", calibration.p0_mprddlctl);
	debug(".p0_mpwrdlctl\t= 0x%08X\n", calibration.p0_mpwrdlctl);
	debug(".p0_mpwldectrl0\t= 0x%08X\n", calibration.p0_mpwldectrl0);
	debug(".p0_mpwldectrl1\t= 0x%08X\n", calibration.p0_mpwldectrl1);
	debug(".p1_mpdgctrl0\t= 0x%08X\n", calibration.p1_mpdgctrl0);
	debug(".p1_mpdgctrl1\t= 0x%08X\n", calibration.p1_mpdgctrl1);
	debug(".p1_mprddlctl\t= 0x%08X\n", calibration.p1_mprddlctl);
	debug(".p1_mpwrdlctl\t= 0x%08X\n", calibration.p1_mpwrdlctl);
	debug(".p1_mpwldectrl0\t= 0x%08X\n", calibration.p1_mpwldectrl0);
	debug(".p1_mpwldectrl1\t= 0x%08X\n", calibration.p1_mpwldectrl1);
}

static void spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo)
{
	int ret;

	/* Perform DDR DRAM calibration */
	udelay(100);
	ret = mmdc_do_write_level_calibration(sysinfo);
	if (ret) {
		printf("DDR: Write level calibration error [%d]\n", ret);
		return;
	}

	ret = mmdc_do_dqs_calibration(sysinfo);
	if (ret) {
		printf("DDR: DQS calibration error [%d]\n", ret);
		return;
	}

	spl_dram_print_cal(sysinfo);
}
#endif /* CONFIG_MX6_DDRCAL */

static void spl_dram_init(void)
{
	struct mx6_ddr_sysinfo sysinfo = {
		/* width of data bus:0=16,1=32,2=64 */
		.dsize = 2,
		/* config for full 4GB range so that get_mem_size() works */
		.cs_density = 32, /* 32Gb per CS */
		/* single chip select */
		.ncs = 1,
		.cs1_mirror = 0,
		.rtt_wr = 1 /*DDR3_RTT_60_OHM*/,	/* RTT_Wr = RZQ/4 */
		.rtt_nom = 2 /*DDR3_RTT_120_OHM*/,	/* RTT_Nom = RZQ/2 */
		.walat = 1,	/* Write additional latency */
		.ralat = 5,	/* Read additional latency */
		.mif3_mode = 3,	/* Command prediction working mode */
		.bi_on = 1,	/* Bank interleaving enabled */
		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
		.pd_fast_exit = 1, /* enable precharge power-down fast exit */
		.ddr_type = DDR_TYPE_DDR3,
		.refsel = 1,	/* Refresh cycles at 32KHz */
		.refr = 7,	/* 8 refresh commands per refresh cycle */
	};

	mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
	mx6_dram_cfg(&sysinfo, &mx6_4x256mx16_mmdc_calib, &mt41k128m16jt_125);

#ifdef CONFIG_MX6_DDRCAL
	spl_dram_perform_cal(&sysinfo);
#endif
}

#ifdef CONFIG_SPL_SPI_SUPPORT
static void displ5_init_ecspi(void)
{
	displ5_set_iomux_ecspi_spl();
	enable_spi_clk(1, 1);
}
#else
static inline void displ5_init_ecspi(void) { }
#endif

#ifdef CONFIG_SPL_MMC_SUPPORT
static struct fsl_esdhc_cfg usdhc_cfg = {
	.esdhc_base = USDHC4_BASE_ADDR,
	.max_bus_width = 8,
};

int board_mmc_init(bd_t *bd)
{
	displ5_set_iomux_usdhc_spl();

	usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
	gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk;

	return fsl_esdhc_initialize(bd, &usdhc_cfg);
}
#endif

void board_init_f(ulong dummy)
{
	ccgr_init();

	arch_cpu_init();

	gpr_init();

	/* setup GP timer */
	timer_init();

	displ5_set_iomux_uart_spl();

	/* UART clocks enabled and gd valid - init serial console */
	preloader_console_init();

	displ5_init_ecspi();

	/* DDR initialization */
	spl_dram_init();

	/* Clear the BSS. */
	memset(__bss_start, 0, __bss_end - __bss_start);

	displ5_set_iomux_misc_spl();

	/* Initialize and reset WDT in SPL */
	hw_watchdog_init();
	WATCHDOG_RESET();

	/* load/boot image from boot device */
	board_init_r(NULL, 0);
}

#define EM_PAD IMX_GPIO_NR(3, 29)
int board_check_emergency_pad(void)
{
	int ret;

	ret = gpio_direction_input(EM_PAD);
	if (ret)
		return ret;

	return !gpio_get_value(EM_PAD);
}

void board_boot_order(u32 *spl_boot_list)
{
	/* Default boot sequence SPI -> MMC */
	spl_boot_list[0] = spl_boot_device();
	spl_boot_list[1] = BOOT_DEVICE_MMC1;
	spl_boot_list[2] = BOOT_DEVICE_UART;
	spl_boot_list[3] = BOOT_DEVICE_NONE;

	/*
	 * In case of emergency PAD pressed, we always boot
	 * to proper u-boot and perform recovery tasks there.
	 */
	if (board_check_emergency_pad())
		return;

#ifdef CONFIG_SPL_ENV_SUPPORT
	/* 'fastboot' */
	const char *s;

	if (env_init() || env_load())
		return;

	s = env_get("BOOT_FROM");
	if (s && !bootcount_error() && strcmp(s, "ACTIVE") == 0) {
		spl_boot_list[0] = BOOT_DEVICE_MMC1;
		spl_boot_list[1] = spl_boot_device();
	}
#endif
}

void reset_cpu(ulong addr) {}

#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
	return 0;
}
#endif

#ifdef CONFIG_SPL_OS_BOOT
/* Return: 1 - boot to U-Boot. 0 - boot OS (falcon mode) */
int spl_start_uboot(void)
{
	/* break into full u-boot on 'c' */
	if (serial_tstc() && serial_getc() == 'c')
		return 1;

#ifdef CONFIG_SPL_ENV_SUPPORT
	if (env_get_yesno("boot_os") != 1)
		return 1;
#endif
	return 0;
}
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
a3eec24a LM	2	/*
	3	* Copyright (C) 2017 DENX Software Engineering
	4	* Lukasz Majewski, DENX Software Engineering, [email protected]
a3eec24a LM	5	*/
	6
	7	#include <common.h>
4bfd1f5d	8	#include <env.h>
a3eec24a	9	#include <spl.h>
b08c8c48	10	#include <linux/libfdt.h>
a3eec24a LM	11	#include <asm/io.h>
	12	#include <asm/arch/clock.h>
	13	#include <asm/arch/mx6-ddr.h>
	14	#include <asm/arch/mx6-pins.h>
	15	#include "asm/arch/crm_regs.h"
	16	#include <asm/arch/sys_proto.h>
	17	#include <asm/arch/imx-regs.h>
	18	#include "asm/arch/iomux.h"
	19	#include <asm/mach-imx/iomux-v3.h>
27aede24	20	#include <asm/gpio.h>
a3eec24a	21	#include <environment.h>
e37ac717	22	#include <fsl_esdhc_imx.h>
a3eec24a	23	#include <netdev.h>
2dbd5cd9	24	#include <bootcount.h>
76d1d169	25	#include <watchdog.h>
a3eec24a LM	26	#include "common.h"
	27
	28	DECLARE_GLOBAL_DATA_PTR;
	29
	30	static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
	31	.dram_sdclk_0 = 0x00000030,
	32	.dram_sdclk_1 = 0x00000030,
	33	.dram_cas = 0x00000030,
	34	.dram_ras = 0x00000030,
	35	.dram_reset = 0x00000030,
	36	.dram_sdcke0 = 0x00003000,
	37	.dram_sdcke1 = 0x00003000,
	38	.dram_sdba2 = 0x00000000,
	39	.dram_sdodt0 = 0x00000030,
	40	.dram_sdodt1 = 0x00000030,
	41
	42	.dram_sdqs0 = 0x00000030,
	43	.dram_sdqs1 = 0x00000030,
	44	.dram_sdqs2 = 0x00000030,
	45	.dram_sdqs3 = 0x00000030,
	46	.dram_sdqs4 = 0x00000030,
	47	.dram_sdqs5 = 0x00000030,
	48	.dram_sdqs6 = 0x00000030,
	49	.dram_sdqs7 = 0x00000030,
	50
	51	.dram_dqm0 = 0x00000030,
	52	.dram_dqm1 = 0x00000030,
	53	.dram_dqm2 = 0x00000030,
	54	.dram_dqm3 = 0x00000030,
	55	.dram_dqm4 = 0x00000030,
	56	.dram_dqm5 = 0x00000030,
	57	.dram_dqm6 = 0x00000030,
	58	.dram_dqm7 = 0x00000030,
	59	};
	60
	61	static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
	62	.grp_ddr_type = 0x000c0000,
	63	.grp_ddrmode_ctl = 0x00020000,
	64	.grp_ddrpke = 0x00000000,
	65	.grp_addds = 0x00000030,
	66	.grp_ctlds = 0x00000030,
	67	.grp_ddrmode = 0x00020000,
	68	.grp_b0ds = 0x00000030,
	69	.grp_b1ds = 0x00000030,
	70	.grp_b2ds = 0x00000030,
	71	.grp_b3ds = 0x00000030,
	72	.grp_b4ds = 0x00000030,
	73	.grp_b5ds = 0x00000030,
	74	.grp_b6ds = 0x00000030,
	75	.grp_b7ds = 0x00000030,
	76	};
	77
	78	/* 4x128Mx16.cfg */
	79	static const struct mx6_mmdc_calibration mx6_4x256mx16_mmdc_calib = {
	80	.p0_mpwldectrl0 = 0x002D0028,
	81	.p0_mpwldectrl1 = 0x0032002D,
	82	.p1_mpwldectrl0 = 0x00210036,
	83	.p1_mpwldectrl1 = 0x0019002E,
	84	.p0_mpdgctrl0 = 0x4349035C,
	85	.p0_mpdgctrl1 = 0x0348033D,
	86	.p1_mpdgctrl0 = 0x43550362,
	87	.p1_mpdgctrl1 = 0x03520316,
	88	.p0_mprddlctl = 0x41393940,
	89	.p1_mprddlctl = 0x3F3A3C47,
90	.p0_mpwrdlctl = 0x413A423A,
91	.p1_mpwrdlctl = 0x4042483E,
92	};
93
94	/* MT41K128M16JT-125 (2Gb density) */
95	static const struct mx6_ddr3_cfg mt41k128m16jt_125 = {
96	.mem_speed = 1600,
97	.density = 2,
98	.width = 16,
99	.banks = 8,
100	.rowaddr = 14,
101	.coladdr = 10,
102	.pagesz = 2,
103	.trcd = 1375,
104	.trcmin = 4875,
105	.trasmin = 3500,
106	};
107
108	static void ccgr_init(void)
109	{
110	struct mxc_ccm_reg ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
111
112	writel(0x00C03F3F, &ccm->CCGR0);
113	writel(0x0030FC3F, &ccm->CCGR1);
114	writel(0x0FFFCFC0, &ccm->CCGR2);
115	writel(0x3FF00000, &ccm->CCGR3);
116	writel(0x00FFF300, &ccm->CCGR4);
117	writel(0x0F0000C3, &ccm->CCGR5);
118	writel(0x000003FF, &ccm->CCGR6);
119	}
120
ea4584d7 LM	121	#ifdef CONFIG_MX6_DDRCAL
	122	static void spl_dram_print_cal(struct mx6_ddr_sysinfo const *sysinfo)
	123	{
	124	struct mx6_mmdc_calibration calibration = {0};
	125
	126	mmdc_read_calibration(sysinfo, &calibration);
	127
	128	debug(".p0_mpdgctrl0\t= 0x%08X\n", calibration.p0_mpdgctrl0);
	129	debug(".p0_mpdgctrl1\t= 0x%08X\n", calibration.p0_mpdgctrl1);
	130	debug(".p0_mprddlctl\t= 0x%08X\n", calibration.p0_mprddlctl);
	131	debug(".p0_mpwrdlctl\t= 0x%08X\n", calibration.p0_mpwrdlctl);
	132	debug(".p0_mpwldectrl0\t= 0x%08X\n", calibration.p0_mpwldectrl0);
	133	debug(".p0_mpwldectrl1\t= 0x%08X\n", calibration.p0_mpwldectrl1);
	134	debug(".p1_mpdgctrl0\t= 0x%08X\n", calibration.p1_mpdgctrl0);
	135	debug(".p1_mpdgctrl1\t= 0x%08X\n", calibration.p1_mpdgctrl1);
	136	debug(".p1_mprddlctl\t= 0x%08X\n", calibration.p1_mprddlctl);
	137	debug(".p1_mpwrdlctl\t= 0x%08X\n", calibration.p1_mpwrdlctl);
	138	debug(".p1_mpwldectrl0\t= 0x%08X\n", calibration.p1_mpwldectrl0);
	139	debug(".p1_mpwldectrl1\t= 0x%08X\n", calibration.p1_mpwldectrl1);
	140	}
	141
	142	static void spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo)
	143	{
	144	int ret;
	145
	146	/* Perform DDR DRAM calibration */
	147	udelay(100);
	148	ret = mmdc_do_write_level_calibration(sysinfo);
	149	if (ret) {
	150	printf("DDR: Write level calibration error [%d]\n", ret);
	151	return;
	152	}
	153
	154	ret = mmdc_do_dqs_calibration(sysinfo);
	155	if (ret) {
	156	printf("DDR: DQS calibration error [%d]\n", ret);
	157	return;
	158	}
	159
	160	spl_dram_print_cal(sysinfo);
	161	}
	162	#endif /* CONFIG_MX6_DDRCAL */
	163
a3eec24a LM	164	static void spl_dram_init(void)
	165	{
	166	struct mx6_ddr_sysinfo sysinfo = {
	167	/* width of data bus:0=16,1=32,2=64 */
	168	.dsize = 2,
	169	/* config for full 4GB range so that get_mem_size() works */
	170	.cs_density = 32, /* 32Gb per CS */
	171	/* single chip select */
	172	.ncs = 1,
	173	.cs1_mirror = 0,
	174	.rtt_wr = 1 /DDR3_RTT_60_OHM/, /* RTT_Wr = RZQ/4 */
	175	.rtt_nom = 2 /DDR3_RTT_120_OHM/, /* RTT_Nom = RZQ/2 */
	176	.walat = 1, /* Write additional latency */
	177	.ralat = 5, /* Read additional latency */
	178	.mif3_mode = 3, /* Command prediction working mode */
	179	.bi_on = 1, /* Bank interleaving enabled */
	180	.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
	181	.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
	182	.pd_fast_exit = 1, /* enable precharge power-down fast exit */
	183	.ddr_type = DDR_TYPE_DDR3,
	184	.refsel = 1, /* Refresh cycles at 32KHz */
	185	.refr = 7, /* 8 refresh commands per refresh cycle */
	186	};
	187
	188	mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
	189	mx6_dram_cfg(&sysinfo, &mx6_4x256mx16_mmdc_calib, &mt41k128m16jt_125);
ea4584d7 LM	190
	191	#ifdef CONFIG_MX6_DDRCAL
	192	spl_dram_perform_cal(&sysinfo);
	193	#endif
a3eec24a LM	194	}
	195
	196	#ifdef CONFIG_SPL_SPI_SUPPORT
	197	static void displ5_init_ecspi(void)
	198	{
	199	displ5_set_iomux_ecspi_spl();
	200	enable_spi_clk(1, 1);
	201	}
	202	#else
	203	static inline void displ5_init_ecspi(void) { }
	204	#endif
	205
	206	#ifdef CONFIG_SPL_MMC_SUPPORT
	207	static struct fsl_esdhc_cfg usdhc_cfg = {
	208	.esdhc_base = USDHC4_BASE_ADDR,
	209	.max_bus_width = 8,
	210	};
	211
	212	int board_mmc_init(bd_t *bd)
	213	{
	214	displ5_set_iomux_usdhc_spl();
	215
	216	usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
	217	gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk;
	218
	219	return fsl_esdhc_initialize(bd, &usdhc_cfg);
	220	}
	221	#endif
	222
	223	void board_init_f(ulong dummy)
	224	{
	225	ccgr_init();
	226
	227	arch_cpu_init();
	228
	229	gpr_init();
	230
	231	/* setup GP timer */
	232	timer_init();
	233
	234	displ5_set_iomux_uart_spl();
	235
	236	/* UART clocks enabled and gd valid - init serial console */
	237	preloader_console_init();
	238
	239	displ5_init_ecspi();
	240
	241	/* DDR initialization */
	242	spl_dram_init();
	243
	244	/* Clear the BSS. */
	245	memset(__bss_start, 0, __bss_end - __bss_start);
	246
27aede24 LM	247	displ5_set_iomux_misc_spl();
27aede24 LM	248
76d1d169 LM	249	/* Initialize and reset WDT in SPL */
	250	hw_watchdog_init();
	251	WATCHDOG_RESET();
	252
a3eec24a LM	253	/* load/boot image from boot device */
	254	board_init_r(NULL, 0);
	255	}
	256
27aede24 LM	257	#define EM_PAD IMX_GPIO_NR(3, 29)
	258	int board_check_emergency_pad(void)
	259	{
	260	int ret;
	261
	262	ret = gpio_direction_input(EM_PAD);
	263	if (ret)
	264	return ret;
	265
	266	return !gpio_get_value(EM_PAD);
	267	}
	268
a3eec24a LM	269	void board_boot_order(u32 *spl_boot_list)
	270	{
	271	/* Default boot sequence SPI -> MMC */
	272	spl_boot_list[0] = spl_boot_device();
	273	spl_boot_list[1] = BOOT_DEVICE_MMC1;
	274	spl_boot_list[2] = BOOT_DEVICE_UART;
	275	spl_boot_list[3] = BOOT_DEVICE_NONE;
	276
27aede24 LM	277	/*
	278	* In case of emergency PAD pressed, we always boot
	279	* to proper u-boot and perform recovery tasks there.
	280	*/
	281	if (board_check_emergency_pad())
	282	return;
	283
a3eec24a LM	284	#ifdef CONFIG_SPL_ENV_SUPPORT
	285	/* 'fastboot' */
	286	const char *s;
	287
e087905a LM	288	if (env_init() \|\| env_load())
e087905a LM	289	return;
a3eec24a LM	290
a3eec24a LM	291	s = env_get("BOOT_FROM");
2dbd5cd9	292	if (s && !bootcount_error() && strcmp(s, "ACTIVE") == 0) {
a3eec24a LM	293	spl_boot_list[0] = BOOT_DEVICE_MMC1;
	294	spl_boot_list[1] = spl_boot_device();
	295	}
	296	#endif
	297	}
	298
	299	void reset_cpu(ulong addr) {}
	300
	301	#ifdef CONFIG_SPL_LOAD_FIT
	302	int board_fit_config_name_match(const char *name)
	303	{
	304	return 0;
	305	}
	306	#endif
	307
	308	#ifdef CONFIG_SPL_OS_BOOT
	309	/* Return: 1 - boot to U-Boot. 0 - boot OS (falcon mode) */
	310	int spl_start_uboot(void)
	311	{
	312	/* break into full u-boot on 'c' */
	313	if (serial_tstc() && serial_getc() == 'c')
	314	return 1;
	315
	316	#ifdef CONFIG_SPL_ENV_SUPPORT
	317	if (env_get_yesno("boot_os") != 1)
	318	return 1;
	319	#endif
	320	return 0;
	321	}
	322	#endif