[u-boot.git] / cpu / mpc85xx / tsec.h

/*
 *  tsec.h
 *
 *  Driver for the Motorola Triple Speed Ethernet Controller
 *
 *  This software may be used and distributed according to the
 *  terms of the GNU Public License, Version 2, incorporated
 *  herein by reference.
 *
 * (C) Copyright 2003, Motorola, Inc.
 * maintained by Xianghua Xiao ([email protected])
 * author Andy Fleming
 *
 */

#ifndef __TSEC_H
#define __TSEC_H

#include <net.h>
#include <mpc85xx.h>

#define TSEC_BASE_ADDR	(CFG_IMMR + 0x24000)
#define TSEC_MEM_SIZE	0x01000

#define MAC_ADDR_LEN 6

#define TSEC_TIMEOUT 	1000000
#define TOUT_LOOP 	1000000

/* MAC register bits */
#define MACCFG1_SOFT_RESET	0x80000000
#define MACCFG1_RESET_RX_MC	0x00080000
#define MACCFG1_RESET_TX_MC	0x00040000
#define MACCFG1_RESET_RX_FUN	0x00020000
#define	MACCFG1_RESET_TX_FUN	0x00010000
#define MACCFG1_LOOPBACK	0x00000100
#define MACCFG1_RX_FLOW		0x00000020
#define MACCFG1_TX_FLOW		0x00000010
#define MACCFG1_SYNCD_RX_EN	0x00000008
#define MACCFG1_RX_EN		0x00000004
#define MACCFG1_SYNCD_TX_EN	0x00000002
#define MACCFG1_TX_EN		0x00000001

#define MACCFG2_INIT_SETTINGS	0x00007205
#define MACCFG2_FULL_DUPLEX	0x00000001
#define MACCFG2_IF              0x00000300
#define MACCFG2_MII             0x00000100

#define ECNTRL_INIT_SETTINGS	0x00001000
#define ECNTRL_TBI_MODE         0x00000020

#define TBIPA_VALUE		0x1f
#define MIIMCFG_INIT_VALUE	0x00000003
#define MIIMCFG_RESET		0x80000000

#define MIIMIND_BUSY            0x00000001
#define MIIMIND_NOTVALID        0x00000004

#define MIIM_TBICON		0x11
#define MIIM_TBICON_GMII	0x00000010
#define MIIM_TBICON_AN		0x00000100

#define MIIM_CONTROL            0x00
#define MIIM_CONTROL_INIT       0x00001140
#define MIIM_ANEN               0x00001000

#define MIIM_TBI_STATUS		0x1
#define MIIM_TBI_STATUS_AN_DONE 0x00000020

#define MIIM_TBI_ANEX		0x6
#define MIIM_TBI_ANEX_NP	0x00000004
#define MIIM_TBI_ANEX_PRX	0x00000002

#define MIIM_TBI_ANLPBPA	0x5
#define MIIM_TBI_ANLPBPA_HALF	0x00000040
#define MIIM_TBI_ANLPBPA_FULL	0x00000020

#ifdef CONFIG_PHY_CIS8201
#define MIIM_AUX_CONSTAT	0x1c
#define MIIM_AUXCONSTAT_INIT	0x0004
#define MIIM_AUXCONSTAT_DUPLEX	0x0020
#define MIIM_AUXCONSTAT_SPEED   0x0018
#define MIIM_AUXCONSTAT_GBIT    0x0010
#define MIIM_AUXCONSTAT_100     0x0008

#define MIIM_EXT_CON1		0x17
#define MIIM_EXTCON1_INIT	0x0000

#endif

#ifdef CONFIG_PHY_M88E1011
#define MIIM_ANAR		0x04
#define MIIM_ANAR_ADVERTISEMENT	0x01e1

#define MIIM_GBIT_CON		0x09
#define MIIM_GBIT_CON_ADVERT	0x1e00

#define MIIM_PHY_STATUS         0x11
#define MIIM_PHYSTAT_SPEED      0xc000
#define MIIM_PHYSTAT_GBIT       0x8000
#define MIIM_PHYSTAT_100        0x4000
#define MIIM_PHYSTAT_DUPLEX     0x2000
#define MIIM_PHYSTAT_SPDDONE	0x0800
#define MIIM_PHYSTAT_LINK	0x0400
#endif

#define MIIM_READ_COMMAND       0x00000001

#define MRBLR_INIT_SETTINGS	PKTSIZE_ALIGN

#define MINFLR_INIT_SETTINGS	0x00000040

#define DMACTRL_INIT_SETTINGS   0x000000c3
#define DMACTRL_GRS             0x00000010
#define DMACTRL_GTS             0x00000008

#define TSTAT_CLEAR_THALT       0x80000000
#define RSTAT_CLEAR_RHALT       0x00800000

/* Write value to the PHY at phyid to the register at offset, */
/* using the register space defined in regbase.  Note that */
/* miimcfg needs to have the clock speed setup correctly.  This */
/* macro will wait until the write is done before it finishes */
#define write_phy_reg(regbase, phyid, offset, value) do { \
	int timeout=1000000; \
	regbase->miimadd = (phyid << 8) | offset; \
	regbase->miimcon = value; \
	asm("msync"); \
	while((regbase->miimind & MIIMIND_BUSY) && timeout--); \
} while(0)


#define IEVENT_INIT_CLEAR	0xffffffff
#define IEVENT_BABR		0x80000000
#define IEVENT_RXC		0x40000000
#define IEVENT_BSY		0x20000000
#define IEVENT_EBERR		0x10000000
#define IEVENT_MSRO		0x04000000
#define IEVENT_GTSC		0x02000000
#define IEVENT_BABT		0x01000000
#define IEVENT_TXC		0x00800000
#define IEVENT_TXE		0x00400000
#define IEVENT_TXB		0x00200000
#define IEVENT_TXF		0x00100000
#define IEVENT_IE		0x00080000
#define IEVENT_LC		0x00040000
#define IEVENT_CRL		0x00020000
#define IEVENT_XFUN		0x00010000
#define IEVENT_RXB0		0x00008000
#define IEVENT_GRSC		0x00000100
#define IEVENT_RXF0		0x00000080

#define IMASK_INIT_CLEAR	0x00000000
#define IMASK_TXEEN		0x00400000
#define IMASK_TXBEN		0x00200000
#define IMASK_TXFEN             0x00100000
#define IMASK_RXFEN0		0x00000080


/* Default Attribute fields */
#define ATTR_INIT_SETTINGS     0x000000c0
#define ATTRELI_INIT_SETTINGS  0x00000000


/* TxBD status field bits */
#define TXBD_READY		0x8000
#define TXBD_PADCRC		0x4000
#define TXBD_WRAP		0x2000
#define TXBD_INTERRUPT		0x1000
#define TXBD_LAST		0x0800
#define TXBD_CRC		0x0400
#define TXBD_DEF		0x0200
#define TXBD_HUGEFRAME		0x0080
#define TXBD_LATECOLLISION	0x0080
#define TXBD_RETRYLIMIT		0x0040
#define	TXBD_RETRYCOUNTMASK	0x003c
#define TXBD_UNDERRUN		0x0002
#define TXBD_STATS              0x03ff

/* RxBD status field bits */
#define RXBD_EMPTY		0x8000
#define RXBD_RO1		0x4000
#define RXBD_WRAP		0x2000
#define RXBD_INTERRUPT		0x1000
#define RXBD_LAST		0x0800
#define RXBD_FIRST		0x0400
#define RXBD_MISS		0x0100
#define RXBD_BROADCAST		0x0080
#define RXBD_MULTICAST		0x0040
#define RXBD_LARGE		0x0020
#define RXBD_NONOCTET		0x0010
#define RXBD_SHORT		0x0008
#define RXBD_CRCERR		0x0004
#define RXBD_OVERRUN		0x0002
#define RXBD_TRUNCATED		0x0001
#define RXBD_STATS		0x003f

typedef struct txbd8
{
	ushort       status;         /* Status Fields */
	ushort       length;         /* Buffer length */
	uint         bufPtr;         /* Buffer Pointer */
} txbd8_t;

typedef struct rxbd8
{
	ushort       status;         /* Status Fields */
	ushort       length;         /* Buffer Length */
	uint         bufPtr;         /* Buffer Pointer */
} rxbd8_t;

typedef struct rmon_mib
{
	/* Transmit and Receive Counters */
	uint	tr64;		/* Transmit and Receive 64-byte Frame Counter */
	uint	tr127;		/* Transmit and Receive 65-127 byte Frame Counter */
	uint	tr255;		/* Transmit and Receive 128-255 byte Frame Counter */
	uint	tr511;		/* Transmit and Receive 256-511 byte Frame Counter */
	uint	tr1k;		/* Transmit and Receive 512-1023 byte Frame Counter */
	uint	trmax;		/* Transmit and Receive 1024-1518 byte Frame Counter */
	uint	trmgv;		/* Transmit and Receive 1519-1522 byte Good VLAN Frame */
	/* Receive Counters */
	uint	rbyt;		/* Receive Byte Counter */
	uint	rpkt;		/* Receive Packet Counter */
	uint	rfcs;		/* Receive FCS Error Counter */
	uint	rmca;		/* Receive Multicast Packet (Counter) */
	uint	rbca;		/* Receive Broadcast Packet */
	uint	rxcf;		/* Receive Control Frame Packet */
	uint	rxpf;		/* Receive Pause Frame Packet */
	uint	rxuo;		/* Receive Unknown OP Code */
	uint	raln;		/* Receive Alignment Error */
	uint	rflr;		/* Receive Frame Length Error */
	uint	rcde;		/* Receive Code Error */
	uint	rcse;		/* Receive Carrier Sense Error */
	uint	rund;		/* Receive Undersize Packet */
	uint	rovr;		/* Receive Oversize Packet */
	uint	rfrg;		/* Receive Fragments */
	uint	rjbr;		/* Receive Jabber */
	uint	rdrp;		/* Receive Drop */
	/* Transmit Counters */
	uint	tbyt;		/* Transmit Byte Counter */
	uint	tpkt;		/* Transmit Packet */
	uint	tmca;		/* Transmit Multicast Packet */
	uint	tbca;		/* Transmit Broadcast Packet */
	uint	txpf;		/* Transmit Pause Control Frame */
	uint	tdfr;		/* Transmit Deferral Packet */
	uint	tedf;		/* Transmit Excessive Deferral Packet */
	uint	tscl;		/* Transmit Single Collision Packet */
	/* (0x2_n700) */
	uint	tmcl;		/* Transmit Multiple Collision Packet */
	uint	tlcl;		/* Transmit Late Collision Packet */
	uint	txcl;		/* Transmit Excessive Collision Packet */
	uint	tncl;		/* Transmit Total Collision */

	uint	res2;

	uint	tdrp;		/* Transmit Drop Frame */
	uint	tjbr;		/* Transmit Jabber Frame */
	uint	tfcs;		/* Transmit FCS Error */
	uint	txcf;		/* Transmit Control Frame */
	uint	tovr;		/* Transmit Oversize Frame */
	uint	tund;		/* Transmit Undersize Frame */
	uint	tfrg;		/* Transmit Fragments Frame */
	/* General Registers */
	uint	car1;		/* Carry Register One */
	uint	car2;		/* Carry Register Two */
	uint	cam1;		/* Carry Register One Mask */
	uint	cam2;		/* Carry Register Two Mask */
} rmon_mib_t;

typedef struct tsec_hash_regs
{
	uint	iaddr0;		/* Individual Address Register 0 */
	uint	iaddr1;		/* Individual Address Register 1 */
	uint	iaddr2;		/* Individual Address Register 2 */
	uint	iaddr3;		/* Individual Address Register 3 */
	uint	iaddr4;		/* Individual Address Register 4 */
	uint	iaddr5;		/* Individual Address Register 5 */
	uint	iaddr6;		/* Individual Address Register 6 */
	uint	iaddr7;		/* Individual Address Register 7 */
	uint	res1[24];
	uint	gaddr0;		/* Group Address Register 0 */
	uint	gaddr1;		/* Group Address Register 1 */
	uint	gaddr2;		/* Group Address Register 2 */
	uint	gaddr3;		/* Group Address Register 3 */
	uint	gaddr4;		/* Group Address Register 4 */
	uint	gaddr5;		/* Group Address Register 5 */
	uint	gaddr6;		/* Group Address Register 6 */
	uint	gaddr7;		/* Group Address Register 7 */
	uint	res2[24];
} tsec_hash_t;

typedef struct tsec
{
	/* General Control and Status Registers (0x2_n000) */
	uint	res000[4];

	uint	ievent;		/* Interrupt Event */
	uint	imask;		/* Interrupt Mask */
	uint	edis;		/* Error Disabled */
	uint	res01c;
	uint	ecntrl;		/* Ethernet Control */
	uint	minflr;		/* Minimum Frame Length */
	uint	ptv;		/* Pause Time Value */
	uint	dmactrl;	/* DMA Control */
	uint	tbipa;		/* TBI PHY Address */

	uint	res034[3];
	uint	res040[48];

	/* Transmit Control and Status Registers (0x2_n100) */
	uint	tctrl;		/* Transmit Control */
	uint 	tstat;		/* Transmit Status */
	uint	res108;
	uint	tbdlen;		/* Tx BD Data Length */
	uint	res110[5];
	uint	ctbptr;	        /* Current TxBD Pointer */
	uint	res128[23];
	uint	tbptr;		/* TxBD Pointer */
	uint	res188[30];
	/* (0x2_n200) */
	uint        res200;
	uint	tbase;		/* TxBD Base Address */
	uint	res208[42];
	uint	ostbd;		/* Out of Sequence TxBD */
	uint	ostbdp;		/* Out of Sequence Tx Data Buffer Pointer */
	uint        res2b8[18];

	/* Receive Control and Status Registers (0x2_n300) */
	uint	rctrl;		/* Receive Control */
	uint	rstat;		/* Receive Status */
	uint	res308;
	uint	rbdlen;		/* RxBD Data Length */
	uint	res310[4];
	uint        res320;
	uint	crbptr; 	/* Current Receive Buffer Pointer */
	uint	res328[6];
	uint	mrblr;  	/* Maximum Receive Buffer Length */
	uint	res344[16];
	uint	rbptr;   	/* RxBD Pointer */
	uint        res388[30];
	/* (0x2_n400) */
	uint        res400;
	uint	rbase;  	/* RxBD Base Address */
	uint        res408[62];

	/* MAC Registers (0x2_n500) */
	uint	maccfg1;	/* MAC Configuration #1 */
	uint	maccfg2;	/* MAC Configuration #2 */
	uint	ipgifg;		/* Inter Packet Gap/Inter Frame Gap */
	uint	hafdup;		/* Half-duplex */
	uint	maxfrm;		/* Maximum Frame */
	uint	res514;
	uint	res518;

	uint	res51c;

	uint	miimcfg;	/* MII Management: Configuration */
	uint	miimcom;	/* MII Management: Command */
	uint	miimadd;	/* MII Management: Address */
	uint	miimcon;	/* MII Management: Control */
	uint	miimstat;	/* MII Management: Status */
	uint	miimind;	/* MII Management: Indicators */

	uint	res538;

	uint	ifstat;		/* Interface Status */
	uint	macstnaddr1;	/* Station Address, part 1 */
	uint	macstnaddr2;	/* Station Address, part 2 */
	uint	res548[46];

	/* (0x2_n600) */
	uint	res600[32];

	/* RMON MIB Registers (0x2_n680-0x2_n73c) */
	rmon_mib_t	rmon;
	uint	res740[48];

	/* Hash Function Registers (0x2_n800) */
	tsec_hash_t	hash;

	uint        res900[128];

	/* Pattern Registers (0x2_nb00) */
	uint        resb00[62];
	uint        attr;          /* Default Attribute Register */
	uint        attreli;       /* Default Attribute Extract Length and Index */

	/* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */
	uint	resc00[256];
} tsec_t;

#endif /* __TSEC_H */
Commit	Line	Data
42d1f039 WD	1	/*
	2	* tsec.h
	3	*
	4	* Driver for the Motorola Triple Speed Ethernet Controller
	5	*
	6	* This software may be used and distributed according to the
	7	* terms of the GNU Public License, Version 2, incorporated
	8	* herein by reference.
	9	*
	10	* (C) Copyright 2003, Motorola, Inc.
	11	* maintained by Xianghua Xiao ([email protected])
	12	* author Andy Fleming
	13	*
	14	*/
	15
	16	#ifndef __TSEC_H
	17	#define __TSEC_H
	18
	19	#include <net.h>
	20	#include <mpc85xx.h>
	21
	22	#define TSEC_BASE_ADDR (CFG_IMMR + 0x24000)
	23	#define TSEC_MEM_SIZE 0x01000
	24
	25	#define MAC_ADDR_LEN 6
	26
	27	#define TSEC_TIMEOUT 1000000
	28	#define TOUT_LOOP 1000000
	29
	30	/* MAC register bits */
	31	#define MACCFG1_SOFT_RESET 0x80000000
	32	#define MACCFG1_RESET_RX_MC 0x00080000
	33	#define MACCFG1_RESET_TX_MC 0x00040000
	34	#define MACCFG1_RESET_RX_FUN 0x00020000
	35	#define MACCFG1_RESET_TX_FUN 0x00010000
	36	#define MACCFG1_LOOPBACK 0x00000100
	37	#define MACCFG1_RX_FLOW 0x00000020
	38	#define MACCFG1_TX_FLOW 0x00000010
	39	#define MACCFG1_SYNCD_RX_EN 0x00000008
	40	#define MACCFG1_RX_EN 0x00000004
	41	#define MACCFG1_SYNCD_TX_EN 0x00000002
	42	#define MACCFG1_TX_EN 0x00000001
	43
	44	#define MACCFG2_INIT_SETTINGS 0x00007205
	45	#define MACCFG2_FULL_DUPLEX 0x00000001
	46	#define MACCFG2_IF 0x00000300
	47	#define MACCFG2_MII 0x00000100
	48
	49	#define ECNTRL_INIT_SETTINGS 0x00001000
	50	#define ECNTRL_TBI_MODE 0x00000020
	51
	52	#define TBIPA_VALUE 0x1f
	53	#define MIIMCFG_INIT_VALUE 0x00000003
	54	#define MIIMCFG_RESET 0x80000000
	55
	56	#define MIIMIND_BUSY 0x00000001
	57	#define MIIMIND_NOTVALID 0x00000004
	58
	59	#define MIIM_TBICON 0x11
	60	#define MIIM_TBICON_GMII 0x00000010
	61	#define MIIM_TBICON_AN 0x00000100
	62
	63	#define MIIM_CONTROL 0x00
	64	#define MIIM_CONTROL_INIT 0x00001140
65	#define MIIM_ANEN 0x00001000
66
67	#define MIIM_TBI_STATUS 0x1
68	#define MIIM_TBI_STATUS_AN_DONE 0x00000020
69
70	#define MIIM_TBI_ANEX 0x6
71	#define MIIM_TBI_ANEX_NP 0x00000004
72	#define MIIM_TBI_ANEX_PRX 0x00000002
73
74	#define MIIM_TBI_ANLPBPA 0x5
75	#define MIIM_TBI_ANLPBPA_HALF 0x00000040
76	#define MIIM_TBI_ANLPBPA_FULL 0x00000020
77
78	#ifdef CONFIG_PHY_CIS8201
79	#define MIIM_AUX_CONSTAT 0x1c
80	#define MIIM_AUXCONSTAT_INIT 0x0004
81	#define MIIM_AUXCONSTAT_DUPLEX 0x0020
82	#define MIIM_AUXCONSTAT_SPEED 0x0018
83	#define MIIM_AUXCONSTAT_GBIT 0x0010
84	#define MIIM_AUXCONSTAT_100 0x0008
85
86	#define MIIM_EXT_CON1 0x17
87	#define MIIM_EXTCON1_INIT 0x0000
88
89	#endif
90
91	#ifdef CONFIG_PHY_M88E1011
92	#define MIIM_ANAR 0x04
93	#define MIIM_ANAR_ADVERTISEMENT 0x01e1
94
95	#define MIIM_GBIT_CON 0x09
96	#define MIIM_GBIT_CON_ADVERT 0x1e00
97
98	#define MIIM_PHY_STATUS 0x11
99	#define MIIM_PHYSTAT_SPEED 0xc000
100	#define MIIM_PHYSTAT_GBIT 0x8000
101	#define MIIM_PHYSTAT_100 0x4000
102	#define MIIM_PHYSTAT_DUPLEX 0x2000
103	#define MIIM_PHYSTAT_SPDDONE 0x0800
104	#define MIIM_PHYSTAT_LINK 0x0400
105	#endif
106
107	#define MIIM_READ_COMMAND 0x00000001
108
109	#define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN
110
111	#define MINFLR_INIT_SETTINGS 0x00000040
112
113	#define DMACTRL_INIT_SETTINGS 0x000000c3
114	#define DMACTRL_GRS 0x00000010
115	#define DMACTRL_GTS 0x00000008
116
117	#define TSTAT_CLEAR_THALT 0x80000000
118	#define RSTAT_CLEAR_RHALT 0x00800000
119
120	/* Write value to the PHY at phyid to the register at offset, */
121	/* using the register space defined in regbase. Note that */
122	/* miimcfg needs to have the clock speed setup correctly. This */
123	/* macro will wait until the write is done before it finishes */
124	#define write_phy_reg(regbase, phyid, offset, value) do { \
125	int timeout=1000000; \
126	regbase->miimadd = (phyid << 8) \| offset; \
127	regbase->miimcon = value; \
128	asm("msync"); \
129	while((regbase->miimind & MIIMIND_BUSY) && timeout--); \
130	} while(0)
131
132
133	#define IEVENT_INIT_CLEAR 0xffffffff
134	#define IEVENT_BABR 0x80000000
135	#define IEVENT_RXC 0x40000000
136	#define IEVENT_BSY 0x20000000
137	#define IEVENT_EBERR 0x10000000
138	#define IEVENT_MSRO 0x04000000
139	#define IEVENT_GTSC 0x02000000
140	#define IEVENT_BABT 0x01000000
141	#define IEVENT_TXC 0x00800000
142	#define IEVENT_TXE 0x00400000
143	#define IEVENT_TXB 0x00200000
144	#define IEVENT_TXF 0x00100000
145	#define IEVENT_IE 0x00080000
146	#define IEVENT_LC 0x00040000
147	#define IEVENT_CRL 0x00020000
148	#define IEVENT_XFUN 0x00010000
149	#define IEVENT_RXB0 0x00008000
150	#define IEVENT_GRSC 0x00000100
151	#define IEVENT_RXF0 0x00000080
152
153	#define IMASK_INIT_CLEAR 0x00000000
154	#define IMASK_TXEEN 0x00400000
155	#define IMASK_TXBEN 0x00200000
156	#define IMASK_TXFEN 0x00100000
157	#define IMASK_RXFEN0 0x00000080
158
159
160	/* Default Attribute fields */
161	#define ATTR_INIT_SETTINGS 0x000000c0
162	#define ATTRELI_INIT_SETTINGS 0x00000000
163
164
165	/* TxBD status field bits */
166	#define TXBD_READY 0x8000
167	#define TXBD_PADCRC 0x4000
168	#define TXBD_WRAP 0x2000
169	#define TXBD_INTERRUPT 0x1000
170	#define TXBD_LAST 0x0800
171	#define TXBD_CRC 0x0400
172	#define TXBD_DEF 0x0200
173	#define TXBD_HUGEFRAME 0x0080
174	#define TXBD_LATECOLLISION 0x0080
175	#define TXBD_RETRYLIMIT 0x0040
176	#define TXBD_RETRYCOUNTMASK 0x003c
177	#define TXBD_UNDERRUN 0x0002
178	#define TXBD_STATS 0x03ff
179
180	/* RxBD status field bits */
181	#define RXBD_EMPTY 0x8000
182	#define RXBD_RO1 0x4000
183	#define RXBD_WRAP 0x2000
184	#define RXBD_INTERRUPT 0x1000
185	#define RXBD_LAST 0x0800
186	#define RXBD_FIRST 0x0400
187	#define RXBD_MISS 0x0100
188	#define RXBD_BROADCAST 0x0080
189	#define RXBD_MULTICAST 0x0040
190	#define RXBD_LARGE 0x0020
191	#define RXBD_NONOCTET 0x0010
192	#define RXBD_SHORT 0x0008
193	#define RXBD_CRCERR 0x0004
194	#define RXBD_OVERRUN 0x0002
195	#define RXBD_TRUNCATED 0x0001
196	#define RXBD_STATS 0x003f
197
198	typedef struct txbd8
199	{
200	ushort status; /* Status Fields */
201	ushort length; /* Buffer length */
202	uint bufPtr; /* Buffer Pointer */
203	} txbd8_t;
204
205	typedef struct rxbd8
206	{
207	ushort status; /* Status Fields */
208	ushort length; /* Buffer Length */
209	uint bufPtr; /* Buffer Pointer */
210	} rxbd8_t;
211
212	typedef struct rmon_mib
213	{
214	/* Transmit and Receive Counters */
215	uint tr64; /* Transmit and Receive 64-byte Frame Counter */
216	uint tr127; /* Transmit and Receive 65-127 byte Frame Counter */
217	uint tr255; /* Transmit and Receive 128-255 byte Frame Counter */
218	uint tr511; /* Transmit and Receive 256-511 byte Frame Counter */
219	uint tr1k; /* Transmit and Receive 512-1023 byte Frame Counter */
220	uint trmax; /* Transmit and Receive 1024-1518 byte Frame Counter */
221	uint trmgv; /* Transmit and Receive 1519-1522 byte Good VLAN Frame */
222	/* Receive Counters */
223	uint rbyt; /* Receive Byte Counter */
224	uint rpkt; /* Receive Packet Counter */
225	uint rfcs; /* Receive FCS Error Counter */
226	uint rmca; /* Receive Multicast Packet (Counter) */
227	uint rbca; /* Receive Broadcast Packet */
228	uint rxcf; /* Receive Control Frame Packet */
229	uint rxpf; /* Receive Pause Frame Packet */
230	uint rxuo; /* Receive Unknown OP Code */
231	uint raln; /* Receive Alignment Error */
232	uint rflr; /* Receive Frame Length Error */
233	uint rcde; /* Receive Code Error */
234	uint rcse; /* Receive Carrier Sense Error */
235	uint rund; /* Receive Undersize Packet */
236	uint rovr; /* Receive Oversize Packet */
237	uint rfrg; /* Receive Fragments */
238	uint rjbr; /* Receive Jabber */
239	uint rdrp; /* Receive Drop */
240	/* Transmit Counters */
241	uint tbyt; /* Transmit Byte Counter */
242	uint tpkt; /* Transmit Packet */
243	uint tmca; /* Transmit Multicast Packet */
244	uint tbca; /* Transmit Broadcast Packet */
245	uint txpf; /* Transmit Pause Control Frame */
246	uint tdfr; /* Transmit Deferral Packet */
247	uint tedf; /* Transmit Excessive Deferral Packet */
248	uint tscl; /* Transmit Single Collision Packet */
249	/* (0x2_n700) */
250	uint tmcl; /* Transmit Multiple Collision Packet */
251	uint tlcl; /* Transmit Late Collision Packet */
252	uint txcl; /* Transmit Excessive Collision Packet */
253	uint tncl; /* Transmit Total Collision */
254
255	uint res2;
256
257	uint tdrp; /* Transmit Drop Frame */
258	uint tjbr; /* Transmit Jabber Frame */
259	uint tfcs; /* Transmit FCS Error */
260	uint txcf; /* Transmit Control Frame */
261	uint tovr; /* Transmit Oversize Frame */
262	uint tund; /* Transmit Undersize Frame */
263	uint tfrg; /* Transmit Fragments Frame */
264	/* General Registers */
265	uint car1; /* Carry Register One */
266	uint car2; /* Carry Register Two */
267	uint cam1; /* Carry Register One Mask */
268	uint cam2; /* Carry Register Two Mask */
269	} rmon_mib_t;
270
271	typedef struct tsec_hash_regs
272	{
273	uint iaddr0; /* Individual Address Register 0 */
274	uint iaddr1; /* Individual Address Register 1 */
275	uint iaddr2; /* Individual Address Register 2 */
276	uint iaddr3; /* Individual Address Register 3 */
277	uint iaddr4; /* Individual Address Register 4 */
278	uint iaddr5; /* Individual Address Register 5 */
279	uint iaddr6; /* Individual Address Register 6 */
280	uint iaddr7; /* Individual Address Register 7 */
281	uint res1[24];
282	uint gaddr0; /* Group Address Register 0 */
283	uint gaddr1; /* Group Address Register 1 */
284	uint gaddr2; /* Group Address Register 2 */
285	uint gaddr3; /* Group Address Register 3 */
286	uint gaddr4; /* Group Address Register 4 */
287	uint gaddr5; /* Group Address Register 5 */
288	uint gaddr6; /* Group Address Register 6 */
289	uint gaddr7; /* Group Address Register 7 */
290	uint res2[24];
291	} tsec_hash_t;
292
293	typedef struct tsec
294	{
295	/* General Control and Status Registers (0x2_n000) */
296	uint res000[4];
297
298	uint ievent; /* Interrupt Event */
299	uint imask; /* Interrupt Mask */
300	uint edis; /* Error Disabled */
301	uint res01c;
302	uint ecntrl; /* Ethernet Control */
303	uint minflr; /* Minimum Frame Length */
304	uint ptv; /* Pause Time Value */
305	uint dmactrl; /* DMA Control */
306	uint tbipa; /* TBI PHY Address */
307
308	uint res034[3];
309	uint res040[48];
310
311	/* Transmit Control and Status Registers (0x2_n100) */
312	uint tctrl; /* Transmit Control */
313	uint tstat; /* Transmit Status */
314	uint res108;
315	uint tbdlen; /* Tx BD Data Length */
316	uint res110[5];
317	uint ctbptr; /* Current TxBD Pointer */
318	uint res128[23];
319	uint tbptr; /* TxBD Pointer */
320	uint res188[30];
321	/* (0x2_n200) */
322	uint res200;
323	uint tbase; /* TxBD Base Address */
324	uint res208[42];
325	uint ostbd; /* Out of Sequence TxBD */
326	uint ostbdp; /* Out of Sequence Tx Data Buffer Pointer */
327	uint res2b8[18];
328
329	/* Receive Control and Status Registers (0x2_n300) */
330	uint rctrl; /* Receive Control */
331	uint rstat; /* Receive Status */
332	uint res308;
333	uint rbdlen; /* RxBD Data Length */
334	uint res310[4];
335	uint res320;
336	uint crbptr; /* Current Receive Buffer Pointer */
337	uint res328[6];
338	uint mrblr; /* Maximum Receive Buffer Length */
339	uint res344[16];
340	uint rbptr; /* RxBD Pointer */
341	uint res388[30];
342	/* (0x2_n400) */
343	uint res400;
344	uint rbase; /* RxBD Base Address */
345	uint res408[62];
346
347	/* MAC Registers (0x2_n500) */
348	uint maccfg1; /* MAC Configuration #1 */
349	uint maccfg2; /* MAC Configuration #2 */
350	uint ipgifg; /* Inter Packet Gap/Inter Frame Gap */
351	uint hafdup; /* Half-duplex */
352	uint maxfrm; /* Maximum Frame */
353	uint res514;
354	uint res518;
355
356	uint res51c;
357
358	uint miimcfg; /* MII Management: Configuration */
359	uint miimcom; /* MII Management: Command */
360	uint miimadd; /* MII Management: Address */
361	uint miimcon; /* MII Management: Control */
362	uint miimstat; /* MII Management: Status */
363	uint miimind; /* MII Management: Indicators */
364
365	uint res538;
366
367	uint ifstat; /* Interface Status */
368	uint macstnaddr1; /* Station Address, part 1 */
369	uint macstnaddr2; /* Station Address, part 2 */
370	uint res548[46];
371
372	/* (0x2_n600) */
373	uint res600[32];
374
375	/* RMON MIB Registers (0x2_n680-0x2_n73c) */
376	rmon_mib_t rmon;
377	uint res740[48];
378
379	/* Hash Function Registers (0x2_n800) */
380	tsec_hash_t hash;
381
382	uint res900[128];
383
384	/* Pattern Registers (0x2_nb00) */
385	uint resb00[62];
386	uint attr; /* Default Attribute Register */
387	uint attreli; /* Default Attribute Extract Length and Index */
388
389	/* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */
390	uint resc00[256];
391	} tsec_t;
392
393	#endif /* __TSEC_H */