[u-boot.git] / drivers / spi / rk_spi.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * spi driver for rockchip
 *
 * (C) 2019 Theobroma Systems Design und Consulting GmbH
 *
 * (C) Copyright 2015 Google, Inc
 *
 * (C) Copyright 2008-2013 Rockchip Electronics
 * Peter, Software Engineering, <[email protected]>.
 */

#include <common.h>
#include <clk.h>
#include <dm.h>
#include <dt-structs.h>
#include <errno.h>
#include <log.h>
#include <spi.h>
#include <time.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/periph.h>
#include <dm/pinctrl.h>
#include "rk_spi.h"

/* Change to 1 to output registers at the start of each transaction */
#define DEBUG_RK_SPI	0

/*
 * ctrlr1 is 16-bits, so we should support lengths of 0xffff + 1. However,
 * the controller seems to hang when given 0x10000, so stick with this for now.
 */
#define ROCKCHIP_SPI_MAX_TRANLEN		0xffff

struct rockchip_spi_params {
	/* RXFIFO overruns and TXFIFO underruns stop the master clock */
	bool master_manages_fifo;
};

struct rockchip_spi_platdata {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
	struct dtd_rockchip_rk3288_spi of_plat;
#endif
	s32 frequency;		/* Default clock frequency, -1 for none */
	fdt_addr_t base;
	uint deactivate_delay_us;	/* Delay to wait after deactivate */
	uint activate_delay_us;		/* Delay to wait after activate */
};

struct rockchip_spi_priv {
	struct rockchip_spi *regs;
	struct clk clk;
	unsigned int max_freq;
	unsigned int mode;
	ulong last_transaction_us;	/* Time of last transaction end */
	unsigned int speed_hz;
	unsigned int last_speed_hz;
	uint input_rate;
};

#define SPI_FIFO_DEPTH		32

static void rkspi_dump_regs(struct rockchip_spi *regs)
{
	debug("ctrl0: \t\t0x%08x\n", readl(&regs->ctrlr0));
	debug("ctrl1: \t\t0x%08x\n", readl(&regs->ctrlr1));
	debug("ssienr: \t\t0x%08x\n", readl(&regs->enr));
	debug("ser: \t\t0x%08x\n", readl(&regs->ser));
	debug("baudr: \t\t0x%08x\n", readl(&regs->baudr));
	debug("txftlr: \t\t0x%08x\n", readl(&regs->txftlr));
	debug("rxftlr: \t\t0x%08x\n", readl(&regs->rxftlr));
	debug("txflr: \t\t0x%08x\n", readl(&regs->txflr));
	debug("rxflr: \t\t0x%08x\n", readl(&regs->rxflr));
	debug("sr: \t\t0x%08x\n", readl(&regs->sr));
	debug("imr: \t\t0x%08x\n", readl(&regs->imr));
	debug("isr: \t\t0x%08x\n", readl(&regs->isr));
	debug("dmacr: \t\t0x%08x\n", readl(&regs->dmacr));
	debug("dmatdlr: \t0x%08x\n", readl(&regs->dmatdlr));
	debug("dmardlr: \t0x%08x\n", readl(&regs->dmardlr));
}

static void rkspi_enable_chip(struct rockchip_spi *regs, bool enable)
{
	writel(enable ? 1 : 0, &regs->enr);
}

static void rkspi_set_clk(struct rockchip_spi_priv *priv, uint speed)
{
	/*
	 * We should try not to exceed the speed requested by the caller:
	 * when selecting a divider, we need to make sure we round up.
	 */
	uint clk_div = DIV_ROUND_UP(priv->input_rate, speed);

	/* The baudrate register (BAUDR) is defined as a 32bit register where
	 * the upper 16bit are reserved and having 'Fsclk_out' in the lower
	 * 16bits with 'Fsclk_out' defined as follows:
	 *
	 *   Fsclk_out = Fspi_clk/ SCKDV
	 *   Where SCKDV is any even value between 2 and 65534.
	 */
	if (clk_div > 0xfffe) {
		clk_div = 0xfffe;
		debug("%s: can't divide down to %d Hz (actual will be %d Hz)\n",
		      __func__, speed, priv->input_rate / clk_div);
	}

	/* Round up to the next even 16bit number */
	clk_div = (clk_div + 1) & 0xfffe;

	debug("spi speed %u, div %u\n", speed, clk_div);

	clrsetbits_le32(&priv->regs->baudr, 0xffff, clk_div);
	priv->last_speed_hz = speed;
}

static int rkspi_wait_till_not_busy(struct rockchip_spi *regs)
{
	unsigned long start;

	start = get_timer(0);
	while (readl(&regs->sr) & SR_BUSY) {
		if (get_timer(start) > ROCKCHIP_SPI_TIMEOUT_MS) {
			debug("RK SPI: Status keeps busy for 1000us after a read/write!\n");
			return -ETIMEDOUT;
		}
	}

	return 0;
}

static void spi_cs_activate(struct udevice *dev, uint cs)
{
	struct udevice *bus = dev->parent;
	struct rockchip_spi_platdata *plat = bus->platdata;
	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	struct rockchip_spi *regs = priv->regs;

	/* If it's too soon to do another transaction, wait */
	if (plat->deactivate_delay_us && priv->last_transaction_us) {
		ulong delay_us;		/* The delay completed so far */
		delay_us = timer_get_us() - priv->last_transaction_us;
		if (delay_us < plat->deactivate_delay_us) {
			ulong additional_delay_us =
				plat->deactivate_delay_us - delay_us;
			debug("%s: delaying by %ld us\n",
			      __func__, additional_delay_us);
			udelay(additional_delay_us);
		}
	}

	debug("activate cs%u\n", cs);
	writel(1 << cs, &regs->ser);
	if (plat->activate_delay_us)
		udelay(plat->activate_delay_us);
}

static void spi_cs_deactivate(struct udevice *dev, uint cs)
{
	struct udevice *bus = dev->parent;
	struct rockchip_spi_platdata *plat = bus->platdata;
	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	struct rockchip_spi *regs = priv->regs;

	debug("deactivate cs%u\n", cs);
	writel(0, &regs->ser);

	/* Remember time of this transaction so we can honour the bus delay */
	if (plat->deactivate_delay_us)
		priv->last_transaction_us = timer_get_us();
}

#if CONFIG_IS_ENABLED(OF_PLATDATA)
static int conv_of_platdata(struct udevice *dev)
{
	struct rockchip_spi_platdata *plat = dev->platdata;
	struct dtd_rockchip_rk3288_spi *dtplat = &plat->of_plat;
	struct rockchip_spi_priv *priv = dev_get_priv(dev);
	int ret;

	plat->base = dtplat->reg[0];
	plat->frequency = 20000000;
	ret = clk_get_by_driver_info(dev, dtplat->clocks, &priv->clk);
	if (ret < 0)
		return ret;
	dev->req_seq = 0;

	return 0;
}
#endif

static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
	struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	int ret;

	plat->base = dev_read_addr(bus);

	ret = clk_get_by_index(bus, 0, &priv->clk);
	if (ret < 0) {
		debug("%s: Could not get clock for %s: %d\n", __func__,
		      bus->name, ret);
		return ret;
	}

	plat->frequency =
		dev_read_u32_default(bus, "spi-max-frequency", 50000000);
	plat->deactivate_delay_us =
		dev_read_u32_default(bus, "spi-deactivate-delay", 0);
	plat->activate_delay_us =
		dev_read_u32_default(bus, "spi-activate-delay", 0);

	debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n",
	      __func__, (uint)plat->base, plat->frequency,
	      plat->deactivate_delay_us);
#endif

	return 0;
}

static int rockchip_spi_calc_modclk(ulong max_freq)
{
	/*
	 * While this is not strictly correct for the RK3368, as the
	 * GPLL will be 576MHz, things will still work, as the
	 * clk_set_rate(...) implementation in our clock-driver will
	 * chose the next closest rate not exceeding what we request
	 * based on the output of this function.
	 */

	unsigned div;
	const unsigned long gpll_hz = 594000000UL;

	/*
	 * We need to find an input clock that provides at least twice
	 * the maximum frequency and can be generated from the assumed
	 * speed of GPLL (594MHz) using an integer divider.
	 *
	 * To give us more achievable bitrates at higher speeds (these
	 * are generated by dividing by an even 16-bit integer from
	 * this frequency), we try to have an input frequency of at
	 * least 4x our max_freq.
	 */

	div = DIV_ROUND_UP(gpll_hz, max_freq * 4);
	return gpll_hz / div;
}

static int rockchip_spi_probe(struct udevice *bus)
{
	struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	int ret;

	debug("%s: probe\n", __func__);
#if CONFIG_IS_ENABLED(OF_PLATDATA)
	ret = conv_of_platdata(bus);
	if (ret)
		return ret;
#endif
	priv->regs = (struct rockchip_spi *)plat->base;

	priv->last_transaction_us = timer_get_us();
	priv->max_freq = plat->frequency;

	/* Clamp the value from the DTS against any hardware limits */
	if (priv->max_freq > ROCKCHIP_SPI_MAX_RATE)
		priv->max_freq = ROCKCHIP_SPI_MAX_RATE;

	/* Find a module-input clock that fits with the max_freq setting */
	ret = clk_set_rate(&priv->clk,
			   rockchip_spi_calc_modclk(priv->max_freq));
	if (ret < 0) {
		debug("%s: Failed to set clock: %d\n", __func__, ret);
		return ret;
	}
	priv->input_rate = ret;
	debug("%s: rate = %u\n", __func__, priv->input_rate);

	return 0;
}

static int rockchip_spi_claim_bus(struct udevice *dev)
{
	struct udevice *bus = dev->parent;
	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	struct rockchip_spi *regs = priv->regs;
	uint ctrlr0;

	/* Disable the SPI hardware */
	rkspi_enable_chip(regs, false);

	if (priv->speed_hz != priv->last_speed_hz)
		rkspi_set_clk(priv, priv->speed_hz);

	/* Operation Mode */
	ctrlr0 = OMOD_MASTER << OMOD_SHIFT;

	/* Data Frame Size */
	ctrlr0 |= DFS_8BIT << DFS_SHIFT;

	/* set SPI mode 0..3 */
	if (priv->mode & SPI_CPOL)
		ctrlr0 |= SCOL_HIGH << SCOL_SHIFT;
	if (priv->mode & SPI_CPHA)
		ctrlr0 |= SCPH_TOGSTA << SCPH_SHIFT;

	/* Chip Select Mode */
	ctrlr0 |= CSM_KEEP << CSM_SHIFT;

	/* SSN to Sclk_out delay */
	ctrlr0 |= SSN_DELAY_ONE << SSN_DELAY_SHIFT;

	/* Serial Endian Mode */
	ctrlr0 |= SEM_LITTLE << SEM_SHIFT;

	/* First Bit Mode */
	ctrlr0 |= FBM_MSB << FBM_SHIFT;

	/* Byte and Halfword Transform */
	ctrlr0 |= HALF_WORD_OFF << HALF_WORD_TX_SHIFT;

	/* Rxd Sample Delay */
	ctrlr0 |= 0 << RXDSD_SHIFT;

	/* Frame Format */
	ctrlr0 |= FRF_SPI << FRF_SHIFT;

	/* Tx and Rx mode */
	ctrlr0 |= TMOD_TR << TMOD_SHIFT;

	writel(ctrlr0, &regs->ctrlr0);

	return 0;
}

static int rockchip_spi_release_bus(struct udevice *dev)
{
	struct udevice *bus = dev->parent;
	struct rockchip_spi_priv *priv = dev_get_priv(bus);

	rkspi_enable_chip(priv->regs, false);

	return 0;
}

static inline int rockchip_spi_16bit_reader(struct udevice *dev,
					    u8 **din, int *len)
{
	struct udevice *bus = dev->parent;
	const struct rockchip_spi_params * const data =
		(void *)dev_get_driver_data(bus);
	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	struct rockchip_spi *regs = priv->regs;
	const u32 saved_ctrlr0 = readl(&regs->ctrlr0);
#if defined(DEBUG)
	u32 statistics_rxlevels[33] = { };
#endif
	u32 frames = *len / 2;
	u8 *in = (u8 *)(*din);
	u32 max_chunk_size = SPI_FIFO_DEPTH;

	if (!frames)
		return 0;

	/*
	 * If we know that the hardware will manage RXFIFO overruns
	 * (i.e. stop the SPI clock until there's space in the FIFO),
	 * we the allow largest possible chunk size that can be
	 * represented in CTRLR1.
	 */
	if (data && data->master_manages_fifo)
		max_chunk_size = ROCKCHIP_SPI_MAX_TRANLEN;

	// rockchip_spi_configure(dev, mode, size)
	rkspi_enable_chip(regs, false);
	clrsetbits_le32(&regs->ctrlr0,
			TMOD_MASK << TMOD_SHIFT,
			TMOD_RO << TMOD_SHIFT);
	/* 16bit data frame size */
	clrsetbits_le32(&regs->ctrlr0, DFS_MASK, DFS_16BIT);

	/* Update caller's context */
	const u32 bytes_to_process = 2 * frames;
	*din += bytes_to_process;
	*len -= bytes_to_process;

	/* Process our frames */
	while (frames) {
		u32 chunk_size = min(frames, max_chunk_size);

		frames -= chunk_size;

		writew(chunk_size - 1, &regs->ctrlr1);
		rkspi_enable_chip(regs, true);

		do {
			u32 rx_level = readw(&regs->rxflr);
#if defined(DEBUG)
			statistics_rxlevels[rx_level]++;
#endif
			chunk_size -= rx_level;
			while (rx_level--) {
				u16 val = readw(regs->rxdr);
				*in++ = val & 0xff;
				*in++ = val >> 8;
			}
		} while (chunk_size);

		rkspi_enable_chip(regs, false);
	}

#if defined(DEBUG)
	debug("%s: observed rx_level during processing:\n", __func__);
	for (int i = 0; i <= 32; ++i)
		if (statistics_rxlevels[i])
			debug("\t%2d: %d\n", i, statistics_rxlevels[i]);
#endif
	/* Restore the original transfer setup and return error-free. */
	writel(saved_ctrlr0, &regs->ctrlr0);
	return 0;
}

static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen,
			   const void *dout, void *din, unsigned long flags)
{
	struct udevice *bus = dev->parent;
	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	struct rockchip_spi *regs = priv->regs;
	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
	int len = bitlen >> 3;
	const u8 *out = dout;
	u8 *in = din;
	int toread, towrite;
	int ret = 0;

	debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din,
	      len, flags);
	if (DEBUG_RK_SPI)
		rkspi_dump_regs(regs);

	/* Assert CS before transfer */
	if (flags & SPI_XFER_BEGIN)
		spi_cs_activate(dev, slave_plat->cs);

	/*
	 * To ensure fast loading of firmware images (e.g. full U-Boot
	 * stage, ATF, Linux kernel) from SPI flash, we optimise the
	 * case of read-only transfers by using the full 16bits of each
	 * FIFO element.
	 */
	if (!out)
		ret = rockchip_spi_16bit_reader(dev, &in, &len);

	/* This is the original 8bit reader/writer code */
	while (len > 0) {
		int todo = min(len, ROCKCHIP_SPI_MAX_TRANLEN);

		rkspi_enable_chip(regs, false);
		writel(todo - 1, &regs->ctrlr1);
		rkspi_enable_chip(regs, true);

		toread = todo;
		towrite = todo;
		while (toread || towrite) {
			u32 status = readl(&regs->sr);

			if (towrite && !(status & SR_TF_FULL)) {
				writel(out ? *out++ : 0, regs->txdr);
				towrite--;
			}
			if (toread && !(status & SR_RF_EMPT)) {
				u32 byte = readl(regs->rxdr);

				if (in)
					*in++ = byte;
				toread--;
			}
		}

		/*
		 * In case that there's a transmit-component, we need to wait
		 * until the control goes idle before we can disable the SPI
		 * control logic (as this will implictly flush the FIFOs).
		 */
		if (out) {
			ret = rkspi_wait_till_not_busy(regs);
			if (ret)
				break;
		}

		len -= todo;
	}

	/* Deassert CS after transfer */
	if (flags & SPI_XFER_END)
		spi_cs_deactivate(dev, slave_plat->cs);

	rkspi_enable_chip(regs, false);

	return ret;
}

static int rockchip_spi_set_speed(struct udevice *bus, uint speed)
{
	struct rockchip_spi_priv *priv = dev_get_priv(bus);

	/* Clamp to the maximum frequency specified in the DTS */
	if (speed > priv->max_freq)
		speed = priv->max_freq;

	priv->speed_hz = speed;

	return 0;
}

static int rockchip_spi_set_mode(struct udevice *bus, uint mode)
{
	struct rockchip_spi_priv *priv = dev_get_priv(bus);

	priv->mode = mode;

	return 0;
}

static const struct dm_spi_ops rockchip_spi_ops = {
	.claim_bus	= rockchip_spi_claim_bus,
	.release_bus	= rockchip_spi_release_bus,
	.xfer		= rockchip_spi_xfer,
	.set_speed	= rockchip_spi_set_speed,
	.set_mode	= rockchip_spi_set_mode,
	/*
	 * cs_info is not needed, since we require all chip selects to be
	 * in the device tree explicitly
	 */
};

const  struct rockchip_spi_params rk3399_spi_params = {
	.master_manages_fifo = true,
};

static const struct udevice_id rockchip_spi_ids[] = {
	{ .compatible = "rockchip,rk3066-spi" },
	{ .compatible = "rockchip,rk3288-spi" },
	{ .compatible = "rockchip,rk3328-spi" },
	{ .compatible = "rockchip,rk3368-spi",
	  .data = (ulong)&rk3399_spi_params },
	{ .compatible = "rockchip,rk3399-spi",
	  .data = (ulong)&rk3399_spi_params },
	{ }
};

U_BOOT_DRIVER(rockchip_rk3288_spi) = {
	.name	= "rockchip_rk3288_spi",
	.id	= UCLASS_SPI,
	.of_match = rockchip_spi_ids,
	.ops	= &rockchip_spi_ops,
	.ofdata_to_platdata = rockchip_spi_ofdata_to_platdata,
	.platdata_auto	= sizeof(struct rockchip_spi_platdata),
	.priv_auto	= sizeof(struct rockchip_spi_priv),
	.probe	= rockchip_spi_probe,
};

U_BOOT_DRIVER_ALIAS(rockchip_rk3288_spi, rockchip_rk3368_spi)
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
1b2fd5bf SG	2	/*
	3	* spi driver for rockchip
	4	*
8aa6c921 PT	5	* (C) 2019 Theobroma Systems Design und Consulting GmbH
8aa6c921 PT	6	*
1b2fd5bf SG	7	* (C) Copyright 2015 Google, Inc
	8	*
	9	* (C) Copyright 2008-2013 Rockchip Electronics
	10	* Peter, Software Engineering, <[email protected]>.
1b2fd5bf SG	11	*/
	12
	13	#include <common.h>
	14	#include <clk.h>
	15	#include <dm.h>
6e019c4f	16	#include <dt-structs.h>
1b2fd5bf	17	#include <errno.h>
f7ae49fc	18	#include <log.h>
1b2fd5bf	19	#include <spi.h>
1045315d	20	#include <time.h>
c05ed00a	21	#include <linux/delay.h>
1221ce45	22	#include <linux/errno.h>
1b2fd5bf	23	#include <asm/io.h>
15f09a1a KY	24	#include <asm/arch-rockchip/clock.h>
15f09a1a KY	25	#include <asm/arch-rockchip/periph.h>
1b2fd5bf SG	26	#include <dm/pinctrl.h>
	27	#include "rk_spi.h"
	28
1b2fd5bf SG	29	/* Change to 1 to output registers at the start of each transaction */
	30	#define DEBUG_RK_SPI 0
	31
dbbdc81c JT	32	/*
	33	* ctrlr1 is 16-bits, so we should support lengths of 0xffff + 1. However,
	34	* the controller seems to hang when given 0x10000, so stick with this for now.
	35	*/
	36	#define ROCKCHIP_SPI_MAX_TRANLEN 0xffff
	37
51a644a1 PT	38	struct rockchip_spi_params {
	39	/* RXFIFO overruns and TXFIFO underruns stop the master clock */
	40	bool master_manages_fifo;
	41	};
	42
1b2fd5bf	43	struct rockchip_spi_platdata {
6e019c4f SG	44	#if CONFIG_IS_ENABLED(OF_PLATDATA)
	45	struct dtd_rockchip_rk3288_spi of_plat;
	46	#endif
1b2fd5bf SG	47	s32 frequency; /* Default clock frequency, -1 for none */
	48	fdt_addr_t base;
	49	uint deactivate_delay_us; /* Delay to wait after deactivate */
183a3a0f	50	uint activate_delay_us; /* Delay to wait after activate */
1b2fd5bf SG	51	};
	52
	53	struct rockchip_spi_priv {
	54	struct rockchip_spi *regs;
135aa950	55	struct clk clk;
1b2fd5bf SG	56	unsigned int max_freq;
1b2fd5bf SG	57	unsigned int mode;
1b2fd5bf	58	ulong last_transaction_us; /* Time of last transaction end */
1b2fd5bf	59	unsigned int speed_hz;
28a943c1	60	unsigned int last_speed_hz;
1b2fd5bf SG	61	uint input_rate;
	62	};
	63
	64	#define SPI_FIFO_DEPTH 32
	65
	66	static void rkspi_dump_regs(struct rockchip_spi *regs)
	67	{
	68	debug("ctrl0: \t\t0x%08x\n", readl(&regs->ctrlr0));
	69	debug("ctrl1: \t\t0x%08x\n", readl(&regs->ctrlr1));
	70	debug("ssienr: \t\t0x%08x\n", readl(&regs->enr));
	71	debug("ser: \t\t0x%08x\n", readl(&regs->ser));
	72	debug("baudr: \t\t0x%08x\n", readl(&regs->baudr));
	73	debug("txftlr: \t\t0x%08x\n", readl(&regs->txftlr));
	74	debug("rxftlr: \t\t0x%08x\n", readl(&regs->rxftlr));
	75	debug("txflr: \t\t0x%08x\n", readl(&regs->txflr));
	76	debug("rxflr: \t\t0x%08x\n", readl(&regs->rxflr));
	77	debug("sr: \t\t0x%08x\n", readl(&regs->sr));
	78	debug("imr: \t\t0x%08x\n", readl(&regs->imr));
	79	debug("isr: \t\t0x%08x\n", readl(&regs->isr));
	80	debug("dmacr: \t\t0x%08x\n", readl(&regs->dmacr));
	81	debug("dmatdlr: \t0x%08x\n", readl(&regs->dmatdlr));
	82	debug("dmardlr: \t0x%08x\n", readl(&regs->dmardlr));
	83	}
	84
	85	static void rkspi_enable_chip(struct rockchip_spi *regs, bool enable)
	86	{
	87	writel(enable ? 1 : 0, &regs->enr);
	88	}
	89
	90	static void rkspi_set_clk(struct rockchip_spi_priv *priv, uint speed)
	91	{
9fc354e2 PT	92	/*
	93	* We should try not to exceed the speed requested by the caller:
	94	* when selecting a divider, we need to make sure we round up.
	95	*/
	96	uint clk_div = DIV_ROUND_UP(priv->input_rate, speed);
	97
	98	/* The baudrate register (BAUDR) is defined as a 32bit register where
	99	* the upper 16bit are reserved and having 'Fsclk_out' in the lower
	100	* 16bits with 'Fsclk_out' defined as follows:
	101	*
	102	* Fsclk_out = Fspi_clk/ SCKDV
	103	* Where SCKDV is any even value between 2 and 65534.
	104	*/
	105	if (clk_div > 0xfffe) {
	106	clk_div = 0xfffe;
11f12c17	107	debug("%s: can't divide down to %d Hz (actual will be %d Hz)\n",
9fc354e2 PT	108	__func__, speed, priv->input_rate / clk_div);
	109	}
	110
	111	/* Round up to the next even 16bit number */
	112	clk_div = (clk_div + 1) & 0xfffe;
1b2fd5bf	113
1b2fd5bf SG	114	debug("spi speed %u, div %u\n", speed, clk_div);
1b2fd5bf SG	115
9fc354e2	116	clrsetbits_le32(&priv->regs->baudr, 0xffff, clk_div);
28a943c1	117	priv->last_speed_hz = speed;
1b2fd5bf SG	118	}
	119
	120	static int rkspi_wait_till_not_busy(struct rockchip_spi *regs)
	121	{
	122	unsigned long start;
	123
	124	start = get_timer(0);
	125	while (readl(&regs->sr) & SR_BUSY) {
	126	if (get_timer(start) > ROCKCHIP_SPI_TIMEOUT_MS) {
	127	debug("RK SPI: Status keeps busy for 1000us after a read/write!\n");
	128	return -ETIMEDOUT;
	129	}
	130	}
	131
	132	return 0;
	133	}
	134
183a3a0f	135	static void spi_cs_activate(struct udevice *dev, uint cs)
1b2fd5bf	136	{
183a3a0f SG	137	struct udevice *bus = dev->parent;
	138	struct rockchip_spi_platdata *plat = bus->platdata;
	139	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	140	struct rockchip_spi *regs = priv->regs;
	141
b4252474 SG	142	/* If it's too soon to do another transaction, wait */
	143	if (plat->deactivate_delay_us && priv->last_transaction_us) {
	144	ulong delay_us; /* The delay completed so far */
	145	delay_us = timer_get_us() - priv->last_transaction_us;
f92cf0ad PT	146	if (delay_us < plat->deactivate_delay_us) {
	147	ulong additional_delay_us =
	148	plat->deactivate_delay_us - delay_us;
	149	debug("%s: delaying by %ld us\n",
	150	__func__, additional_delay_us);
	151	udelay(additional_delay_us);
	152	}
b4252474 SG	153	}
b4252474 SG	154
1b2fd5bf SG	155	debug("activate cs%u\n", cs);
1b2fd5bf SG	156	writel(1 << cs, &regs->ser);
183a3a0f SG	157	if (plat->activate_delay_us)
183a3a0f SG	158	udelay(plat->activate_delay_us);
1b2fd5bf SG	159	}
1b2fd5bf SG	160
183a3a0f	161	static void spi_cs_deactivate(struct udevice *dev, uint cs)
1b2fd5bf	162	{
183a3a0f SG	163	struct udevice *bus = dev->parent;
	164	struct rockchip_spi_platdata *plat = bus->platdata;
	165	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	166	struct rockchip_spi *regs = priv->regs;
	167
1b2fd5bf SG	168	debug("deactivate cs%u\n", cs);
1b2fd5bf SG	169	writel(0, &regs->ser);
183a3a0f SG	170
	171	/* Remember time of this transaction so we can honour the bus delay */
	172	if (plat->deactivate_delay_us)
	173	priv->last_transaction_us = timer_get_us();
1b2fd5bf SG	174	}
1b2fd5bf SG	175
6e019c4f SG	176	#if CONFIG_IS_ENABLED(OF_PLATDATA)
	177	static int conv_of_platdata(struct udevice *dev)
	178	{
	179	struct rockchip_spi_platdata *plat = dev->platdata;
	180	struct dtd_rockchip_rk3288_spi *dtplat = &plat->of_plat;
	181	struct rockchip_spi_priv *priv = dev_get_priv(dev);
	182	int ret;
	183
	184	plat->base = dtplat->reg[0];
	185	plat->frequency = 20000000;
51f1263d	186	ret = clk_get_by_driver_info(dev, dtplat->clocks, &priv->clk);
6e019c4f SG	187	if (ret < 0)
	188	return ret;
	189	dev->req_seq = 0;
	190
	191	return 0;
	192	}
	193	#endif
	194
1b2fd5bf SG	195	static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
1b2fd5bf SG	196	{
6e019c4f SG	197	#if !CONFIG_IS_ENABLED(OF_PLATDATA)
6e019c4f SG	198	struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
71037d1c	199	struct rockchip_spi_priv *priv = dev_get_priv(bus);
1b2fd5bf SG	200	int ret;
1b2fd5bf SG	201
d27c2739	202	plat->base = dev_read_addr(bus);
1b2fd5bf	203
71037d1c SG	204	ret = clk_get_by_index(bus, 0, &priv->clk);
	205	if (ret < 0) {
	206	debug("%s: Could not get clock for %s: %d\n", __func__,
	207	bus->name, ret);
	208	return ret;
	209	}
1b2fd5bf	210
6c65577c PT	211	plat->frequency =
	212	dev_read_u32_default(bus, "spi-max-frequency", 50000000);
	213	plat->deactivate_delay_us =
	214	dev_read_u32_default(bus, "spi-deactivate-delay", 0);
	215	plat->activate_delay_us =
	216	dev_read_u32_default(bus, "spi-activate-delay", 0);
	217
90a28470 SG	218	debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n",
90a28470 SG	219	__func__, (uint)plat->base, plat->frequency,
1b2fd5bf	220	plat->deactivate_delay_us);
6e019c4f	221	#endif
1b2fd5bf SG	222
	223	return 0;
	224	}
	225
bd376714 PT	226	static int rockchip_spi_calc_modclk(ulong max_freq)
bd376714 PT	227	{
d16120a6 PT	228	/*
	229	* While this is not strictly correct for the RK3368, as the
	230	* GPLL will be 576MHz, things will still work, as the
	231	* clk_set_rate(...) implementation in our clock-driver will
	232	* chose the next closest rate not exceeding what we request
	233	* based on the output of this function.
	234	*/
	235
bd376714 PT	236	unsigned div;
	237	const unsigned long gpll_hz = 594000000UL;
	238
	239	/*
	240	* We need to find an input clock that provides at least twice
	241	* the maximum frequency and can be generated from the assumed
	242	* speed of GPLL (594MHz) using an integer divider.
	243	*
	244	* To give us more achievable bitrates at higher speeds (these
	245	* are generated by dividing by an even 16-bit integer from
	246	* this frequency), we try to have an input frequency of at
	247	* least 4x our max_freq.
	248	*/
	249
	250	div = DIV_ROUND_UP(gpll_hz, max_freq * 4);
	251	return gpll_hz / div;
	252	}
	253
1b2fd5bf SG	254	static int rockchip_spi_probe(struct udevice *bus)
	255	{
	256	struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
	257	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	258	int ret;
	259
	260	debug("%s: probe\n", __func__);
6e019c4f SG	261	#if CONFIG_IS_ENABLED(OF_PLATDATA)
	262	ret = conv_of_platdata(bus);
	263	if (ret)
	264	return ret;
	265	#endif
1b2fd5bf SG	266	priv->regs = (struct rockchip_spi *)plat->base;
	267
	268	priv->last_transaction_us = timer_get_us();
	269	priv->max_freq = plat->frequency;
1b2fd5bf	270
bd376714 PT	271	/* Clamp the value from the DTS against any hardware limits */
	272	if (priv->max_freq > ROCKCHIP_SPI_MAX_RATE)
	273	priv->max_freq = ROCKCHIP_SPI_MAX_RATE;
	274
	275	/* Find a module-input clock that fits with the max_freq setting */
	276	ret = clk_set_rate(&priv->clk,
	277	rockchip_spi_calc_modclk(priv->max_freq));
1b2fd5bf SG	278	if (ret < 0) {
	279	debug("%s: Failed to set clock: %d\n", __func__, ret);
	280	return ret;
	281	}
	282	priv->input_rate = ret;
	283	debug("%s: rate = %u\n", __func__, priv->input_rate);
1b2fd5bf SG	284
	285	return 0;
	286	}
	287
	288	static int rockchip_spi_claim_bus(struct udevice *dev)
	289	{
	290	struct udevice *bus = dev->parent;
1b2fd5bf SG	291	struct rockchip_spi_priv *priv = dev_get_priv(bus);
1b2fd5bf SG	292	struct rockchip_spi *regs = priv->regs;
1b2fd5bf	293	uint ctrlr0;
1b2fd5bf SG	294
1b2fd5bf SG	295	/* Disable the SPI hardware */
b6101e90	296	rkspi_enable_chip(regs, false);
1b2fd5bf	297
28a943c1 SG	298	if (priv->speed_hz != priv->last_speed_hz)
28a943c1 SG	299	rkspi_set_clk(priv, priv->speed_hz);
1b2fd5bf SG	300
	301	/* Operation Mode */
	302	ctrlr0 = OMOD_MASTER << OMOD_SHIFT;
	303
	304	/* Data Frame Size */
0e661b6d	305	ctrlr0 \|= DFS_8BIT << DFS_SHIFT;
1b2fd5bf SG	306
	307	/* set SPI mode 0..3 */
	308	if (priv->mode & SPI_CPOL)
	309	ctrlr0 \|= SCOL_HIGH << SCOL_SHIFT;
	310	if (priv->mode & SPI_CPHA)
	311	ctrlr0 \|= SCPH_TOGSTA << SCPH_SHIFT;
	312
	313	/* Chip Select Mode */
	314	ctrlr0 \|= CSM_KEEP << CSM_SHIFT;
	315
	316	/* SSN to Sclk_out delay */
	317	ctrlr0 \|= SSN_DELAY_ONE << SSN_DELAY_SHIFT;
	318
	319	/* Serial Endian Mode */
	320	ctrlr0 \|= SEM_LITTLE << SEM_SHIFT;
	321
	322	/* First Bit Mode */
	323	ctrlr0 \|= FBM_MSB << FBM_SHIFT;
	324
	325	/* Byte and Halfword Transform */
0e661b6d	326	ctrlr0 \|= HALF_WORD_OFF << HALF_WORD_TX_SHIFT;
1b2fd5bf SG	327
	328	/* Rxd Sample Delay */
	329	ctrlr0 \|= 0 << RXDSD_SHIFT;
	330
	331	/* Frame Format */
	332	ctrlr0 \|= FRF_SPI << FRF_SHIFT;
	333
	334	/* Tx and Rx mode */
0e661b6d	335	ctrlr0 \|= TMOD_TR << TMOD_SHIFT;
1b2fd5bf SG	336
1b2fd5bf SG	337	writel(ctrlr0, &regs->ctrlr0);
1b2fd5bf SG	338
	339	return 0;
	340	}
	341
	342	static int rockchip_spi_release_bus(struct udevice *dev)
	343	{
e15af8e2 SG	344	struct udevice *bus = dev->parent;
	345	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	346
	347	rkspi_enable_chip(priv->regs, false);
	348
1b2fd5bf SG	349	return 0;
	350	}
	351
8aa6c921 PT	352	static inline int rockchip_spi_16bit_reader(struct udevice *dev,
	353	u8 *din, int len)
	354	{
	355	struct udevice *bus = dev->parent;
	356	const struct rockchip_spi_params * const data =
	357	(void *)dev_get_driver_data(bus);
	358	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	359	struct rockchip_spi *regs = priv->regs;
	360	const u32 saved_ctrlr0 = readl(&regs->ctrlr0);
	361	#if defined(DEBUG)
	362	u32 statistics_rxlevels[33] = { };
	363	#endif
	364	u32 frames = *len / 2;
2236149e	365	u8 in = (u8 )(*din);
8aa6c921 PT	366	u32 max_chunk_size = SPI_FIFO_DEPTH;
	367
	368	if (!frames)
	369	return 0;
	370
51a644a1 PT	371	/*
	372	* If we know that the hardware will manage RXFIFO overruns
	373	* (i.e. stop the SPI clock until there's space in the FIFO),
	374	* we the allow largest possible chunk size that can be
	375	* represented in CTRLR1.
	376	*/
	377	if (data && data->master_manages_fifo)
dbbdc81c	378	max_chunk_size = ROCKCHIP_SPI_MAX_TRANLEN;
51a644a1	379
8aa6c921 PT	380	// rockchip_spi_configure(dev, mode, size)
	381	rkspi_enable_chip(regs, false);
	382	clrsetbits_le32(&regs->ctrlr0,
	383	TMOD_MASK << TMOD_SHIFT,
	384	TMOD_RO << TMOD_SHIFT);
	385	/* 16bit data frame size */
	386	clrsetbits_le32(&regs->ctrlr0, DFS_MASK, DFS_16BIT);
	387
	388	/* Update caller's context */
	389	const u32 bytes_to_process = 2 * frames;
	390	*din += bytes_to_process;
	391	*len -= bytes_to_process;
	392
	393	/* Process our frames */
	394	while (frames) {
	395	u32 chunk_size = min(frames, max_chunk_size);
	396
	397	frames -= chunk_size;
	398
	399	writew(chunk_size - 1, &regs->ctrlr1);
	400	rkspi_enable_chip(regs, true);
	401
	402	do {
	403	u32 rx_level = readw(&regs->rxflr);
	404	#if defined(DEBUG)
	405	statistics_rxlevels[rx_level]++;
	406	#endif
	407	chunk_size -= rx_level;
2236149e PT	408	while (rx_level--) {
	409	u16 val = readw(regs->rxdr);
	410	*in++ = val & 0xff;
	411	*in++ = val >> 8;
	412	}
8aa6c921 PT	413	} while (chunk_size);
	414
	415	rkspi_enable_chip(regs, false);
	416	}
	417
	418	#if defined(DEBUG)
	419	debug("%s: observed rx_level during processing:\n", __func__);
	420	for (int i = 0; i <= 32; ++i)
	421	if (statistics_rxlevels[i])
	422	debug("\t%2d: %d\n", i, statistics_rxlevels[i]);
	423	#endif
	424	/* Restore the original transfer setup and return error-free. */
	425	writel(saved_ctrlr0, &regs->ctrlr0);
	426	return 0;
	427	}
	428
1b2fd5bf SG	429	static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen,
	430	const void dout, void din, unsigned long flags)
	431	{
	432	struct udevice *bus = dev->parent;
	433	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	434	struct rockchip_spi *regs = priv->regs;
	435	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
	436	int len = bitlen >> 3;
	437	const u8 *out = dout;
	438	u8 *in = din;
	439	int toread, towrite;
8aa6c921	440	int ret = 0;
1b2fd5bf SG	441
	442	debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din,
	443	len, flags);
	444	if (DEBUG_RK_SPI)
	445	rkspi_dump_regs(regs);
	446
	447	/* Assert CS before transfer */
	448	if (flags & SPI_XFER_BEGIN)
183a3a0f	449	spi_cs_activate(dev, slave_plat->cs);
1b2fd5bf	450
8aa6c921 PT	451	/*
	452	* To ensure fast loading of firmware images (e.g. full U-Boot
	453	* stage, ATF, Linux kernel) from SPI flash, we optimise the
	454	* case of read-only transfers by using the full 16bits of each
	455	* FIFO element.
	456	*/
	457	if (!out)
	458	ret = rockchip_spi_16bit_reader(dev, &in, &len);
	459
	460	/* This is the original 8bit reader/writer code */
1b2fd5bf	461	while (len > 0) {
dbbdc81c	462	int todo = min(len, ROCKCHIP_SPI_MAX_TRANLEN);
1b2fd5bf	463
e15af8e2	464	rkspi_enable_chip(regs, false);
1b2fd5bf SG	465	writel(todo - 1, &regs->ctrlr1);
	466	rkspi_enable_chip(regs, true);
	467
	468	toread = todo;
	469	towrite = todo;
	470	while (toread \|\| towrite) {
	471	u32 status = readl(&regs->sr);
	472
	473	if (towrite && !(status & SR_TF_FULL)) {
	474	writel(out ? *out++ : 0, regs->txdr);
	475	towrite--;
	476	}
	477	if (toread && !(status & SR_RF_EMPT)) {
	478	u32 byte = readl(regs->rxdr);
	479
	480	if (in)
	481	*in++ = byte;
	482	toread--;
	483	}
	484	}
7e0e5c55 PT	485
	486	/*
	487	* In case that there's a transmit-component, we need to wait
	488	* until the control goes idle before we can disable the SPI
	489	* control logic (as this will implictly flush the FIFOs).
	490	*/
	491	if (out) {
	492	ret = rkspi_wait_till_not_busy(regs);
	493	if (ret)
	494	break;
	495	}
	496
1b2fd5bf SG	497	len -= todo;
	498	}
	499
	500	/* Deassert CS after transfer */
	501	if (flags & SPI_XFER_END)
183a3a0f	502	spi_cs_deactivate(dev, slave_plat->cs);
1b2fd5bf SG	503
	504	rkspi_enable_chip(regs, false);
	505
	506	return ret;
	507	}
	508
	509	static int rockchip_spi_set_speed(struct udevice *bus, uint speed)
	510	{
	511	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	512
bd376714	513	/* Clamp to the maximum frequency specified in the DTS */
1b2fd5bf SG	514	if (speed > priv->max_freq)
1b2fd5bf SG	515	speed = priv->max_freq;
bd376714	516
1b2fd5bf SG	517	priv->speed_hz = speed;
	518
	519	return 0;
	520	}
	521
	522	static int rockchip_spi_set_mode(struct udevice *bus, uint mode)
	523	{
	524	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	525
	526	priv->mode = mode;
	527
	528	return 0;
	529	}
	530
	531	static const struct dm_spi_ops rockchip_spi_ops = {
	532	.claim_bus = rockchip_spi_claim_bus,
	533	.release_bus = rockchip_spi_release_bus,
	534	.xfer = rockchip_spi_xfer,
	535	.set_speed = rockchip_spi_set_speed,
	536	.set_mode = rockchip_spi_set_mode,
	537	/*
	538	* cs_info is not needed, since we require all chip selects to be
	539	* in the device tree explicitly
	540	*/
	541	};
	542
51a644a1 PT	543	const struct rockchip_spi_params rk3399_spi_params = {
	544	.master_manages_fifo = true,
	545	};
	546
1b2fd5bf	547	static const struct udevice_id rockchip_spi_ids[] = {
e93d2f4e	548	{ .compatible = "rockchip,rk3066-spi" },
1b2fd5bf	549	{ .compatible = "rockchip,rk3288-spi" },
e93d2f4e	550	{ .compatible = "rockchip,rk3328-spi" },
51a644a1 PT	551	{ .compatible = "rockchip,rk3368-spi",
	552	.data = (ulong)&rk3399_spi_params },
	553	{ .compatible = "rockchip,rk3399-spi",
	554	.data = (ulong)&rk3399_spi_params },
1b2fd5bf SG	555	{ }
	556	};
	557
e3e2470f	558	U_BOOT_DRIVER(rockchip_rk3288_spi) = {
6e019c4f	559	.name = "rockchip_rk3288_spi",
1b2fd5bf SG	560	.id = UCLASS_SPI,
	561	.of_match = rockchip_spi_ids,
	562	.ops = &rockchip_spi_ops,
	563	.ofdata_to_platdata = rockchip_spi_ofdata_to_platdata,
41575d8e SG	564	.platdata_auto = sizeof(struct rockchip_spi_platdata),
41575d8e SG	565	.priv_auto = sizeof(struct rockchip_spi_priv),
1b2fd5bf SG	566	.probe = rockchip_spi_probe,
1b2fd5bf SG	567	};
addf358b WL	568
addf358b WL	569	U_BOOT_DRIVER_ALIAS(rockchip_rk3288_spi, rockchip_rk3368_spi)