[u-boot.git] / drivers / phy / phy-stm32-usbphyc.c

// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
 */

#include <common.h>
#include <clk.h>
#include <div64.h>
#include <dm.h>
#include <fdtdec.h>
#include <generic-phy.h>
#include <log.h>
#include <reset.h>
#include <syscon.h>
#include <usb.h>
#include <asm/io.h>
#include <dm/device_compat.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <power/regulator.h>

/* USBPHYC registers */
#define STM32_USBPHYC_PLL	0x0
#define STM32_USBPHYC_MISC	0x8

/* STM32_USBPHYC_PLL bit fields */
#define PLLNDIV			GENMASK(6, 0)
#define PLLNDIV_SHIFT		0
#define PLLFRACIN		GENMASK(25, 10)
#define PLLFRACIN_SHIFT		10
#define PLLEN			BIT(26)
#define PLLSTRB			BIT(27)
#define PLLSTRBYP		BIT(28)
#define PLLFRACCTL		BIT(29)
#define PLLDITHEN0		BIT(30)
#define PLLDITHEN1		BIT(31)

/* STM32_USBPHYC_MISC bit fields */
#define SWITHOST		BIT(0)

#define MAX_PHYS		2

/* max 100 us for PLL lock and 100 us for PHY init */
#define PLL_INIT_TIME_US	200
#define PLL_PWR_DOWN_TIME_US	5
#define PLL_FVCO		2880	 /* in MHz */
#define PLL_INFF_MIN_RATE	19200000 /* in Hz */
#define PLL_INFF_MAX_RATE	38400000 /* in Hz */

struct pll_params {
	u8 ndiv;
	u16 frac;
};

struct stm32_usbphyc {
	fdt_addr_t base;
	struct clk clk;
	struct udevice *vdda1v1;
	struct udevice *vdda1v8;
	struct stm32_usbphyc_phy {
		struct udevice *vdd;
		struct udevice *vbus;
		bool init;
		bool powered;
	} phys[MAX_PHYS];
};

static void stm32_usbphyc_get_pll_params(u32 clk_rate,
					 struct pll_params *pll_params)
{
	unsigned long long fvco, ndiv, frac;

	/*
	 *    | FVCO = INFF*2*(NDIV + FRACT/2^16 ) when DITHER_DISABLE[1] = 1
	 *    | FVCO = 2880MHz
	 *    | NDIV = integer part of input bits to set the LDF
	 *    | FRACT = fractional part of input bits to set the LDF
	 *  =>	PLLNDIV = integer part of (FVCO / (INFF*2))
	 *  =>	PLLFRACIN = fractional part of(FVCO / INFF*2) * 2^16
	 * <=>  PLLFRACIN = ((FVCO / (INFF*2)) - PLLNDIV) * 2^16
	 */
	fvco = (unsigned long long)PLL_FVCO * 1000000; /* In Hz */

	ndiv = fvco;
	do_div(ndiv, (clk_rate * 2));
	pll_params->ndiv = (u8)ndiv;

	frac = fvco * (1 << 16);
	do_div(frac, (clk_rate * 2));
	frac = frac - (ndiv * (1 << 16));
	pll_params->frac = (u16)frac;
}

static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc)
{
	struct pll_params pll_params;
	u32 clk_rate = clk_get_rate(&usbphyc->clk);
	u32 usbphyc_pll;

	if ((clk_rate < PLL_INFF_MIN_RATE) || (clk_rate > PLL_INFF_MAX_RATE)) {
		pr_debug("%s: input clk freq (%dHz) out of range\n",
			 __func__, clk_rate);
		return -EINVAL;
	}

	stm32_usbphyc_get_pll_params(clk_rate, &pll_params);

	usbphyc_pll = PLLDITHEN1 | PLLDITHEN0 | PLLSTRBYP;
	usbphyc_pll |= ((pll_params.ndiv << PLLNDIV_SHIFT) & PLLNDIV);

	if (pll_params.frac) {
		usbphyc_pll |= PLLFRACCTL;
		usbphyc_pll |= ((pll_params.frac << PLLFRACIN_SHIFT)
				 & PLLFRACIN);
	}

	writel(usbphyc_pll, usbphyc->base + STM32_USBPHYC_PLL);

	pr_debug("%s: input clk freq=%dHz, ndiv=%d, frac=%d\n", __func__,
		 clk_rate, pll_params.ndiv, pll_params.frac);

	return 0;
}

static bool stm32_usbphyc_is_init(struct stm32_usbphyc *usbphyc)
{
	int i;

	for (i = 0; i < MAX_PHYS; i++) {
		if (usbphyc->phys[i].init)
			return true;
	}

	return false;
}

static bool stm32_usbphyc_is_powered(struct stm32_usbphyc *usbphyc)
{
	int i;

	for (i = 0; i < MAX_PHYS; i++) {
		if (usbphyc->phys[i].powered)
			return true;
	}

	return false;
}

static int stm32_usbphyc_phy_init(struct phy *phy)
{
	struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
	struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
	bool pllen = readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN ?
		     true : false;
	int ret;

	pr_debug("%s phy ID = %lu\n", __func__, phy->id);
	/* Check if one phy port has already configured the pll */
	if (pllen && stm32_usbphyc_is_init(usbphyc))
		goto initialized;

	if (usbphyc->vdda1v1) {
		ret = regulator_set_enable(usbphyc->vdda1v1, true);
		if (ret)
			return ret;
	}

	if (usbphyc->vdda1v8) {
		ret = regulator_set_enable(usbphyc->vdda1v8, true);
		if (ret)
			return ret;
	}

	if (pllen) {
		clrbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
		udelay(PLL_PWR_DOWN_TIME_US);
	}

	ret = stm32_usbphyc_pll_init(usbphyc);
	if (ret)
		return ret;

	setbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);

	/* We must wait PLL_INIT_TIME_US before using PHY */
	udelay(PLL_INIT_TIME_US);

	if (!(readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN))
		return -EIO;

initialized:
	usbphyc_phy->init = true;

	return 0;
}

static int stm32_usbphyc_phy_exit(struct phy *phy)
{
	struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
	struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
	int ret;

	pr_debug("%s phy ID = %lu\n", __func__, phy->id);
	usbphyc_phy->init = false;

	/* Check if other phy port requires pllen */
	if (stm32_usbphyc_is_init(usbphyc))
		return 0;

	clrbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);

	/*
	 * We must wait PLL_PWR_DOWN_TIME_US before checking that PLLEN
	 * bit is still clear
	 */
	udelay(PLL_PWR_DOWN_TIME_US);

	if (readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN)
		return -EIO;

	if (usbphyc->vdda1v1) {
		ret = regulator_set_enable(usbphyc->vdda1v1, false);
		if (ret)
			return ret;
	}

	if (usbphyc->vdda1v8) {
		ret = regulator_set_enable(usbphyc->vdda1v8, false);
		if (ret)
			return ret;
	}

	return 0;
}

static int stm32_usbphyc_phy_power_on(struct phy *phy)
{
	struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
	struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
	int ret;

	pr_debug("%s phy ID = %lu\n", __func__, phy->id);
	if (usbphyc_phy->vdd) {
		ret = regulator_set_enable(usbphyc_phy->vdd, true);
		if (ret)
			return ret;
	}
	if (usbphyc_phy->vbus) {
		ret = regulator_set_enable(usbphyc_phy->vbus, true);
		if (ret)
			return ret;
	}

	usbphyc_phy->powered = true;

	return 0;
}

static int stm32_usbphyc_phy_power_off(struct phy *phy)
{
	struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
	struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
	int ret;

	pr_debug("%s phy ID = %lu\n", __func__, phy->id);
	usbphyc_phy->powered = false;

	if (stm32_usbphyc_is_powered(usbphyc))
		return 0;

	if (usbphyc_phy->vbus) {
		ret = regulator_set_enable(usbphyc_phy->vbus, false);
		if (ret)
			return ret;
	}
	if (usbphyc_phy->vdd) {
		ret = regulator_set_enable_if_allowed(usbphyc_phy->vdd, false);
		if (ret)
			return ret;
	}

	return 0;
}

static int stm32_usbphyc_get_regulator(ofnode node,
				       char *supply_name,
				       struct udevice **regulator)
{
	struct ofnode_phandle_args regulator_phandle;
	int ret;

	ret = ofnode_parse_phandle_with_args(node, supply_name,
					     NULL, 0, 0,
					     &regulator_phandle);
	if (ret)
		return ret;

	ret = uclass_get_device_by_ofnode(UCLASS_REGULATOR,
					  regulator_phandle.node,
					  regulator);
	if (ret)
		return ret;

	return 0;
}

static int stm32_usbphyc_of_xlate(struct phy *phy,
				  struct ofnode_phandle_args *args)
{
	if (args->args_count < 1)
		return -ENODEV;

	if (args->args[0] >= MAX_PHYS)
		return -ENODEV;

	phy->id = args->args[0];

	if ((phy->id == 0 && args->args_count != 1) ||
	    (phy->id == 1 && args->args_count != 2)) {
		dev_err(phy->dev, "invalid number of cells for phy port%ld\n",
			phy->id);
		return -EINVAL;
	}

	return 0;
}

static const struct phy_ops stm32_usbphyc_phy_ops = {
	.init = stm32_usbphyc_phy_init,
	.exit = stm32_usbphyc_phy_exit,
	.power_on = stm32_usbphyc_phy_power_on,
	.power_off = stm32_usbphyc_phy_power_off,
	.of_xlate = stm32_usbphyc_of_xlate,
};

static int stm32_usbphyc_probe(struct udevice *dev)
{
	struct stm32_usbphyc *usbphyc = dev_get_priv(dev);
	struct reset_ctl reset;
	ofnode node;
	int i, ret;

	usbphyc->base = dev_read_addr(dev);
	if (usbphyc->base == FDT_ADDR_T_NONE)
		return -EINVAL;

	/* Enable clock */
	ret = clk_get_by_index(dev, 0, &usbphyc->clk);
	if (ret)
		return ret;

	ret = clk_enable(&usbphyc->clk);
	if (ret)
		return ret;

	/* Reset */
	ret = reset_get_by_index(dev, 0, &reset);
	if (!ret) {
		reset_assert(&reset);
		udelay(2);
		reset_deassert(&reset);
	}

	/* get usbphyc regulator */
	ret = device_get_supply_regulator(dev, "vdda1v1-supply",
					  &usbphyc->vdda1v1);
	if (ret) {
		dev_err(dev, "Can't get vdda1v1-supply regulator\n");
		return ret;
	}

	ret = device_get_supply_regulator(dev, "vdda1v8-supply",
					  &usbphyc->vdda1v8);
	if (ret) {
		dev_err(dev, "Can't get vdda1v8-supply regulator\n");
		return ret;
	}

	/*
	 * parse all PHY subnodes in order to populate regulator associated
	 * to each PHY port
	 */
	node = dev_read_first_subnode(dev);
	for (i = 0; i < MAX_PHYS; i++) {
		struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + i;

		usbphyc_phy->init = false;
		usbphyc_phy->powered = false;
		ret = stm32_usbphyc_get_regulator(node, "phy-supply",
						  &usbphyc_phy->vdd);
		if (ret) {
			dev_err(dev, "Can't get phy-supply regulator\n");
			return ret;
		}

		ret = stm32_usbphyc_get_regulator(node, "vbus-supply",
						  &usbphyc_phy->vbus);
		if (ret)
			usbphyc_phy->vbus = NULL;

		node = dev_read_next_subnode(node);
	}

	/* Check if second port has to be used for host controller */
	if (dev_read_bool(dev, "st,port2-switch-to-host"))
		setbits_le32(usbphyc->base + STM32_USBPHYC_MISC, SWITHOST);

	return 0;
}

static const struct udevice_id stm32_usbphyc_of_match[] = {
	{ .compatible = "st,stm32mp1-usbphyc", },
	{ },
};

U_BOOT_DRIVER(stm32_usb_phyc) = {
	.name = "stm32-usbphyc",
	.id = UCLASS_PHY,
	.of_match = stm32_usbphyc_of_match,
	.ops = &stm32_usbphyc_phy_ops,
	.probe = stm32_usbphyc_probe,
	.priv_auto	= sizeof(struct stm32_usbphyc),
};
Commit	Line	Data
624d2cae	1	// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3b291216 PC	2	/*
	3	* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
	4	*/
	5
	6	#include <common.h>
	7	#include <clk.h>
	8	#include <div64.h>
	9	#include <dm.h>
	10	#include <fdtdec.h>
	11	#include <generic-phy.h>
f7ae49fc	12	#include <log.h>
3b291216 PC	13	#include <reset.h>
	14	#include <syscon.h>
	15	#include <usb.h>
	16	#include <asm/io.h>
336d4615	17	#include <dm/device_compat.h>
3b291216	18	#include <linux/bitops.h>
c05ed00a	19	#include <linux/delay.h>
3b291216 PC	20	#include <power/regulator.h>
	21
	22	/* USBPHYC registers */
	23	#define STM32_USBPHYC_PLL 0x0
	24	#define STM32_USBPHYC_MISC 0x8
	25
	26	/* STM32_USBPHYC_PLL bit fields */
	27	#define PLLNDIV GENMASK(6, 0)
	28	#define PLLNDIV_SHIFT 0
	29	#define PLLFRACIN GENMASK(25, 10)
	30	#define PLLFRACIN_SHIFT 10
	31	#define PLLEN BIT(26)
	32	#define PLLSTRB BIT(27)
	33	#define PLLSTRBYP BIT(28)
	34	#define PLLFRACCTL BIT(29)
	35	#define PLLDITHEN0 BIT(30)
	36	#define PLLDITHEN1 BIT(31)
	37
	38	/* STM32_USBPHYC_MISC bit fields */
	39	#define SWITHOST BIT(0)
	40
	41	#define MAX_PHYS 2
	42
901f6950 PD	43	/* max 100 us for PLL lock and 100 us for PHY init */
901f6950 PD	44	#define PLL_INIT_TIME_US 200
3b291216 PC	45	#define PLL_PWR_DOWN_TIME_US 5
	46	#define PLL_FVCO 2880 /* in MHz */
	47	#define PLL_INFF_MIN_RATE 19200000 /* in Hz */
	48	#define PLL_INFF_MAX_RATE 38400000 /* in Hz */
	49
	50	struct pll_params {
	51	u8 ndiv;
	52	u16 frac;
	53	};
	54
	55	struct stm32_usbphyc {
	56	fdt_addr_t base;
	57	struct clk clk;
c50151d4 PD	58	struct udevice *vdda1v1;
c50151d4 PD	59	struct udevice *vdda1v8;
3b291216 PC	60	struct stm32_usbphyc_phy {
3b291216 PC	61	struct udevice *vdd;
c4801389	62	struct udevice *vbus;
3b291216 PC	63	bool init;
	64	bool powered;
	65	} phys[MAX_PHYS];
	66	};
	67
e1904abc PD	68	static void stm32_usbphyc_get_pll_params(u32 clk_rate,
e1904abc PD	69	struct pll_params *pll_params)
3b291216 PC	70	{
	71	unsigned long long fvco, ndiv, frac;
	72
	73	/*
	74	* \| FVCO = INFF2(NDIV + FRACT/2^16 ) when DITHER_DISABLE[1] = 1
	75	* \| FVCO = 2880MHz
	76	* \| NDIV = integer part of input bits to set the LDF
	77	* \| FRACT = fractional part of input bits to set the LDF
	78	* => PLLNDIV = integer part of (FVCO / (INFF*2))
	79	* => PLLFRACIN = fractional part of(FVCO / INFF2) 2^16
	80	* <=> PLLFRACIN = ((FVCO / (INFF2)) - PLLNDIV) 2^16
	81	*/
	82	fvco = (unsigned long long)PLL_FVCO * 1000000; /* In Hz */
	83
	84	ndiv = fvco;
	85	do_div(ndiv, (clk_rate * 2));
	86	pll_params->ndiv = (u8)ndiv;
	87
	88	frac = fvco * (1 << 16);
	89	do_div(frac, (clk_rate * 2));
	90	frac = frac - (ndiv * (1 << 16));
	91	pll_params->frac = (u16)frac;
	92	}
	93
	94	static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc)
	95	{
	96	struct pll_params pll_params;
	97	u32 clk_rate = clk_get_rate(&usbphyc->clk);
	98	u32 usbphyc_pll;
	99
	100	if ((clk_rate < PLL_INFF_MIN_RATE) \|\| (clk_rate > PLL_INFF_MAX_RATE)) {
	101	pr_debug("%s: input clk freq (%dHz) out of range\n",
	102	__func__, clk_rate);
	103	return -EINVAL;
	104	}
	105
	106	stm32_usbphyc_get_pll_params(clk_rate, &pll_params);
	107
	108	usbphyc_pll = PLLDITHEN1 \| PLLDITHEN0 \| PLLSTRBYP;
	109	usbphyc_pll \|= ((pll_params.ndiv << PLLNDIV_SHIFT) & PLLNDIV);
	110
	111	if (pll_params.frac) {
	112	usbphyc_pll \|= PLLFRACCTL;
	113	usbphyc_pll \|= ((pll_params.frac << PLLFRACIN_SHIFT)
	114	& PLLFRACIN);
	115	}
	116
	117	writel(usbphyc_pll, usbphyc->base + STM32_USBPHYC_PLL);
	118
	119	pr_debug("%s: input clk freq=%dHz, ndiv=%d, frac=%d\n", __func__,
	120	clk_rate, pll_params.ndiv, pll_params.frac);
	121
	122	return 0;
	123	}
	124
	125	static bool stm32_usbphyc_is_init(struct stm32_usbphyc *usbphyc)
	126	{
	127	int i;
	128
	129	for (i = 0; i < MAX_PHYS; i++) {
	130	if (usbphyc->phys[i].init)
	131	return true;
	132	}
	133
134	return false;
135	}
136
137	static bool stm32_usbphyc_is_powered(struct stm32_usbphyc *usbphyc)
138	{
139	int i;
140
141	for (i = 0; i < MAX_PHYS; i++) {
142	if (usbphyc->phys[i].powered)
143	return true;
144	}
145
146	return false;
147	}
148
149	static int stm32_usbphyc_phy_init(struct phy *phy)
150	{
151	struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
152	struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
153	bool pllen = readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN ?
154	true : false;
155	int ret;
156
157	pr_debug("%s phy ID = %lu\n", __func__, phy->id);
158	/* Check if one phy port has already configured the pll */
159	if (pllen && stm32_usbphyc_is_init(usbphyc))
160	goto initialized;
161
e1904abc PD	162	if (usbphyc->vdda1v1) {
	163	ret = regulator_set_enable(usbphyc->vdda1v1, true);
	164	if (ret)
	165	return ret;
	166	}
	167
	168	if (usbphyc->vdda1v8) {
	169	ret = regulator_set_enable(usbphyc->vdda1v8, true);
	170	if (ret)
	171	return ret;
	172	}
	173
3b291216 PC	174	if (pllen) {
	175	clrbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
	176	udelay(PLL_PWR_DOWN_TIME_US);
	177	}
	178
	179	ret = stm32_usbphyc_pll_init(usbphyc);
	180	if (ret)
	181	return ret;
	182
	183	setbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
	184
901f6950 PD	185	/* We must wait PLL_INIT_TIME_US before using PHY */
901f6950 PD	186	udelay(PLL_INIT_TIME_US);
3b291216 PC	187
	188	if (!(readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN))
	189	return -EIO;
	190
	191	initialized:
	192	usbphyc_phy->init = true;
	193
	194	return 0;
	195	}
	196
	197	static int stm32_usbphyc_phy_exit(struct phy *phy)
	198	{
	199	struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
	200	struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
e1904abc	201	int ret;
3b291216 PC	202
	203	pr_debug("%s phy ID = %lu\n", __func__, phy->id);
	204	usbphyc_phy->init = false;
	205
	206	/* Check if other phy port requires pllen */
	207	if (stm32_usbphyc_is_init(usbphyc))
	208	return 0;
	209
	210	clrbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
	211
	212	/*
	213	* We must wait PLL_PWR_DOWN_TIME_US before checking that PLLEN
	214	* bit is still clear
	215	*/
	216	udelay(PLL_PWR_DOWN_TIME_US);
	217
	218	if (readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN)
	219	return -EIO;
	220
c50151d4	221	if (usbphyc->vdda1v1) {
e1904abc	222	ret = regulator_set_enable(usbphyc->vdda1v1, false);
3b291216 PC	223	if (ret)
	224	return ret;
	225	}
	226
c50151d4	227	if (usbphyc->vdda1v8) {
e1904abc	228	ret = regulator_set_enable(usbphyc->vdda1v8, false);
3b291216 PC	229	if (ret)
	230	return ret;
	231	}
c50151d4	232
e1904abc PD	233	return 0;
	234	}
	235
	236	static int stm32_usbphyc_phy_power_on(struct phy *phy)
	237	{
	238	struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
	239	struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
	240	int ret;
	241
	242	pr_debug("%s phy ID = %lu\n", __func__, phy->id);
	243	if (usbphyc_phy->vdd) {
	244	ret = regulator_set_enable(usbphyc_phy->vdd, true);
3b291216 PC	245	if (ret)
	246	return ret;
	247	}
c4801389 PD	248	if (usbphyc_phy->vbus) {
	249	ret = regulator_set_enable(usbphyc_phy->vbus, true);
	250	if (ret)
	251	return ret;
	252	}
3b291216 PC	253
	254	usbphyc_phy->powered = true;
	255
	256	return 0;
	257	}
	258
	259	static int stm32_usbphyc_phy_power_off(struct phy *phy)
	260	{
	261	struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
	262	struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
	263	int ret;
	264
	265	pr_debug("%s phy ID = %lu\n", __func__, phy->id);
	266	usbphyc_phy->powered = false;
	267
	268	if (stm32_usbphyc_is_powered(usbphyc))
	269	return 0;
	270
c4801389 PD	271	if (usbphyc_phy->vbus) {
	272	ret = regulator_set_enable(usbphyc_phy->vbus, false);
	273	if (ret)
	274	return ret;
	275	}
e1904abc	276	if (usbphyc_phy->vdd) {
9f9191a1	277	ret = regulator_set_enable_if_allowed(usbphyc_phy->vdd, false);
3b291216 PC	278	if (ret)
	279	return ret;
	280	}
	281
	282	return 0;
	283	}
	284
c4801389	285	static int stm32_usbphyc_get_regulator(ofnode node,
3b291216 PC	286	char *supply_name,
	287	struct udevice **regulator)
	288	{
	289	struct ofnode_phandle_args regulator_phandle;
	290	int ret;
	291
	292	ret = ofnode_parse_phandle_with_args(node, supply_name,
	293	NULL, 0, 0,
	294	&regulator_phandle);
c4801389	295	if (ret)
3b291216	296	return ret;
3b291216 PC	297
	298	ret = uclass_get_device_by_ofnode(UCLASS_REGULATOR,
	299	regulator_phandle.node,
	300	regulator);
c4801389	301	if (ret)
3b291216	302	return ret;
3b291216 PC	303
	304	return 0;
	305	}
	306
	307	static int stm32_usbphyc_of_xlate(struct phy *phy,
	308	struct ofnode_phandle_args *args)
	309	{
1655f2da PD	310	if (args->args_count < 1)
1655f2da PD	311	return -ENODEV;
3b291216 PC	312
	313	if (args->args[0] >= MAX_PHYS)
	314	return -ENODEV;
	315
1655f2da PD	316	phy->id = args->args[0];
	317
	318	if ((phy->id == 0 && args->args_count != 1) \|\|
	319	(phy->id == 1 && args->args_count != 2)) {
0aeaca62	320	dev_err(phy->dev, "invalid number of cells for phy port%ld\n",
1655f2da PD	321	phy->id);
	322	return -EINVAL;
	323	}
3b291216 PC	324
	325	return 0;
	326	}
	327
	328	static const struct phy_ops stm32_usbphyc_phy_ops = {
	329	.init = stm32_usbphyc_phy_init,
	330	.exit = stm32_usbphyc_phy_exit,
	331	.power_on = stm32_usbphyc_phy_power_on,
	332	.power_off = stm32_usbphyc_phy_power_off,
	333	.of_xlate = stm32_usbphyc_of_xlate,
	334	};
	335
	336	static int stm32_usbphyc_probe(struct udevice *dev)
	337	{
	338	struct stm32_usbphyc *usbphyc = dev_get_priv(dev);
	339	struct reset_ctl reset;
	340	ofnode node;
	341	int i, ret;
	342
	343	usbphyc->base = dev_read_addr(dev);
	344	if (usbphyc->base == FDT_ADDR_T_NONE)
	345	return -EINVAL;
	346
	347	/* Enable clock */
	348	ret = clk_get_by_index(dev, 0, &usbphyc->clk);
	349	if (ret)
	350	return ret;
	351
	352	ret = clk_enable(&usbphyc->clk);
	353	if (ret)
	354	return ret;
	355
	356	/* Reset */
	357	ret = reset_get_by_index(dev, 0, &reset);
	358	if (!ret) {
	359	reset_assert(&reset);
	360	udelay(2);
	361	reset_deassert(&reset);
	362	}
	363
c50151d4 PD	364	/* get usbphyc regulator */
	365	ret = device_get_supply_regulator(dev, "vdda1v1-supply",
	366	&usbphyc->vdda1v1);
	367	if (ret) {
	368	dev_err(dev, "Can't get vdda1v1-supply regulator\n");
	369	return ret;
	370	}
	371
	372	ret = device_get_supply_regulator(dev, "vdda1v8-supply",
	373	&usbphyc->vdda1v8);
	374	if (ret) {
	375	dev_err(dev, "Can't get vdda1v8-supply regulator\n");
	376	return ret;
	377	}
	378
3b291216 PC	379	/*
	380	* parse all PHY subnodes in order to populate regulator associated
	381	* to each PHY port
	382	*/
	383	node = dev_read_first_subnode(dev);
	384	for (i = 0; i < MAX_PHYS; i++) {
	385	struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + i;
	386
3b291216 PC	387	usbphyc_phy->init = false;
3b291216 PC	388	usbphyc_phy->powered = false;
c4801389	389	ret = stm32_usbphyc_get_regulator(node, "phy-supply",
3b291216	390	&usbphyc_phy->vdd);
c4801389 PD	391	if (ret) {
c4801389 PD	392	dev_err(dev, "Can't get phy-supply regulator\n");
3b291216	393	return ret;
c4801389 PD	394	}
	395
	396	ret = stm32_usbphyc_get_regulator(node, "vbus-supply",
	397	&usbphyc_phy->vbus);
	398	if (ret)
	399	usbphyc_phy->vbus = NULL;
3b291216	400
3b291216 PC	401	node = dev_read_next_subnode(node);
	402	}
	403
	404	/* Check if second port has to be used for host controller */
	405	if (dev_read_bool(dev, "st,port2-switch-to-host"))
	406	setbits_le32(usbphyc->base + STM32_USBPHYC_MISC, SWITHOST);
	407
	408	return 0;
	409	}
	410
	411	static const struct udevice_id stm32_usbphyc_of_match[] = {
	412	{ .compatible = "st,stm32mp1-usbphyc", },
	413	{ },
	414	};
	415
	416	U_BOOT_DRIVER(stm32_usb_phyc) = {
	417	.name = "stm32-usbphyc",
	418	.id = UCLASS_PHY,
	419	.of_match = stm32_usbphyc_of_match,
	420	.ops = &stm32_usbphyc_phy_ops,
	421	.probe = stm32_usbphyc_probe,
41575d8e	422	.priv_auto = sizeof(struct stm32_usbphyc),
3b291216	423	};