[u-boot.git] / drivers / spi / mxc_spi.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2008, Guennadi Liakhovetski <[email protected]>
 */

#include <common.h>
#include <clk.h>
#include <dm.h>
#include <log.h>
#include <malloc.h>
#include <spi.h>
#include <asm/global_data.h>
#include <dm/device_compat.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/mach-imx/spi.h>

DECLARE_GLOBAL_DATA_PTR;

/* MX35 and older is CSPI */
#if defined(CONFIG_MX25) || defined(CONFIG_MX31) || defined(CONFIG_MX35)
#define MXC_CSPI
struct cspi_regs {
	u32 rxdata;
	u32 txdata;
	u32 ctrl;
	u32 intr;
	u32 dma;
	u32 stat;
	u32 period;
	u32 test;
};

#define MXC_CSPICTRL_EN			BIT(0)
#define MXC_CSPICTRL_MODE		BIT(1)
#define MXC_CSPICTRL_XCH		BIT(2)
#define MXC_CSPICTRL_SMC		BIT(3)
#define MXC_CSPICTRL_POL		BIT(4)
#define MXC_CSPICTRL_PHA		BIT(5)
#define MXC_CSPICTRL_SSCTL		BIT(6)
#define MXC_CSPICTRL_SSPOL		BIT(7)
#define MXC_CSPICTRL_DATARATE(x)	(((x) & 0x7) << 16)
#define MXC_CSPICTRL_RXOVF		BIT(6)
#define MXC_CSPIPERIOD_32KHZ		BIT(15)
#define MAX_SPI_BYTES			4
#if defined(CONFIG_MX25) || defined(CONFIG_MX35)
#define MXC_CSPICTRL_CHIPSELECT(x)	(((x) & 0x3) << 12)
#define MXC_CSPICTRL_BITCOUNT(x)	(((x) & 0xfff) << 20)
#define MXC_CSPICTRL_TC			BIT(7)
#define MXC_CSPICTRL_MAXBITS		0xfff
#else	/* MX31 */
#define MXC_CSPICTRL_CHIPSELECT(x)	(((x) & 0x3) << 24)
#define MXC_CSPICTRL_BITCOUNT(x)	(((x) & 0x1f) << 8)
#define MXC_CSPICTRL_TC			BIT(8)
#define MXC_CSPICTRL_MAXBITS		0x1f
#endif

#else	/* MX51 and newer is ECSPI */
#define MXC_ECSPI
struct cspi_regs {
	u32 rxdata;
	u32 txdata;
	u32 ctrl;
	u32 cfg;
	u32 intr;
	u32 dma;
	u32 stat;
	u32 period;
};

#define MXC_CSPICTRL_EN			BIT(0)
#define MXC_CSPICTRL_MODE		BIT(1)
#define MXC_CSPICTRL_XCH		BIT(2)
#define MXC_CSPICTRL_MODE_MASK		(0xf << 4)
#define MXC_CSPICTRL_CHIPSELECT(x)	(((x) & 0x3) << 12)
#define MXC_CSPICTRL_BITCOUNT(x)	(((x) & 0xfff) << 20)
#define MXC_CSPICTRL_PREDIV(x)		(((x) & 0xF) << 12)
#define MXC_CSPICTRL_POSTDIV(x)		(((x) & 0xF) << 8)
#define MXC_CSPICTRL_SELCHAN(x)		(((x) & 0x3) << 18)
#define MXC_CSPICTRL_MAXBITS		0xfff
#define MXC_CSPICTRL_TC			BIT(7)
#define MXC_CSPICTRL_RXOVF		BIT(6)
#define MXC_CSPIPERIOD_32KHZ		BIT(15)
#define MAX_SPI_BYTES			32

/* Bit position inside CTRL register to be associated with SS */
#define MXC_CSPICTRL_CHAN	18

/* Bit position inside CON register to be associated with SS */
#define MXC_CSPICON_PHA		0  /* SCLK phase control */
#define MXC_CSPICON_POL		4  /* SCLK polarity */
#define MXC_CSPICON_SSPOL	12 /* SS polarity */
#define MXC_CSPICON_CTL		20 /* inactive state of SCLK */
#endif

#ifdef CONFIG_MX27
/* i.MX27 has a completely wrong register layout and register definitions in the
 * datasheet, the correct one is in the Freescale's Linux driver */

#error "i.MX27 CSPI not supported due to drastic differences in register definitions" \
"See linux mxc_spi driver from Freescale for details."
#endif

__weak int board_spi_cs_gpio(unsigned bus, unsigned cs)
{
	return -1;
}

#define OUT	MXC_GPIO_DIRECTION_OUT

#define reg_read readl
#define reg_write(a, v) writel(v, a)

#if !defined(CONFIG_SYS_SPI_MXC_WAIT)
#define CONFIG_SYS_SPI_MXC_WAIT		(CONFIG_SYS_HZ/100)	/* 10 ms */
#endif

#define MAX_CS_COUNT	4

struct mxc_spi_slave {
	struct spi_slave slave;
	unsigned long	base;
	u32		ctrl_reg;
#if defined(MXC_ECSPI)
	u32		cfg_reg;
#endif
	int		gpio;
	int		ss_pol;
	unsigned int	max_hz;
	unsigned int	mode;
	struct gpio_desc ss;
	struct gpio_desc cs_gpios[MAX_CS_COUNT];
	struct udevice *dev;
};

static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
{
	return container_of(slave, struct mxc_spi_slave, slave);
}

static void mxc_spi_cs_activate(struct mxc_spi_slave *mxcs)
{
#if CONFIG_IS_ENABLED(DM_SPI)
	struct udevice *dev = mxcs->dev;
	struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);

	u32 cs = slave_plat->cs;

	if (!dm_gpio_is_valid(&mxcs->cs_gpios[cs]))
		return;

	dm_gpio_set_value(&mxcs->cs_gpios[cs], 1);
#else
	if (mxcs->gpio > 0)
		gpio_set_value(mxcs->gpio, mxcs->ss_pol);
#endif
}

static void mxc_spi_cs_deactivate(struct mxc_spi_slave *mxcs)
{
#if CONFIG_IS_ENABLED(DM_SPI)
	struct udevice *dev = mxcs->dev;
	struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);

	u32 cs = slave_plat->cs;

	if (!dm_gpio_is_valid(&mxcs->cs_gpios[cs]))
		return;

	dm_gpio_set_value(&mxcs->cs_gpios[cs], 0);
#else
	if (mxcs->gpio > 0)
		gpio_set_value(mxcs->gpio, !(mxcs->ss_pol));
#endif
}

u32 get_cspi_div(u32 div)
{
	int i;

	for (i = 0; i < 8; i++) {
		if (div <= (4 << i))
			return i;
	}
	return i;
}

#ifdef MXC_CSPI
static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
{
	unsigned int ctrl_reg;
	u32 clk_src;
	u32 div;
	unsigned int max_hz = mxcs->max_hz;
	unsigned int mode = mxcs->mode;

	clk_src = mxc_get_clock(MXC_CSPI_CLK);

	div = DIV_ROUND_UP(clk_src, max_hz);
	div = get_cspi_div(div);

	debug("clk %d Hz, div %d, real clk %d Hz\n",
		max_hz, div, clk_src / (4 << div));

	ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) |
		MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) |
		MXC_CSPICTRL_DATARATE(div) |
		MXC_CSPICTRL_EN |
#ifdef CONFIG_MX35
		MXC_CSPICTRL_SSCTL |
#endif
		MXC_CSPICTRL_MODE;

	if (mode & SPI_CPHA)
		ctrl_reg |= MXC_CSPICTRL_PHA;
	if (mode & SPI_CPOL)
		ctrl_reg |= MXC_CSPICTRL_POL;
	if (mode & SPI_CS_HIGH)
		ctrl_reg |= MXC_CSPICTRL_SSPOL;
	mxcs->ctrl_reg = ctrl_reg;

	return 0;
}
#endif

#ifdef MXC_ECSPI
static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
{
	u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
	s32 reg_ctrl, reg_config;
	u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0;
	u32 pre_div = 0, post_div = 0;
	struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
	unsigned int max_hz = mxcs->max_hz;
	unsigned int mode = mxcs->mode;

	/*
	 * Reset SPI and set all CSs to master mode, if toggling
	 * between slave and master mode we might see a glitch
	 * on the clock line
	 */
	reg_ctrl = MXC_CSPICTRL_MODE_MASK;
	reg_write(&regs->ctrl, reg_ctrl);
	reg_ctrl |=  MXC_CSPICTRL_EN;
	reg_write(&regs->ctrl, reg_ctrl);

	if (clk_src > max_hz) {
		pre_div = (clk_src - 1) / max_hz;
		/* fls(1) = 1, fls(0x80000000) = 32, fls(16) = 5 */
		post_div = fls(pre_div);
		if (post_div > 4) {
			post_div -= 4;
			if (post_div >= 16) {
				printf("Error: no divider for the freq: %d\n",
					max_hz);
				return -1;
			}
			pre_div >>= post_div;
		} else {
			post_div = 0;
		}
	}

	debug("pre_div = %d, post_div=%d\n", pre_div, post_div);
	reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) |
		MXC_CSPICTRL_SELCHAN(cs);
	reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) |
		MXC_CSPICTRL_PREDIV(pre_div);
	reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) |
		MXC_CSPICTRL_POSTDIV(post_div);

	if (mode & SPI_CS_HIGH)
		ss_pol = 1;

	if (mode & SPI_CPOL) {
		sclkpol = 1;
		sclkctl = 1;
	}

	if (mode & SPI_CPHA)
		sclkpha = 1;

	reg_config = reg_read(&regs->cfg);

	/*
	 * Configuration register setup
	 * The MX51 supports different setup for each SS
	 */
	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) |
		(ss_pol << (cs + MXC_CSPICON_SSPOL));
	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) |
		(sclkpol << (cs + MXC_CSPICON_POL));
	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_CTL))) |
		(sclkctl << (cs + MXC_CSPICON_CTL));
	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) |
		(sclkpha << (cs + MXC_CSPICON_PHA));

	debug("reg_ctrl = 0x%x\n", reg_ctrl);
	reg_write(&regs->ctrl, reg_ctrl);
	debug("reg_config = 0x%x\n", reg_config);
	reg_write(&regs->cfg, reg_config);

	/* save config register and control register */
	mxcs->ctrl_reg = reg_ctrl;
	mxcs->cfg_reg = reg_config;

	/* clear interrupt reg */
	reg_write(&regs->intr, 0);
	reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);

	return 0;
}
#endif

int spi_xchg_single(struct mxc_spi_slave *mxcs, unsigned int bitlen,
	const u8 *dout, u8 *din, unsigned long flags)
{
	int nbytes = DIV_ROUND_UP(bitlen, 8);
	u32 data, cnt, i;
	struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
	u32 ts;
	int status;

	debug("%s: bitlen %d dout 0x%lx din 0x%lx\n",
		__func__, bitlen, (ulong)dout, (ulong)din);

	mxcs->ctrl_reg = (mxcs->ctrl_reg &
		~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) |
		MXC_CSPICTRL_BITCOUNT(bitlen - 1);

	reg_write(&regs->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN);
#ifdef MXC_ECSPI
	reg_write(&regs->cfg, mxcs->cfg_reg);
#endif

	/* Clear interrupt register */
	reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);

	/*
	 * The SPI controller works only with words,
	 * check if less than a word is sent.
	 * Access to the FIFO is only 32 bit
	 */
	if (bitlen % 32) {
		data = 0;
		cnt = (bitlen % 32) / 8;
		if (dout) {
			for (i = 0; i < cnt; i++) {
				data = (data << 8) | (*dout++ & 0xFF);
			}
		}
		debug("Sending SPI 0x%x\n", data);

		reg_write(&regs->txdata, data);
		nbytes -= cnt;
	}

	data = 0;

	while (nbytes > 0) {
		data = 0;
		if (dout) {
			/* Buffer is not 32-bit aligned */
			if ((unsigned long)dout & 0x03) {
				data = 0;
				for (i = 0; i < 4; i++)
					data = (data << 8) | (*dout++ & 0xFF);
			} else {
				data = *(u32 *)dout;
				data = cpu_to_be32(data);
				dout += 4;
			}
		}
		debug("Sending SPI 0x%x\n", data);
		reg_write(&regs->txdata, data);
		nbytes -= 4;
	}

	/* FIFO is written, now starts the transfer setting the XCH bit */
	reg_write(&regs->ctrl, mxcs->ctrl_reg |
		MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH);

	ts = get_timer(0);
	status = reg_read(&regs->stat);
	/* Wait until the TC (Transfer completed) bit is set */
	while ((status & MXC_CSPICTRL_TC) == 0) {
		if (get_timer(ts) > CONFIG_SYS_SPI_MXC_WAIT) {
			printf("spi_xchg_single: Timeout!\n");
			return -1;
		}
		status = reg_read(&regs->stat);
	}

	/* Transfer completed, clear any pending request */
	reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);

	nbytes = DIV_ROUND_UP(bitlen, 8);

	cnt = nbytes % 32;

	if (bitlen % 32) {
		data = reg_read(&regs->rxdata);
		cnt = (bitlen % 32) / 8;
		data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8);
		debug("SPI Rx unaligned: 0x%x\n", data);
		if (din) {
			memcpy(din, &data, cnt);
			din += cnt;
		}
		nbytes -= cnt;
	}

	while (nbytes > 0) {
		u32 tmp;
		tmp = reg_read(&regs->rxdata);
		data = cpu_to_be32(tmp);
		debug("SPI Rx: 0x%x 0x%x\n", tmp, data);
		cnt = min_t(u32, nbytes, sizeof(data));
		if (din) {
			memcpy(din, &data, cnt);
			din += cnt;
		}
		nbytes -= cnt;
	}

	return 0;

}

static int mxc_spi_xfer_internal(struct mxc_spi_slave *mxcs,
				 unsigned int bitlen, const void *dout,
				 void *din, unsigned long flags)
{
	int n_bytes = DIV_ROUND_UP(bitlen, 8);
	int n_bits;
	int ret;
	u32 blk_size;
	u8 *p_outbuf = (u8 *)dout;
	u8 *p_inbuf = (u8 *)din;

	if (!mxcs)
		return -EINVAL;

	if (flags & SPI_XFER_BEGIN)
		mxc_spi_cs_activate(mxcs);

	while (n_bytes > 0) {
		if (n_bytes < MAX_SPI_BYTES)
			blk_size = n_bytes;
		else
			blk_size = MAX_SPI_BYTES;

		n_bits = blk_size * 8;

		ret = spi_xchg_single(mxcs, n_bits, p_outbuf, p_inbuf, 0);

		if (ret)
			return ret;
		if (dout)
			p_outbuf += blk_size;
		if (din)
			p_inbuf += blk_size;
		n_bytes -= blk_size;
	}

	if (flags & SPI_XFER_END) {
		mxc_spi_cs_deactivate(mxcs);
	}

	return 0;
}

static int mxc_spi_claim_bus_internal(struct mxc_spi_slave *mxcs, int cs)
{
	struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
	int ret;

	reg_write(&regs->rxdata, 1);
	udelay(1);
	ret = spi_cfg_mxc(mxcs, cs);
	if (ret) {
		printf("mxc_spi: cannot setup SPI controller\n");
		return ret;
	}
	reg_write(&regs->period, MXC_CSPIPERIOD_32KHZ);
	reg_write(&regs->intr, 0);

	return 0;
}

#if !CONFIG_IS_ENABLED(DM_SPI)
int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
		void *din, unsigned long flags)
{
	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);

	return mxc_spi_xfer_internal(mxcs, bitlen, dout, din, flags);
}

/*
 * Some SPI devices require active chip-select over multiple
 * transactions, we achieve this using a GPIO. Still, the SPI
 * controller has to be configured to use one of its own chipselects.
 * To use this feature you have to implement board_spi_cs_gpio() to assign
 * a gpio value for each cs (-1 if cs doesn't need to use gpio).
 * You must use some unused on this SPI controller cs between 0 and 3.
 */
static int setup_cs_gpio(struct mxc_spi_slave *mxcs,
			 unsigned int bus, unsigned int cs)
{
	int ret;

	mxcs->gpio = board_spi_cs_gpio(bus, cs);
	if (mxcs->gpio == -1)
		return 0;

	gpio_request(mxcs->gpio, "spi-cs");
	ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol));
	if (ret) {
		printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
		return -EINVAL;
	}

	return 0;
}

static unsigned long spi_bases[] = {
	MXC_SPI_BASE_ADDRESSES
};

struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
			unsigned int max_hz, unsigned int mode)
{
	struct mxc_spi_slave *mxcs;
	int ret;

	if (bus >= ARRAY_SIZE(spi_bases))
		return NULL;

	if (max_hz == 0) {
		printf("Error: desired clock is 0\n");
		return NULL;
	}

	mxcs = spi_alloc_slave(struct mxc_spi_slave, bus, cs);
	if (!mxcs) {
		puts("mxc_spi: SPI Slave not allocated !\n");
		return NULL;
	}

	mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;

	ret = setup_cs_gpio(mxcs, bus, cs);
	if (ret < 0) {
		free(mxcs);
		return NULL;
	}

	mxcs->base = spi_bases[bus];
	mxcs->max_hz = max_hz;
	mxcs->mode = mode;

	return &mxcs->slave;
}

void spi_free_slave(struct spi_slave *slave)
{
	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);

	free(mxcs);
}

int spi_claim_bus(struct spi_slave *slave)
{
	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);

	return mxc_spi_claim_bus_internal(mxcs, slave->cs);
}

void spi_release_bus(struct spi_slave *slave)
{
	/* TODO: Shut the controller down */
}
#else

static int mxc_spi_probe(struct udevice *bus)
{
	struct mxc_spi_slave *mxcs = dev_get_plat(bus);
	int node = dev_of_offset(bus);
	const void *blob = gd->fdt_blob;
	int ret;
	int i;

	ret = gpio_request_list_by_name(bus, "cs-gpios", mxcs->cs_gpios,
					ARRAY_SIZE(mxcs->cs_gpios), 0);
	if (ret < 0) {
		pr_err("Can't get %s gpios! Error: %d", bus->name, ret);
		return ret;
	}

	for (i = 0; i < ARRAY_SIZE(mxcs->cs_gpios); i++) {
		if (!dm_gpio_is_valid(&mxcs->cs_gpios[i]))
			continue;

		ret = dm_gpio_set_dir_flags(&mxcs->cs_gpios[i],
					    GPIOD_IS_OUT | GPIOD_ACTIVE_LOW);
		if (ret) {
			dev_err(bus, "Setting cs %d error\n", i);
			return ret;
		}
	}

	mxcs->base = dev_read_addr(bus);
	if (mxcs->base == FDT_ADDR_T_NONE)
		return -ENODEV;

#if CONFIG_IS_ENABLED(CLK)
	struct clk clk;
	ret = clk_get_by_index(bus, 0, &clk);
	if (ret)
		return ret;

	clk_enable(&clk);

	mxcs->max_hz = clk_get_rate(&clk);
#else
	mxcs->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
				      20000000);
#endif

	return 0;
}

static int mxc_spi_xfer(struct udevice *dev, unsigned int bitlen,
		const void *dout, void *din, unsigned long flags)
{
	struct mxc_spi_slave *mxcs = dev_get_plat(dev->parent);


	return mxc_spi_xfer_internal(mxcs, bitlen, dout, din, flags);
}

static int mxc_spi_claim_bus(struct udevice *dev)
{
	struct mxc_spi_slave *mxcs = dev_get_plat(dev->parent);
	struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);

	mxcs->dev = dev;

	return mxc_spi_claim_bus_internal(mxcs, slave_plat->cs);
}

static int mxc_spi_release_bus(struct udevice *dev)
{
	return 0;
}

static int mxc_spi_set_speed(struct udevice *bus, uint speed)
{
	/* Nothing to do */
	return 0;
}

static int mxc_spi_set_mode(struct udevice *bus, uint mode)
{
	struct mxc_spi_slave *mxcs = dev_get_plat(bus);

	mxcs->mode = mode;
	mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;

	return 0;
}

static const struct dm_spi_ops mxc_spi_ops = {
	.claim_bus	= mxc_spi_claim_bus,
	.release_bus	= mxc_spi_release_bus,
	.xfer		= mxc_spi_xfer,
	.set_speed	= mxc_spi_set_speed,
	.set_mode	= mxc_spi_set_mode,
};

static const struct udevice_id mxc_spi_ids[] = {
	{ .compatible = "fsl,imx51-ecspi" },
	{ }
};

U_BOOT_DRIVER(mxc_spi) = {
	.name	= "mxc_spi",
	.id	= UCLASS_SPI,
	.of_match = mxc_spi_ids,
	.ops	= &mxc_spi_ops,
	.plat_auto	= sizeof(struct mxc_spi_slave),
	.probe	= mxc_spi_probe,
};
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
38254f45 GL	2	/*
38254f45 GL	3	* Copyright (C) 2008, Guennadi Liakhovetski <[email protected]>
38254f45 GL	4	*/
	5
	6	#include <common.h>
38b92ca1	7	#include <clk.h>
994266bd	8	#include <dm.h>
f7ae49fc	9	#include <log.h>
d255bb0e	10	#include <malloc.h>
38254f45	11	#include <spi.h>
401d1c4f	12	#include <asm/global_data.h>
336d4615	13	#include <dm/device_compat.h>
cd93d625	14	#include <linux/bitops.h>
c05ed00a	15	#include <linux/delay.h>
1221ce45	16	#include <linux/errno.h>
38254f45	17	#include <asm/io.h>
d8e0ca85	18	#include <asm/gpio.h>
86271115 SB	19	#include <asm/arch/imx-regs.h>
86271115 SB	20	#include <asm/arch/clock.h>
552a848e	21	#include <asm/mach-imx/spi.h>
38254f45	22
994266bd PF	23	DECLARE_GLOBAL_DATA_PTR;
994266bd PF	24
6cd4f48b MV	25	/* MX35 and older is CSPI */
	26	#if defined(CONFIG_MX25) \|\| defined(CONFIG_MX31) \|\| defined(CONFIG_MX35)
	27	#define MXC_CSPI
	28	struct cspi_regs {
	29	u32 rxdata;
	30	u32 txdata;
	31	u32 ctrl;
	32	u32 intr;
	33	u32 dma;
	34	u32 stat;
	35	u32 period;
	36	u32 test;
	37	};
	38
	39	#define MXC_CSPICTRL_EN BIT(0)
	40	#define MXC_CSPICTRL_MODE BIT(1)
	41	#define MXC_CSPICTRL_XCH BIT(2)
	42	#define MXC_CSPICTRL_SMC BIT(3)
	43	#define MXC_CSPICTRL_POL BIT(4)
	44	#define MXC_CSPICTRL_PHA BIT(5)
	45	#define MXC_CSPICTRL_SSCTL BIT(6)
	46	#define MXC_CSPICTRL_SSPOL BIT(7)
	47	#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
	48	#define MXC_CSPICTRL_RXOVF BIT(6)
	49	#define MXC_CSPIPERIOD_32KHZ BIT(15)
	50	#define MAX_SPI_BYTES 4
	51	#if defined(CONFIG_MX25) \|\| defined(CONFIG_MX35)
	52	#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
	53	#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
	54	#define MXC_CSPICTRL_TC BIT(7)
	55	#define MXC_CSPICTRL_MAXBITS 0xfff
	56	#else /* MX31 */
	57	#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24)
	58	#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8)
	59	#define MXC_CSPICTRL_TC BIT(8)
	60	#define MXC_CSPICTRL_MAXBITS 0x1f
	61	#endif
	62
	63	#else /* MX51 and newer is ECSPI */
	64	#define MXC_ECSPI
	65	struct cspi_regs {
	66	u32 rxdata;
	67	u32 txdata;
	68	u32 ctrl;
	69	u32 cfg;
	70	u32 intr;
	71	u32 dma;
	72	u32 stat;
	73	u32 period;
	74	};
	75
	76	#define MXC_CSPICTRL_EN BIT(0)
	77	#define MXC_CSPICTRL_MODE BIT(1)
	78	#define MXC_CSPICTRL_XCH BIT(2)
	79	#define MXC_CSPICTRL_MODE_MASK (0xf << 4)
	80	#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
	81	#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
	82	#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
	83	#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
	84	#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
	85	#define MXC_CSPICTRL_MAXBITS 0xfff
	86	#define MXC_CSPICTRL_TC BIT(7)
	87	#define MXC_CSPICTRL_RXOVF BIT(6)
	88	#define MXC_CSPIPERIOD_32KHZ BIT(15)
89	#define MAX_SPI_BYTES 32
90
91	/* Bit position inside CTRL register to be associated with SS */
92	#define MXC_CSPICTRL_CHAN 18
93
94	/* Bit position inside CON register to be associated with SS */
95	#define MXC_CSPICON_PHA 0 /* SCLK phase control */
96	#define MXC_CSPICON_POL 4 /* SCLK polarity */
97	#define MXC_CSPICON_SSPOL 12 /* SS polarity */
98	#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
99	#endif
100
38254f45 GL	101	#ifdef CONFIG_MX27
	102	/* i.MX27 has a completely wrong register layout and register definitions in the
	103	* datasheet, the correct one is in the Freescale's Linux driver */
	104
61a58a16	105	#error "i.MX27 CSPI not supported due to drastic differences in register definitions" \
38254f45	106	"See linux mxc_spi driver from Freescale for details."
08c61a58	107	#endif
c9d59c7f	108
155fa9af NK	109	__weak int board_spi_cs_gpio(unsigned bus, unsigned cs)
	110	{
	111	return -1;
	112	}
	113
c4ea1424 SB	114	#define OUT MXC_GPIO_DIRECTION_OUT
c4ea1424 SB	115
ac87c17d SB	116	#define reg_read readl
	117	#define reg_write(a, v) writel(v, a)
	118
f659b573 HS	119	#if !defined(CONFIG_SYS_SPI_MXC_WAIT)
	120	#define CONFIG_SYS_SPI_MXC_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */
	121	#endif
	122
7a3faf31 HS	123	#define MAX_CS_COUNT 4
7a3faf31 HS	124
d255bb0e HS	125	struct mxc_spi_slave {
	126	struct spi_slave slave;
	127	unsigned long base;
	128	u32 ctrl_reg;
08c61a58	129	#if defined(MXC_ECSPI)
d205ddcf SB	130	u32 cfg_reg;
d205ddcf SB	131	#endif
fc7a93c8	132	int gpio;
c4ea1424	133	int ss_pol;
027a9a00 MN	134	unsigned int max_hz;
027a9a00 MN	135	unsigned int mode;
994266bd	136	struct gpio_desc ss;
7a3faf31 HS	137	struct gpio_desc cs_gpios[MAX_CS_COUNT];
7a3faf31 HS	138	struct udevice *dev;
38254f45	139	};
d255bb0e HS	140
	141	static inline struct mxc_spi_slave to_mxc_spi_slave(struct spi_slave slave)
	142	{
	143	return container_of(slave, struct mxc_spi_slave, slave);
	144	}
38254f45	145
994266bd	146	static void mxc_spi_cs_activate(struct mxc_spi_slave *mxcs)
d205ddcf	147	{
56c40460	148	#if CONFIG_IS_ENABLED(DM_SPI)
7a3faf31	149	struct udevice *dev = mxcs->dev;
8a8d24bd	150	struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
7a3faf31 HS	151
	152	u32 cs = slave_plat->cs;
	153
	154	if (!dm_gpio_is_valid(&mxcs->cs_gpios[cs]))
	155	return;
	156
	157	dm_gpio_set_value(&mxcs->cs_gpios[cs], 1);
	158	#else
	159	if (mxcs->gpio > 0)
	160	gpio_set_value(mxcs->gpio, mxcs->ss_pol);
	161	#endif
d205ddcf SB	162	}
d205ddcf SB	163
994266bd	164	static void mxc_spi_cs_deactivate(struct mxc_spi_slave *mxcs)
d205ddcf	165	{
56c40460	166	#if CONFIG_IS_ENABLED(DM_SPI)
7a3faf31	167	struct udevice *dev = mxcs->dev;
8a8d24bd	168	struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
7a3faf31 HS	169
	170	u32 cs = slave_plat->cs;
	171
	172	if (!dm_gpio_is_valid(&mxcs->cs_gpios[cs]))
	173	return;
	174
	175	dm_gpio_set_value(&mxcs->cs_gpios[cs], 0);
	176	#else
	177	if (mxcs->gpio > 0)
	178	gpio_set_value(mxcs->gpio, !(mxcs->ss_pol));
	179	#endif
d205ddcf SB	180	}
d205ddcf SB	181
afaa9f65 AG	182	u32 get_cspi_div(u32 div)
	183	{
	184	int i;
	185
	186	for (i = 0; i < 8; i++) {
	187	if (div <= (4 << i))
	188	return i;
	189	}
	190	return i;
	191	}
	192
08c61a58	193	#ifdef MXC_CSPI
027a9a00	194	static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
c9d59c7f SB	195	{
c9d59c7f SB	196	unsigned int ctrl_reg;
afaa9f65 AG	197	u32 clk_src;
afaa9f65 AG	198	u32 div;
027a9a00 MN	199	unsigned int max_hz = mxcs->max_hz;
027a9a00 MN	200	unsigned int mode = mxcs->mode;
afaa9f65 AG	201
	202	clk_src = mxc_get_clock(MXC_CSPI_CLK);
	203
cd200403	204	div = DIV_ROUND_UP(clk_src, max_hz);
afaa9f65 AG	205	div = get_cspi_div(div);
	206
	207	debug("clk %d Hz, div %d, real clk %d Hz\n",
	208	max_hz, div, clk_src / (4 << div));
c9d59c7f SB	209
	210	ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) \|
	211	MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) \|
afaa9f65	212	MXC_CSPICTRL_DATARATE(div) \|
c9d59c7f SB	213	MXC_CSPICTRL_EN \|
	214	#ifdef CONFIG_MX35
	215	MXC_CSPICTRL_SSCTL \|
	216	#endif
	217	MXC_CSPICTRL_MODE;
	218
	219	if (mode & SPI_CPHA)
	220	ctrl_reg \|= MXC_CSPICTRL_PHA;
	221	if (mode & SPI_CPOL)
	222	ctrl_reg \|= MXC_CSPICTRL_POL;
	223	if (mode & SPI_CS_HIGH)
	224	ctrl_reg \|= MXC_CSPICTRL_SSPOL;
	225	mxcs->ctrl_reg = ctrl_reg;
	226
	227	return 0;
	228	}
	229	#endif
	230
08c61a58	231	#ifdef MXC_ECSPI
027a9a00	232	static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
d205ddcf SB	233	{
d205ddcf SB	234	u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
9a30903b	235	s32 reg_ctrl, reg_config;
5d584cce MN	236	u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0;
5d584cce MN	237	u32 pre_div = 0, post_div = 0;
ac87c17d	238	struct cspi_regs regs = (struct cspi_regs )mxcs->base;
027a9a00 MN	239	unsigned int max_hz = mxcs->max_hz;
027a9a00 MN	240	unsigned int mode = mxcs->mode;
d205ddcf	241
0f1411bc FE	242	/*
	243	* Reset SPI and set all CSs to master mode, if toggling
	244	* between slave and master mode we might see a glitch
	245	* on the clock line
	246	*/
	247	reg_ctrl = MXC_CSPICTRL_MODE_MASK;
	248	reg_write(&regs->ctrl, reg_ctrl);
	249	reg_ctrl \|= MXC_CSPICTRL_EN;
	250	reg_write(&regs->ctrl, reg_ctrl);
d205ddcf	251
d205ddcf	252	if (clk_src > max_hz) {
9a30903b DB	253	pre_div = (clk_src - 1) / max_hz;
	254	/* fls(1) = 1, fls(0x80000000) = 32, fls(16) = 5 */
	255	post_div = fls(pre_div);
	256	if (post_div > 4) {
	257	post_div -= 4;
	258	if (post_div >= 16) {
d205ddcf SB	259	printf("Error: no divider for the freq: %d\n",
	260	max_hz);
	261	return -1;
	262	}
9a30903b DB	263	pre_div >>= post_div;
	264	} else {
	265	post_div = 0;
d205ddcf SB	266	}
	267	}
	268
	269	debug("pre_div = %d, post_div=%d\n", pre_div, post_div);
	270	reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) \|
	271	MXC_CSPICTRL_SELCHAN(cs);
	272	reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) \|
	273	MXC_CSPICTRL_PREDIV(pre_div);
	274	reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) \|
	275	MXC_CSPICTRL_POSTDIV(post_div);
	276
d205ddcf SB	277	if (mode & SPI_CS_HIGH)
	278	ss_pol = 1;
	279
5d584cce	280	if (mode & SPI_CPOL) {
d205ddcf	281	sclkpol = 1;
5d584cce MN	282	sclkctl = 1;
5d584cce MN	283	}
d205ddcf SB	284
	285	if (mode & SPI_CPHA)
	286	sclkpha = 1;
	287
ac87c17d	288	reg_config = reg_read(&regs->cfg);
d205ddcf SB	289
	290	/*
	291	* Configuration register setup
c9d59c7f	292	* The MX51 supports different setup for each SS
d205ddcf SB	293	*/
	294	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) \|
	295	(ss_pol << (cs + MXC_CSPICON_SSPOL));
	296	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) \|
	297	(sclkpol << (cs + MXC_CSPICON_POL));
5d584cce MN	298	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_CTL))) \|
5d584cce MN	299	(sclkctl << (cs + MXC_CSPICON_CTL));
d205ddcf SB	300	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) \|
	301	(sclkpha << (cs + MXC_CSPICON_PHA));
	302
	303	debug("reg_ctrl = 0x%x\n", reg_ctrl);
ac87c17d	304	reg_write(&regs->ctrl, reg_ctrl);
d205ddcf	305	debug("reg_config = 0x%x\n", reg_config);
ac87c17d	306	reg_write(&regs->cfg, reg_config);
d205ddcf SB	307
	308	/* save config register and control register */
	309	mxcs->ctrl_reg = reg_ctrl;
	310	mxcs->cfg_reg = reg_config;
	311
	312	/* clear interrupt reg */
ac87c17d SB	313	reg_write(&regs->intr, 0);
ac87c17d SB	314	reg_write(&regs->stat, MXC_CSPICTRL_TC \| MXC_CSPICTRL_RXOVF);
d205ddcf SB	315
	316	return 0;
	317	}
	318	#endif
	319
994266bd	320	int spi_xchg_single(struct mxc_spi_slave *mxcs, unsigned int bitlen,
2f721d17	321	const u8 dout, u8 din, unsigned long flags)
38254f45	322	{
9675fed4	323	int nbytes = DIV_ROUND_UP(bitlen, 8);
2f721d17	324	u32 data, cnt, i;
ac87c17d	325	struct cspi_regs regs = (struct cspi_regs )mxcs->base;
f659b573 HS	326	u32 ts;
f659b573 HS	327	int status;
38254f45	328
65a106e3 YL	329	debug("%s: bitlen %d dout 0x%lx din 0x%lx\n",
65a106e3 YL	330	__func__, bitlen, (ulong)dout, (ulong)din);
d205ddcf SB	331
	332	mxcs->ctrl_reg = (mxcs->ctrl_reg &
	333	~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) \|
f9b6a157	334	MXC_CSPICTRL_BITCOUNT(bitlen - 1);
38254f45	335
ac87c17d	336	reg_write(&regs->ctrl, mxcs->ctrl_reg \| MXC_CSPICTRL_EN);
08c61a58	337	#ifdef MXC_ECSPI
ac87c17d	338	reg_write(&regs->cfg, mxcs->cfg_reg);
d205ddcf	339	#endif
38254f45	340
d205ddcf	341	/* Clear interrupt register */
ac87c17d	342	reg_write(&regs->stat, MXC_CSPICTRL_TC \| MXC_CSPICTRL_RXOVF);
fc7a93c8	343
2f721d17 SB	344	/*
	345	* The SPI controller works only with words,
	346	* check if less than a word is sent.
	347	* Access to the FIFO is only 32 bit
	348	*/
	349	if (bitlen % 32) {
	350	data = 0;
	351	cnt = (bitlen % 32) / 8;
	352	if (dout) {
	353	for (i = 0; i < cnt; i++) {
	354	data = (data << 8) \| (*dout++ & 0xFF);
	355	}
	356	}
	357	debug("Sending SPI 0x%x\n", data);
	358
ac87c17d	359	reg_write(&regs->txdata, data);
2f721d17 SB	360	nbytes -= cnt;
	361	}
	362
	363	data = 0;
	364
	365	while (nbytes > 0) {
	366	data = 0;
	367	if (dout) {
	368	/* Buffer is not 32-bit aligned */
	369	if ((unsigned long)dout & 0x03) {
	370	data = 0;
dff01094	371	for (i = 0; i < 4; i++)
2f721d17	372	data = (data << 8) \| (*dout++ & 0xFF);
2f721d17 SB	373	} else {
	374	data = (u32 )dout;
	375	data = cpu_to_be32(data);
6d5ce1bd	376	dout += 4;
2f721d17	377	}
2f721d17 SB	378	}
2f721d17 SB	379	debug("Sending SPI 0x%x\n", data);
ac87c17d	380	reg_write(&regs->txdata, data);
2f721d17 SB	381	nbytes -= 4;
2f721d17 SB	382	}
38254f45	383
d205ddcf	384	/* FIFO is written, now starts the transfer setting the XCH bit */
ac87c17d	385	reg_write(&regs->ctrl, mxcs->ctrl_reg \|
d205ddcf	386	MXC_CSPICTRL_EN \| MXC_CSPICTRL_XCH);
38254f45	387
f659b573 HS	388	ts = get_timer(0);
f659b573 HS	389	status = reg_read(&regs->stat);
d205ddcf	390	/* Wait until the TC (Transfer completed) bit is set */
f659b573 HS	391	while ((status & MXC_CSPICTRL_TC) == 0) {
	392	if (get_timer(ts) > CONFIG_SYS_SPI_MXC_WAIT) {
	393	printf("spi_xchg_single: Timeout!\n");
	394	return -1;
	395	}
	396	status = reg_read(&regs->stat);
	397	}
38254f45	398
d205ddcf	399	/* Transfer completed, clear any pending request */
ac87c17d	400	reg_write(&regs->stat, MXC_CSPICTRL_TC \| MXC_CSPICTRL_RXOVF);
d205ddcf	401
9675fed4	402	nbytes = DIV_ROUND_UP(bitlen, 8);
d205ddcf	403
2f721d17	404	cnt = nbytes % 32;
d205ddcf	405
2f721d17	406	if (bitlen % 32) {
ac87c17d	407	data = reg_read(&regs->rxdata);
2f721d17	408	cnt = (bitlen % 32) / 8;
dff01094	409	data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8);
2f721d17 SB	410	debug("SPI Rx unaligned: 0x%x\n", data);
2f721d17 SB	411	if (din) {
dff01094 AG	412	memcpy(din, &data, cnt);
dff01094 AG	413	din += cnt;
2f721d17 SB	414	}
	415	nbytes -= cnt;
	416	}
	417
	418	while (nbytes > 0) {
	419	u32 tmp;
ac87c17d	420	tmp = reg_read(&regs->rxdata);
2f721d17 SB	421	data = cpu_to_be32(tmp);
2f721d17 SB	422	debug("SPI Rx: 0x%x 0x%x\n", tmp, data);
b4141195	423	cnt = min_t(u32, nbytes, sizeof(data));
2f721d17 SB	424	if (din) {
	425	memcpy(din, &data, cnt);
	426	din += cnt;
	427	}
	428	nbytes -= cnt;
	429	}
	430
	431	return 0;
fc7a93c8	432
38254f45 GL	433	}
38254f45 GL	434
994266bd PF	435	static int mxc_spi_xfer_internal(struct mxc_spi_slave *mxcs,
	436	unsigned int bitlen, const void *dout,
	437	void *din, unsigned long flags)
38254f45	438	{
9675fed4	439	int n_bytes = DIV_ROUND_UP(bitlen, 8);
2f721d17 SB	440	int n_bits;
	441	int ret;
	442	u32 blk_size;
	443	u8 p_outbuf = (u8 )dout;
	444	u8 p_inbuf = (u8 )din;
38254f45	445
994266bd PF	446	if (!mxcs)
994266bd PF	447	return -EINVAL;
38254f45	448
2f721d17	449	if (flags & SPI_XFER_BEGIN)
994266bd	450	mxc_spi_cs_activate(mxcs);
2f721d17 SB	451
2f721d17 SB	452	while (n_bytes > 0) {
2f721d17 SB	453	if (n_bytes < MAX_SPI_BYTES)
	454	blk_size = n_bytes;
	455	else
	456	blk_size = MAX_SPI_BYTES;
	457
	458	n_bits = blk_size * 8;
	459
994266bd	460	ret = spi_xchg_single(mxcs, n_bits, p_outbuf, p_inbuf, 0);
2f721d17 SB	461
	462	if (ret)
	463	return ret;
	464	if (dout)
	465	p_outbuf += blk_size;
	466	if (din)
	467	p_inbuf += blk_size;
	468	n_bytes -= blk_size;
eff536be ML	469	}
eff536be ML	470
2f721d17	471	if (flags & SPI_XFER_END) {
994266bd	472	mxc_spi_cs_deactivate(mxcs);
f9b6a157	473	}
38254f45 GL	474
	475	return 0;
	476	}
	477
994266bd PF	478	static int mxc_spi_claim_bus_internal(struct mxc_spi_slave *mxcs, int cs)
	479	{
	480	struct cspi_regs regs = (struct cspi_regs )mxcs->base;
	481	int ret;
	482
	483	reg_write(&regs->rxdata, 1);
	484	udelay(1);
	485	ret = spi_cfg_mxc(mxcs, cs);
	486	if (ret) {
	487	printf("mxc_spi: cannot setup SPI controller\n");
	488	return ret;
	489	}
	490	reg_write(&regs->period, MXC_CSPIPERIOD_32KHZ);
	491	reg_write(&regs->intr, 0);
	492
	493	return 0;
	494	}
	495
56c40460	496	#if !CONFIG_IS_ENABLED(DM_SPI)
994266bd PF	497	int spi_xfer(struct spi_slave slave, unsigned int bitlen, const void dout,
	498	void *din, unsigned long flags)
	499	{
	500	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
	501
	502	return mxc_spi_xfer_internal(mxcs, bitlen, dout, din, flags);
	503	}
	504
155fa9af NK	505	/*
	506	* Some SPI devices require active chip-select over multiple
	507	* transactions, we achieve this using a GPIO. Still, the SPI
	508	* controller has to be configured to use one of its own chipselects.
	509	* To use this feature you have to implement board_spi_cs_gpio() to assign
	510	* a gpio value for each cs (-1 if cs doesn't need to use gpio).
	511	* You must use some unused on this SPI controller cs between 0 and 3.
	512	*/
	513	static int setup_cs_gpio(struct mxc_spi_slave *mxcs,
	514	unsigned int bus, unsigned int cs)
fc7a93c8 GL	515	{
	516	int ret;
	517
155fa9af NK	518	mxcs->gpio = board_spi_cs_gpio(bus, cs);
	519	if (mxcs->gpio == -1)
	520	return 0;
	521
994266bd	522	gpio_request(mxcs->gpio, "spi-cs");
155fa9af NK	523	ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol));
	524	if (ret) {
	525	printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
	526	return -EINVAL;
fc7a93c8 GL	527	}
fc7a93c8 GL	528
155fa9af	529	return 0;
fc7a93c8 GL	530	}
fc7a93c8 GL	531
994266bd PF	532	static unsigned long spi_bases[] = {
	533	MXC_SPI_BASE_ADDRESSES
	534	};
	535
d255bb0e HS	536	struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
d255bb0e HS	537	unsigned int max_hz, unsigned int mode)
38254f45	538	{
d255bb0e	539	struct mxc_spi_slave *mxcs;
fc7a93c8 GL	540	int ret;
	541
	542	if (bus >= ARRAY_SIZE(spi_bases))
	543	return NULL;
	544
027a9a00 MN	545	if (max_hz == 0) {
	546	printf("Error: desired clock is 0\n");
	547	return NULL;
	548	}
	549
d3504fee	550	mxcs = spi_alloc_slave(struct mxc_spi_slave, bus, cs);
2f721d17 SB	551	if (!mxcs) {
2f721d17 SB	552	puts("mxc_spi: SPI Slave not allocated !\n");
fc7a93c8	553	return NULL;
2f721d17	554	}
38254f45	555
de5bf02c FE	556	mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
de5bf02c FE	557
155fa9af	558	ret = setup_cs_gpio(mxcs, bus, cs);
fc7a93c8 GL	559	if (ret < 0) {
fc7a93c8 GL	560	free(mxcs);
d255bb0e	561	return NULL;
fc7a93c8 GL	562	}
fc7a93c8 GL	563
d205ddcf	564	mxcs->base = spi_bases[bus];
027a9a00 MN	565	mxcs->max_hz = max_hz;
027a9a00 MN	566	mxcs->mode = mode;
d205ddcf	567
d255bb0e HS	568	return &mxcs->slave;
	569	}
	570
	571	void spi_free_slave(struct spi_slave *slave)
	572	{
f9b6a157 GL	573	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
	574
	575	free(mxcs);
d255bb0e HS	576	}
	577
	578	int spi_claim_bus(struct spi_slave *slave)
	579	{
	580	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
	581
994266bd PF	582	return mxc_spi_claim_bus_internal(mxcs, slave->cs);
	583	}
	584
	585	void spi_release_bus(struct spi_slave *slave)
	586	{
	587	/* TODO: Shut the controller down */
	588	}
	589	#else
	590
	591	static int mxc_spi_probe(struct udevice *bus)
	592	{
c69cda25	593	struct mxc_spi_slave *mxcs = dev_get_plat(bus);
994266bd PF	594	int node = dev_of_offset(bus);
	595	const void *blob = gd->fdt_blob;
	596	int ret;
7a3faf31	597	int i;
994266bd	598
7a3faf31 HS	599	ret = gpio_request_list_by_name(bus, "cs-gpios", mxcs->cs_gpios,
	600	ARRAY_SIZE(mxcs->cs_gpios), 0);
	601	if (ret < 0) {
	602	pr_err("Can't get %s gpios! Error: %d", bus->name, ret);
	603	return ret;
	604	}
	605
	606	for (i = 0; i < ARRAY_SIZE(mxcs->cs_gpios); i++) {
	607	if (!dm_gpio_is_valid(&mxcs->cs_gpios[i]))
	608	continue;
	609
	610	ret = dm_gpio_set_dir_flags(&mxcs->cs_gpios[i],
	611	GPIOD_IS_OUT \| GPIOD_ACTIVE_LOW);
	612	if (ret) {
	613	dev_err(bus, "Setting cs %d error\n", i);
	614	return ret;
	615	}
994266bd PF	616	}
994266bd PF	617
2548493a	618	mxcs->base = dev_read_addr(bus);
2b849e1f	619	if (mxcs->base == FDT_ADDR_T_NONE)
994266bd PF	620	return -ENODEV;
994266bd PF	621
38b92ca1 MV	622	#if CONFIG_IS_ENABLED(CLK)
	623	struct clk clk;
	624	ret = clk_get_by_index(bus, 0, &clk);
	625	if (ret)
	626	return ret;
	627
	628	clk_enable(&clk);
	629
	630	mxcs->max_hz = clk_get_rate(&clk);
	631	#else
994266bd PF	632	mxcs->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
994266bd PF	633	20000000);
38b92ca1	634	#endif
38254f45 GL	635
	636	return 0;
	637	}
d255bb0e	638
994266bd PF	639	static int mxc_spi_xfer(struct udevice *dev, unsigned int bitlen,
994266bd PF	640	const void dout, void din, unsigned long flags)
d255bb0e	641	{
c69cda25	642	struct mxc_spi_slave *mxcs = dev_get_plat(dev->parent);
994266bd PF	643
	644
	645	return mxc_spi_xfer_internal(mxcs, bitlen, dout, din, flags);
	646	}
	647
	648	static int mxc_spi_claim_bus(struct udevice *dev)
	649	{
c69cda25	650	struct mxc_spi_slave *mxcs = dev_get_plat(dev->parent);
8a8d24bd	651	struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
994266bd	652
7a3faf31 HS	653	mxcs->dev = dev;
7a3faf31 HS	654
994266bd	655	return mxc_spi_claim_bus_internal(mxcs, slave_plat->cs);
d255bb0e	656	}
994266bd PF	657
	658	static int mxc_spi_release_bus(struct udevice *dev)
	659	{
	660	return 0;
	661	}
	662
	663	static int mxc_spi_set_speed(struct udevice *bus, uint speed)
	664	{
	665	/* Nothing to do */
	666	return 0;
	667	}
	668
	669	static int mxc_spi_set_mode(struct udevice *bus, uint mode)
	670	{
c69cda25	671	struct mxc_spi_slave *mxcs = dev_get_plat(bus);
994266bd PF	672
	673	mxcs->mode = mode;
	674	mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
	675
	676	return 0;
	677	}
	678
	679	static const struct dm_spi_ops mxc_spi_ops = {
	680	.claim_bus = mxc_spi_claim_bus,
	681	.release_bus = mxc_spi_release_bus,
	682	.xfer = mxc_spi_xfer,
	683	.set_speed = mxc_spi_set_speed,
	684	.set_mode = mxc_spi_set_mode,
	685	};
	686
	687	static const struct udevice_id mxc_spi_ids[] = {
	688	{ .compatible = "fsl,imx51-ecspi" },
	689	{ }
	690	};
	691
	692	U_BOOT_DRIVER(mxc_spi) = {
	693	.name = "mxc_spi",
	694	.id = UCLASS_SPI,
	695	.of_match = mxc_spi_ids,
	696	.ops = &mxc_spi_ops,
caa4daa2	697	.plat_auto = sizeof(struct mxc_spi_slave),
994266bd PF	698	.probe = mxc_spi_probe,
	699	};
	700	#endif