[u-boot.git] / drivers / spi / mxc_spi.c

/*
 * Copyright (C) 2008, Guennadi Liakhovetski <[email protected]>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 */

#include <common.h>
#include <malloc.h>
#include <spi.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>

#ifdef CONFIG_MX27
/* i.MX27 has a completely wrong register layout and register definitions in the
 * datasheet, the correct one is in the Freescale's Linux driver */

#error "i.MX27 CSPI not supported due to drastic differences in register definitions" \
"See linux mxc_spi driver from Freescale for details."
#endif

static unsigned long spi_bases[] = {
	MXC_SPI_BASE_ADDRESSES
};

#define OUT	MXC_GPIO_DIRECTION_OUT

#define reg_read readl
#define reg_write(a, v) writel(v, a)

struct mxc_spi_slave {
	struct spi_slave slave;
	unsigned long	base;
	u32		ctrl_reg;
#if defined(MXC_ECSPI)
	u32		cfg_reg;
#endif
	int		gpio;
	int		ss_pol;
};

static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
{
	return container_of(slave, struct mxc_spi_slave, slave);
}

void spi_cs_activate(struct spi_slave *slave)
{
	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
	if (mxcs->gpio > 0)
		gpio_set_value(mxcs->gpio, mxcs->ss_pol);
}

void spi_cs_deactivate(struct spi_slave *slave)
{
	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
	if (mxcs->gpio > 0)
		gpio_set_value(mxcs->gpio,
			      !(mxcs->ss_pol));
}

u32 get_cspi_div(u32 div)
{
	int i;

	for (i = 0; i < 8; i++) {
		if (div <= (4 << i))
			return i;
	}
	return i;
}

#ifdef MXC_CSPI
static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
		unsigned int max_hz, unsigned int mode)
{
	unsigned int ctrl_reg;
	u32 clk_src;
	u32 div;

	clk_src = mxc_get_clock(MXC_CSPI_CLK);

	div = DIV_ROUND_UP(clk_src, max_hz);
	div = get_cspi_div(div);

	debug("clk %d Hz, div %d, real clk %d Hz\n",
		max_hz, div, clk_src / (4 << div));

	ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) |
		MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) |
		MXC_CSPICTRL_DATARATE(div) |
		MXC_CSPICTRL_EN |
#ifdef CONFIG_MX35
		MXC_CSPICTRL_SSCTL |
#endif
		MXC_CSPICTRL_MODE;

	if (mode & SPI_CPHA)
		ctrl_reg |= MXC_CSPICTRL_PHA;
	if (mode & SPI_CPOL)
		ctrl_reg |= MXC_CSPICTRL_POL;
	if (mode & SPI_CS_HIGH)
		ctrl_reg |= MXC_CSPICTRL_SSPOL;
	mxcs->ctrl_reg = ctrl_reg;

	return 0;
}
#endif

#ifdef MXC_ECSPI
static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
		unsigned int max_hz, unsigned int mode)
{
	u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
	s32 pre_div = 0, post_div = 0, i, reg_ctrl, reg_config;
	u32 ss_pol = 0, sclkpol = 0, sclkpha = 0;
	struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;

	if (max_hz == 0) {
		printf("Error: desired clock is 0\n");
		return -1;
	}

	/*
	 * Reset SPI and set all CSs to master mode, if toggling
	 * between slave and master mode we might see a glitch
	 * on the clock line
	 */
	reg_ctrl = MXC_CSPICTRL_MODE_MASK;
	reg_write(&regs->ctrl, reg_ctrl);
	reg_ctrl |=  MXC_CSPICTRL_EN;
	reg_write(&regs->ctrl, reg_ctrl);

	/*
	 * The following computation is taken directly from Freescale's code.
	 */
	if (clk_src > max_hz) {
		pre_div = DIV_ROUND_UP(clk_src, max_hz);
		if (pre_div > 16) {
			post_div = pre_div / 16;
			pre_div = 15;
		}
		if (post_div != 0) {
			for (i = 0; i < 16; i++) {
				if ((1 << i) >= post_div)
					break;
			}
			if (i == 16) {
				printf("Error: no divider for the freq: %d\n",
					max_hz);
				return -1;
			}
			post_div = i;
		}
	}

	debug("pre_div = %d, post_div=%d\n", pre_div, post_div);
	reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) |
		MXC_CSPICTRL_SELCHAN(cs);
	reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) |
		MXC_CSPICTRL_PREDIV(pre_div);
	reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) |
		MXC_CSPICTRL_POSTDIV(post_div);

	/* We need to disable SPI before changing registers */
	reg_ctrl &= ~MXC_CSPICTRL_EN;

	if (mode & SPI_CS_HIGH)
		ss_pol = 1;

	if (mode & SPI_CPOL)
		sclkpol = 1;

	if (mode & SPI_CPHA)
		sclkpha = 1;

	reg_config = reg_read(&regs->cfg);

	/*
	 * Configuration register setup
	 * The MX51 supports different setup for each SS
	 */
	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) |
		(ss_pol << (cs + MXC_CSPICON_SSPOL));
	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) |
		(sclkpol << (cs + MXC_CSPICON_POL));
	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) |
		(sclkpha << (cs + MXC_CSPICON_PHA));

	debug("reg_ctrl = 0x%x\n", reg_ctrl);
	reg_write(&regs->ctrl, reg_ctrl);
	debug("reg_config = 0x%x\n", reg_config);
	reg_write(&regs->cfg, reg_config);

	/* save config register and control register */
	mxcs->ctrl_reg = reg_ctrl;
	mxcs->cfg_reg = reg_config;

	/* clear interrupt reg */
	reg_write(&regs->intr, 0);
	reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);

	return 0;
}
#endif

int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen,
	const u8 *dout, u8 *din, unsigned long flags)
{
	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
	int nbytes = (bitlen + 7) / 8;
	u32 data, cnt, i;
	struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;

	debug("%s: bitlen %d dout 0x%x din 0x%x\n",
		__func__, bitlen, (u32)dout, (u32)din);

	mxcs->ctrl_reg = (mxcs->ctrl_reg &
		~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) |
		MXC_CSPICTRL_BITCOUNT(bitlen - 1);

	reg_write(&regs->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN);
#ifdef MXC_ECSPI
	reg_write(&regs->cfg, mxcs->cfg_reg);
#endif

	/* Clear interrupt register */
	reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);

	/*
	 * The SPI controller works only with words,
	 * check if less than a word is sent.
	 * Access to the FIFO is only 32 bit
	 */
	if (bitlen % 32) {
		data = 0;
		cnt = (bitlen % 32) / 8;
		if (dout) {
			for (i = 0; i < cnt; i++) {
				data = (data << 8) | (*dout++ & 0xFF);
			}
		}
		debug("Sending SPI 0x%x\n", data);

		reg_write(&regs->txdata, data);
		nbytes -= cnt;
	}

	data = 0;

	while (nbytes > 0) {
		data = 0;
		if (dout) {
			/* Buffer is not 32-bit aligned */
			if ((unsigned long)dout & 0x03) {
				data = 0;
				for (i = 0; i < 4; i++)
					data = (data << 8) | (*dout++ & 0xFF);
			} else {
				data = *(u32 *)dout;
				data = cpu_to_be32(data);
			}
			dout += 4;
		}
		debug("Sending SPI 0x%x\n", data);
		reg_write(&regs->txdata, data);
		nbytes -= 4;
	}

	/* FIFO is written, now starts the transfer setting the XCH bit */
	reg_write(&regs->ctrl, mxcs->ctrl_reg |
		MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH);

	/* Wait until the TC (Transfer completed) bit is set */
	while ((reg_read(&regs->stat) & MXC_CSPICTRL_TC) == 0)
		;

	/* Transfer completed, clear any pending request */
	reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);

	nbytes = (bitlen + 7) / 8;

	cnt = nbytes % 32;

	if (bitlen % 32) {
		data = reg_read(&regs->rxdata);
		cnt = (bitlen % 32) / 8;
		data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8);
		debug("SPI Rx unaligned: 0x%x\n", data);
		if (din) {
			memcpy(din, &data, cnt);
			din += cnt;
		}
		nbytes -= cnt;
	}

	while (nbytes > 0) {
		u32 tmp;
		tmp = reg_read(&regs->rxdata);
		data = cpu_to_be32(tmp);
		debug("SPI Rx: 0x%x 0x%x\n", tmp, data);
		cnt = min(nbytes, sizeof(data));
		if (din) {
			memcpy(din, &data, cnt);
			din += cnt;
		}
		nbytes -= cnt;
	}

	return 0;

}

int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
		void *din, unsigned long flags)
{
	int n_bytes = (bitlen + 7) / 8;
	int n_bits;
	int ret;
	u32 blk_size;
	u8 *p_outbuf = (u8 *)dout;
	u8 *p_inbuf = (u8 *)din;

	if (!slave)
		return -1;

	if (flags & SPI_XFER_BEGIN)
		spi_cs_activate(slave);

	while (n_bytes > 0) {
		if (n_bytes < MAX_SPI_BYTES)
			blk_size = n_bytes;
		else
			blk_size = MAX_SPI_BYTES;

		n_bits = blk_size * 8;

		ret = spi_xchg_single(slave, n_bits, p_outbuf, p_inbuf, 0);

		if (ret)
			return ret;
		if (dout)
			p_outbuf += blk_size;
		if (din)
			p_inbuf += blk_size;
		n_bytes -= blk_size;
	}

	if (flags & SPI_XFER_END) {
		spi_cs_deactivate(slave);
	}

	return 0;
}

void spi_init(void)
{
}

static int decode_cs(struct mxc_spi_slave *mxcs, unsigned int cs)
{
	int ret;

	/*
	 * Some SPI devices require active chip-select over multiple
	 * transactions, we achieve this using a GPIO. Still, the SPI
	 * controller has to be configured to use one of its own chipselects.
	 * To use this feature you have to call spi_setup_slave() with
	 * cs = internal_cs | (gpio << 8), and you have to use some unused
	 * on this SPI controller cs between 0 and 3.
	 */
	if (cs > 3) {
		mxcs->gpio = cs >> 8;
		cs &= 3;
		ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol));
		if (ret) {
			printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
			return -EINVAL;
		}
	} else {
		mxcs->gpio = -1;
	}

	return cs;
}

struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
			unsigned int max_hz, unsigned int mode)
{
	struct mxc_spi_slave *mxcs;
	int ret;

	if (bus >= ARRAY_SIZE(spi_bases))
		return NULL;

	mxcs = spi_alloc_slave(struct mxc_spi_slave, bus, cs);
	if (!mxcs) {
		puts("mxc_spi: SPI Slave not allocated !\n");
		return NULL;
	}

	mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;

	ret = decode_cs(mxcs, cs);
	if (ret < 0) {
		free(mxcs);
		return NULL;
	}

	cs = ret;

	mxcs->base = spi_bases[bus];

	ret = spi_cfg_mxc(mxcs, cs, max_hz, mode);
	if (ret) {
		printf("mxc_spi: cannot setup SPI controller\n");
		free(mxcs);
		return NULL;
	}
	return &mxcs->slave;
}

void spi_free_slave(struct spi_slave *slave)
{
	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);

	free(mxcs);
}

int spi_claim_bus(struct spi_slave *slave)
{
	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
	struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;

	reg_write(&regs->rxdata, 1);
	udelay(1);
	reg_write(&regs->ctrl, mxcs->ctrl_reg);
	reg_write(&regs->period, MXC_CSPIPERIOD_32KHZ);
	reg_write(&regs->intr, 0);

	return 0;
}

void spi_release_bus(struct spi_slave *slave)
{
	/* TODO: Shut the controller down */
}
Commit	Line	Data
38254f45 GL	1	/*
	2	* Copyright (C) 2008, Guennadi Liakhovetski <[email protected]>
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License as
	6	* published by the Free Software Foundation; either version 2 of
	7	* the License, or (at your option) any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	17	* MA 02111-1307 USA
	18	*
	19	*/
	20
	21	#include <common.h>
d255bb0e	22	#include <malloc.h>
38254f45	23	#include <spi.h>
fc7a93c8	24	#include <asm/errno.h>
38254f45	25	#include <asm/io.h>
d8e0ca85	26	#include <asm/gpio.h>
86271115 SB	27	#include <asm/arch/imx-regs.h>
86271115 SB	28	#include <asm/arch/clock.h>
38254f45 GL	29
	30	#ifdef CONFIG_MX27
	31	/* i.MX27 has a completely wrong register layout and register definitions in the
	32	* datasheet, the correct one is in the Freescale's Linux driver */
	33
61a58a16	34	#error "i.MX27 CSPI not supported due to drastic differences in register definitions" \
38254f45	35	"See linux mxc_spi driver from Freescale for details."
08c61a58	36	#endif
c9d59c7f SB	37
c9d59c7f SB	38	static unsigned long spi_bases[] = {
08c61a58	39	MXC_SPI_BASE_ADDRESSES
c9d59c7f SB	40	};
c9d59c7f SB	41
c4ea1424 SB	42	#define OUT MXC_GPIO_DIRECTION_OUT
c4ea1424 SB	43
ac87c17d SB	44	#define reg_read readl
	45	#define reg_write(a, v) writel(v, a)
	46
d255bb0e HS	47	struct mxc_spi_slave {
	48	struct spi_slave slave;
	49	unsigned long base;
	50	u32 ctrl_reg;
08c61a58	51	#if defined(MXC_ECSPI)
d205ddcf SB	52	u32 cfg_reg;
d205ddcf SB	53	#endif
fc7a93c8	54	int gpio;
c4ea1424	55	int ss_pol;
38254f45	56	};
d255bb0e HS	57
	58	static inline struct mxc_spi_slave to_mxc_spi_slave(struct spi_slave slave)
	59	{
	60	return container_of(slave, struct mxc_spi_slave, slave);
	61	}
38254f45	62
d205ddcf SB	63	void spi_cs_activate(struct spi_slave *slave)
	64	{
	65	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
	66	if (mxcs->gpio > 0)
d8e0ca85	67	gpio_set_value(mxcs->gpio, mxcs->ss_pol);
d205ddcf SB	68	}
	69
	70	void spi_cs_deactivate(struct spi_slave *slave)
	71	{
	72	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
	73	if (mxcs->gpio > 0)
d8e0ca85	74	gpio_set_value(mxcs->gpio,
c4ea1424	75	!(mxcs->ss_pol));
d205ddcf SB	76	}
d205ddcf SB	77
afaa9f65 AG	78	u32 get_cspi_div(u32 div)
	79	{
	80	int i;
	81
	82	for (i = 0; i < 8; i++) {
	83	if (div <= (4 << i))
	84	return i;
	85	}
	86	return i;
	87	}
	88
08c61a58	89	#ifdef MXC_CSPI
c9d59c7f SB	90	static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
	91	unsigned int max_hz, unsigned int mode)
	92	{
	93	unsigned int ctrl_reg;
afaa9f65 AG	94	u32 clk_src;
	95	u32 div;
	96
	97	clk_src = mxc_get_clock(MXC_CSPI_CLK);
	98
cd200403	99	div = DIV_ROUND_UP(clk_src, max_hz);
afaa9f65 AG	100	div = get_cspi_div(div);
	101
	102	debug("clk %d Hz, div %d, real clk %d Hz\n",
	103	max_hz, div, clk_src / (4 << div));
c9d59c7f SB	104
	105	ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) \|
	106	MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) \|
afaa9f65	107	MXC_CSPICTRL_DATARATE(div) \|
c9d59c7f SB	108	MXC_CSPICTRL_EN \|
	109	#ifdef CONFIG_MX35
	110	MXC_CSPICTRL_SSCTL \|
	111	#endif
	112	MXC_CSPICTRL_MODE;
	113
	114	if (mode & SPI_CPHA)
	115	ctrl_reg \|= MXC_CSPICTRL_PHA;
	116	if (mode & SPI_CPOL)
	117	ctrl_reg \|= MXC_CSPICTRL_POL;
	118	if (mode & SPI_CS_HIGH)
	119	ctrl_reg \|= MXC_CSPICTRL_SSPOL;
	120	mxcs->ctrl_reg = ctrl_reg;
	121
	122	return 0;
	123	}
	124	#endif
	125
08c61a58	126	#ifdef MXC_ECSPI
c9d59c7f	127	static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
d205ddcf SB	128	unsigned int max_hz, unsigned int mode)
	129	{
	130	u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
	131	s32 pre_div = 0, post_div = 0, i, reg_ctrl, reg_config;
	132	u32 ss_pol = 0, sclkpol = 0, sclkpha = 0;
ac87c17d	133	struct cspi_regs regs = (struct cspi_regs )mxcs->base;
d205ddcf SB	134
	135	if (max_hz == 0) {
	136	printf("Error: desired clock is 0\n");
	137	return -1;
	138	}
	139
0f1411bc FE	140	/*
	141	* Reset SPI and set all CSs to master mode, if toggling
	142	* between slave and master mode we might see a glitch
	143	* on the clock line
	144	*/
	145	reg_ctrl = MXC_CSPICTRL_MODE_MASK;
	146	reg_write(&regs->ctrl, reg_ctrl);
	147	reg_ctrl \|= MXC_CSPICTRL_EN;
	148	reg_write(&regs->ctrl, reg_ctrl);
d205ddcf SB	149
	150	/*
	151	* The following computation is taken directly from Freescale's code.
	152	*/
	153	if (clk_src > max_hz) {
cd200403	154	pre_div = DIV_ROUND_UP(clk_src, max_hz);
d205ddcf SB	155	if (pre_div > 16) {
	156	post_div = pre_div / 16;
	157	pre_div = 15;
	158	}
	159	if (post_div != 0) {
	160	for (i = 0; i < 16; i++) {
	161	if ((1 << i) >= post_div)
	162	break;
	163	}
	164	if (i == 16) {
	165	printf("Error: no divider for the freq: %d\n",
	166	max_hz);
	167	return -1;
	168	}
	169	post_div = i;
	170	}
	171	}
	172
	173	debug("pre_div = %d, post_div=%d\n", pre_div, post_div);
	174	reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) \|
	175	MXC_CSPICTRL_SELCHAN(cs);
	176	reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) \|
	177	MXC_CSPICTRL_PREDIV(pre_div);
	178	reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) \|
	179	MXC_CSPICTRL_POSTDIV(post_div);
	180
d205ddcf SB	181	/* We need to disable SPI before changing registers */
	182	reg_ctrl &= ~MXC_CSPICTRL_EN;
	183
	184	if (mode & SPI_CS_HIGH)
	185	ss_pol = 1;
	186
9f481e95	187	if (mode & SPI_CPOL)
d205ddcf SB	188	sclkpol = 1;
	189
	190	if (mode & SPI_CPHA)
	191	sclkpha = 1;
	192
ac87c17d	193	reg_config = reg_read(&regs->cfg);
d205ddcf SB	194
	195	/*
	196	* Configuration register setup
c9d59c7f	197	* The MX51 supports different setup for each SS
d205ddcf SB	198	*/
	199	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) \|
	200	(ss_pol << (cs + MXC_CSPICON_SSPOL));
	201	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) \|
	202	(sclkpol << (cs + MXC_CSPICON_POL));
	203	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) \|
	204	(sclkpha << (cs + MXC_CSPICON_PHA));
	205
	206	debug("reg_ctrl = 0x%x\n", reg_ctrl);
ac87c17d	207	reg_write(&regs->ctrl, reg_ctrl);
d205ddcf	208	debug("reg_config = 0x%x\n", reg_config);
ac87c17d	209	reg_write(&regs->cfg, reg_config);
d205ddcf SB	210
	211	/* save config register and control register */
	212	mxcs->ctrl_reg = reg_ctrl;
	213	mxcs->cfg_reg = reg_config;
	214
	215	/* clear interrupt reg */
ac87c17d SB	216	reg_write(&regs->intr, 0);
ac87c17d SB	217	reg_write(&regs->stat, MXC_CSPICTRL_TC \| MXC_CSPICTRL_RXOVF);
d205ddcf SB	218
	219	return 0;
	220	}
	221	#endif
	222
2f721d17 SB	223	int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen,
2f721d17 SB	224	const u8 dout, u8 din, unsigned long flags)
38254f45	225	{
d255bb0e	226	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
2f721d17 SB	227	int nbytes = (bitlen + 7) / 8;
2f721d17 SB	228	u32 data, cnt, i;
ac87c17d	229	struct cspi_regs regs = (struct cspi_regs )mxcs->base;
38254f45	230
2f721d17 SB	231	debug("%s: bitlen %d dout 0x%x din 0x%x\n",
2f721d17 SB	232	__func__, bitlen, (u32)dout, (u32)din);
d205ddcf SB	233
	234	mxcs->ctrl_reg = (mxcs->ctrl_reg &
	235	~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) \|
f9b6a157	236	MXC_CSPICTRL_BITCOUNT(bitlen - 1);
38254f45	237
ac87c17d	238	reg_write(&regs->ctrl, mxcs->ctrl_reg \| MXC_CSPICTRL_EN);
08c61a58	239	#ifdef MXC_ECSPI
ac87c17d	240	reg_write(&regs->cfg, mxcs->cfg_reg);
d205ddcf	241	#endif
38254f45	242
d205ddcf	243	/* Clear interrupt register */
ac87c17d	244	reg_write(&regs->stat, MXC_CSPICTRL_TC \| MXC_CSPICTRL_RXOVF);
fc7a93c8	245
2f721d17 SB	246	/*
	247	* The SPI controller works only with words,
	248	* check if less than a word is sent.
	249	* Access to the FIFO is only 32 bit
	250	*/
	251	if (bitlen % 32) {
	252	data = 0;
	253	cnt = (bitlen % 32) / 8;
	254	if (dout) {
	255	for (i = 0; i < cnt; i++) {
	256	data = (data << 8) \| (*dout++ & 0xFF);
	257	}
	258	}
	259	debug("Sending SPI 0x%x\n", data);
	260
ac87c17d	261	reg_write(&regs->txdata, data);
2f721d17 SB	262	nbytes -= cnt;
	263	}
	264
	265	data = 0;
	266
	267	while (nbytes > 0) {
	268	data = 0;
	269	if (dout) {
	270	/* Buffer is not 32-bit aligned */
	271	if ((unsigned long)dout & 0x03) {
	272	data = 0;
dff01094	273	for (i = 0; i < 4; i++)
2f721d17	274	data = (data << 8) \| (*dout++ & 0xFF);
2f721d17 SB	275	} else {
	276	data = (u32 )dout;
	277	data = cpu_to_be32(data);
	278	}
	279	dout += 4;
	280	}
	281	debug("Sending SPI 0x%x\n", data);
ac87c17d	282	reg_write(&regs->txdata, data);
2f721d17 SB	283	nbytes -= 4;
2f721d17 SB	284	}
38254f45	285
d205ddcf	286	/* FIFO is written, now starts the transfer setting the XCH bit */
ac87c17d	287	reg_write(&regs->ctrl, mxcs->ctrl_reg \|
d205ddcf	288	MXC_CSPICTRL_EN \| MXC_CSPICTRL_XCH);
38254f45	289
d205ddcf	290	/* Wait until the TC (Transfer completed) bit is set */
ac87c17d	291	while ((reg_read(&regs->stat) & MXC_CSPICTRL_TC) == 0)
38254f45 GL	292	;
38254f45 GL	293
d205ddcf	294	/* Transfer completed, clear any pending request */
ac87c17d	295	reg_write(&regs->stat, MXC_CSPICTRL_TC \| MXC_CSPICTRL_RXOVF);
d205ddcf	296
2f721d17	297	nbytes = (bitlen + 7) / 8;
d205ddcf	298
2f721d17	299	cnt = nbytes % 32;
d205ddcf	300
2f721d17	301	if (bitlen % 32) {
ac87c17d	302	data = reg_read(&regs->rxdata);
2f721d17	303	cnt = (bitlen % 32) / 8;
dff01094	304	data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8);
2f721d17 SB	305	debug("SPI Rx unaligned: 0x%x\n", data);
2f721d17 SB	306	if (din) {
dff01094 AG	307	memcpy(din, &data, cnt);
dff01094 AG	308	din += cnt;
2f721d17 SB	309	}
	310	nbytes -= cnt;
	311	}
	312
	313	while (nbytes > 0) {
	314	u32 tmp;
ac87c17d	315	tmp = reg_read(&regs->rxdata);
2f721d17 SB	316	data = cpu_to_be32(tmp);
	317	debug("SPI Rx: 0x%x 0x%x\n", tmp, data);
	318	cnt = min(nbytes, sizeof(data));
	319	if (din) {
	320	memcpy(din, &data, cnt);
	321	din += cnt;
	322	}
	323	nbytes -= cnt;
	324	}
	325
	326	return 0;
fc7a93c8	327
38254f45 GL	328	}
38254f45 GL	329
d255bb0e HS	330	int spi_xfer(struct spi_slave slave, unsigned int bitlen, const void dout,
d255bb0e HS	331	void *din, unsigned long flags)
38254f45	332	{
2f721d17 SB	333	int n_bytes = (bitlen + 7) / 8;
	334	int n_bits;
	335	int ret;
	336	u32 blk_size;
	337	u8 p_outbuf = (u8 )dout;
	338	u8 p_inbuf = (u8 )din;
38254f45	339
2f721d17 SB	340	if (!slave)
2f721d17 SB	341	return -1;
38254f45	342
2f721d17 SB	343	if (flags & SPI_XFER_BEGIN)
	344	spi_cs_activate(slave);
	345
	346	while (n_bytes > 0) {
2f721d17 SB	347	if (n_bytes < MAX_SPI_BYTES)
	348	blk_size = n_bytes;
	349	else
	350	blk_size = MAX_SPI_BYTES;
	351
	352	n_bits = blk_size * 8;
	353
	354	ret = spi_xchg_single(slave, n_bits, p_outbuf, p_inbuf, 0);
	355
	356	if (ret)
	357	return ret;
	358	if (dout)
	359	p_outbuf += blk_size;
	360	if (din)
	361	p_inbuf += blk_size;
	362	n_bytes -= blk_size;
eff536be ML	363	}
eff536be ML	364
2f721d17 SB	365	if (flags & SPI_XFER_END) {
2f721d17 SB	366	spi_cs_deactivate(slave);
f9b6a157	367	}
38254f45 GL	368
	369	return 0;
	370	}
	371
	372	void spi_init(void)
	373	{
	374	}
	375
fc7a93c8 GL	376	static int decode_cs(struct mxc_spi_slave *mxcs, unsigned int cs)
	377	{
	378	int ret;
	379
	380	/*
	381	* Some SPI devices require active chip-select over multiple
	382	* transactions, we achieve this using a GPIO. Still, the SPI
	383	* controller has to be configured to use one of its own chipselects.
	384	* To use this feature you have to call spi_setup_slave() with
	385	* cs = internal_cs \| (gpio << 8), and you have to use some unused
	386	* on this SPI controller cs between 0 and 3.
	387	*/
	388	if (cs > 3) {
	389	mxcs->gpio = cs >> 8;
	390	cs &= 3;
de5bf02c	391	ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol));
fc7a93c8 GL	392	if (ret) {
	393	printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
	394	return -EINVAL;
	395	}
	396	} else {
	397	mxcs->gpio = -1;
	398	}
	399
	400	return cs;
	401	}
	402
d255bb0e HS	403	struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
d255bb0e HS	404	unsigned int max_hz, unsigned int mode)
38254f45	405	{
d255bb0e	406	struct mxc_spi_slave *mxcs;
fc7a93c8 GL	407	int ret;
	408
	409	if (bus >= ARRAY_SIZE(spi_bases))
	410	return NULL;
	411
d3504fee	412	mxcs = spi_alloc_slave(struct mxc_spi_slave, bus, cs);
2f721d17 SB	413	if (!mxcs) {
2f721d17 SB	414	puts("mxc_spi: SPI Slave not allocated !\n");
fc7a93c8	415	return NULL;
2f721d17	416	}
38254f45	417
de5bf02c FE	418	mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
de5bf02c FE	419
fc7a93c8 GL	420	ret = decode_cs(mxcs, cs);
	421	if (ret < 0) {
	422	free(mxcs);
d255bb0e	423	return NULL;
fc7a93c8 GL	424	}
	425
	426	cs = ret;
38254f45	427
d205ddcf SB	428	mxcs->base = spi_bases[bus];
d205ddcf SB	429
c9d59c7f	430	ret = spi_cfg_mxc(mxcs, cs, max_hz, mode);
d205ddcf SB	431	if (ret) {
	432	printf("mxc_spi: cannot setup SPI controller\n");
	433	free(mxcs);
	434	return NULL;
	435	}
d255bb0e HS	436	return &mxcs->slave;
	437	}
	438
	439	void spi_free_slave(struct spi_slave *slave)
	440	{
f9b6a157 GL	441	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
	442
	443	free(mxcs);
d255bb0e HS	444	}
	445
	446	int spi_claim_bus(struct spi_slave *slave)
	447	{
	448	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
ac87c17d	449	struct cspi_regs regs = (struct cspi_regs )mxcs->base;
d255bb0e	450
ac87c17d	451	reg_write(&regs->rxdata, 1);
38254f45	452	udelay(1);
ac87c17d SB	453	reg_write(&regs->ctrl, mxcs->ctrl_reg);
	454	reg_write(&regs->period, MXC_CSPIPERIOD_32KHZ);
	455	reg_write(&regs->intr, 0);
38254f45 GL	456
	457	return 0;
	458	}
d255bb0e HS	459
	460	void spi_release_bus(struct spi_slave *slave)
	461	{
	462	/* TODO: Shut the controller down */
	463	}