[u-boot.git] / include / configs / FPS860L.h

/*
 * (C) Copyright 2000-2008
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC860		1	/* This is a MPC860 CPU		*/
#define CONFIG_FPS860L		1	/* ...on a FingerPrint Sensor	*/

#undef	CONFIG_8xx_CONS_SMC1
#define	CONFIG_8xx_CONS_SMC2	1	/* Console is on SMC2		*/
#undef	CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE		115200

#define	CONFIG_BOOTCOUNT_LIMIT

#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/

#define CONFIG_BOARD_TYPES	1	/* support board types		*/

#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"flash_nfs=run nfsargs addip;"					\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip;"					\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
	"rootpath=/opt/eldk/ppc_8xx\0"					\
	"hostname=FPS860L\0"						\
	"bootfile=FPS860L/uImage\0"					\
	"fdt_addr=40040000\0"						\
	"kernel_addr=40060000\0"					\
	"ramdisk_addr=40200000\0"					\
	"u-boot=FPS860L/u-image.bin\0"					\
	"load=tftp 200000 ${u-boot}\0"					\
	"update=prot off 40000000 +${filesize};"			\
		"era 40000000 +${filesize};"				\
		"cp.b 200000 40000000 ${filesize};"			\
		"sete filesize;save\0"					\
	""
#define CONFIG_BOOTCOMMAND	"run flash_self"

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_NISDOMAIN
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_BOOTP_NTPSERVER
#define CONFIG_BOOTP_TIMEOFFSET

#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP


#define CONFIG_NETCONSOLE


/*
 * Miscellaneous configurable options
 */
#define	CFG_LONGHELP			/* undef to save memory		*/
#define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/

#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
#ifdef	CFG_HUSH_PARSER
#define	CFG_PROMPT_HUSH_PS2	"> "
#endif

#if defined(CONFIG_CMD_KGDB)
#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define	CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/

#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/

#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CFG_IMMR		0xFFF00000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CFG_INIT_RAM_ADDR	CFG_IMMR
#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define	CFG_SDRAM_BASE		0x00000000
#define CFG_FLASH_BASE		0x40000000
#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define CFG_MONITOR_BASE	CFG_FLASH_BASE
#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/

/*-----------------------------------------------------------------------
 * FLASH organization
 */

/* use CFI flash driver */
#define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_USE_BUFFER_WRITE	1
#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks */
#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip */

#define	CONFIG_ENV_IS_IN_FLASH	1
#define	CONFIG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)

#define	CFG_USE_PPCENV			/* Environment embedded in sect .ppcenv */

/*-----------------------------------------------------------------------
 * Dynamic MTD partition support
 */
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT		"nor0=TQM8xxL-0"

#define MTDPARTS_DEFAULT	"mtdparts=TQM8xxL-0:256k(u-boot),"	\
						"128k(dtb),"		\
						"1664k(kernel),"	\
						"2m(rootfs),"		\
						"4m(data)"

/*-----------------------------------------------------------------------
 * Hardware Information Block
 */
#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)

/*-----------------------------------------------------------------------
 * RTCSC - Real-Time Clock Status and Control Register		11-27
 *-----------------------------------------------------------------------
 */
#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CFG_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit - leave PLL multiplication factor unchanged !
 */
#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF11
#define CFG_SCCR	(SCCR_TBS     | \
			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
			 SCCR_DFALCD00)

/*-----------------------------------------------------------------------
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 *
 */
#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )

/*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
#define CFG_DER	0

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/

/* used to re-map FLASH both when starting from SRAM or FLASH:
 * restrict access enough to keep SRAM working (if any)
 * but not too much to meddle with FLASH accesses
 */
#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */

/*
 * FLASH timing:
 */
#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
				 OR_SCY_3_CLK | OR_EHTR | OR_BI)

#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )

#define CFG_OR1_REMAP	CFG_OR0_REMAP
#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )

/*
 * BR2/3 and OR2/3 (SDRAM)
 *
 */
#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/

/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
#define CFG_OR_TIMING_SDRAM	0x00000A00

#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )

#define	CFG_OR3_PRELIM	CFG_OR2_PRELIM
#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )

/*
 * Memory Periodic Timer Prescaler
 *
 * The Divider for PTA (refresh timer) configuration is based on an
 * example SDRAM configuration (64 MBit, one bank). The adjustment to
 * the number of chip selects (NCS) and the actually needed refresh
 * rate is done by setting MPTPR.
 *
 * PTA is calculated from
 *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
 *
 *	gclk	  CPU clock (not bus clock!)
 *	Trefresh  Refresh cycle * 4 (four word bursts used)
 *
 * 4096  Rows from SDRAM example configuration
 * 1000  factor s -> ms
 *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
 *    4  Number of refresh cycles per period
 *   64  Refresh cycle in ms per number of rows
 * --------------------------------------------
 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
 *
 * 50 MHz => 50.000.000 / Divider =  98
 * 66 Mhz => 66.000.000 / Divider = 129
 * 80 Mhz => 80.000.000 / Divider = 156
 */

#define CFG_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
#define CFG_MAMR_PTA	98

/*
 * For 16 MBit, refresh rates could be 31.3 us
 * (= 64 ms / 2K = 125 / quad bursts).
 * For a simpler initialization, 15.6 us is used instead.
 *
 * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
 * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
 */
#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/

/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/

/*
 * MAMR settings for SDRAM
 */

/* 8 column SDRAM */
#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
/* 9 column SDRAM */
#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)


/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#define CONFIG_SCC1_ENET

#endif	/* __CONFIG_H */
Commit	Line	Data
384ae025	1	/*
29f8f58f	2	* (C) Copyright 2000-2008
384ae025 WD	3	* Wolfgang Denk, DENX Software Engineering, [email protected].
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*
	32	* High Level Configuration Options
	33	* (easy to change)
	34	*/
	35
	36	#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
	37	#define CONFIG_FPS860L 1 /* ...on a FingerPrint Sensor */
	38
	39	#undef CONFIG_8xx_CONS_SMC1
	40	#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
	41	#undef CONFIG_8xx_CONS_NONE
	42	#define CONFIG_BAUDRATE 115200
eb6da805 WD	43
	44	#define CONFIG_BOOTCOUNT_LIMIT
	45
384ae025	46	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
384ae025	47
384ae025 WD	48	#define CONFIG_BOARD_TYPES 1 /* support board types */
384ae025 WD	49
32bf3d14	50	#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
eb6da805 WD	51
	52	#undef CONFIG_BOOTARGS
	53
	54	#define CONFIG_EXTRA_ENV_SETTINGS \
	55	"netdev=eth0\0" \
	56	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	57	"nfsroot=${serverip}:${rootpath}\0" \
	58	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	59	"addip=setenv bootargs ${bootargs} " \
	60	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	61	":${hostname}:${netdev}:off panic=1\0" \
	62	"flash_nfs=run nfsargs addip;" \
	63	"bootm ${kernel_addr}\0" \
	64	"flash_self=run ramargs addip;" \
	65	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
	66	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
	67	"rootpath=/opt/eldk/ppc_8xx\0" \
29f8f58f WD	68	"hostname=FPS860L\0" \
29f8f58f WD	69	"bootfile=FPS860L/uImage\0" \
eb6da805 WD	70	"fdt_addr=40040000\0" \
	71	"kernel_addr=40060000\0" \
	72	"ramdisk_addr=40200000\0" \
29f8f58f WD	73	"u-boot=FPS860L/u-image.bin\0" \
	74	"load=tftp 200000 ${u-boot}\0" \
	75	"update=prot off 40000000 +${filesize};" \
	76	"era 40000000 +${filesize};" \
	77	"cp.b 200000 40000000 ${filesize};" \
	78	"sete filesize;save\0" \
eb6da805 WD	79	""
eb6da805 WD	80	#define CONFIG_BOOTCOMMAND "run flash_self"
384ae025 WD	81
	82	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	83	#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
	84
	85	#undef CONFIG_WATCHDOG /* watchdog disabled */
	86
5d2ebe1b JL	87	/*
	88	* BOOTP options
	89	*/
	90	#define CONFIG_BOOTP_SUBNETMASK
	91	#define CONFIG_BOOTP_GATEWAY
	92	#define CONFIG_BOOTP_HOSTNAME
	93	#define CONFIG_BOOTP_BOOTPATH
	94	#define CONFIG_BOOTP_BOOTFILESIZE
	95	#define CONFIG_BOOTP_SUBNETMASK
	96	#define CONFIG_BOOTP_GATEWAY
	97	#define CONFIG_BOOTP_HOSTNAME
	98	#define CONFIG_BOOTP_NISDOMAIN
	99	#define CONFIG_BOOTP_BOOTPATH
	100	#define CONFIG_BOOTP_DNS
	101	#define CONFIG_BOOTP_DNS2
	102	#define CONFIG_BOOTP_SEND_HOSTNAME
	103	#define CONFIG_BOOTP_NTPSERVER
	104	#define CONFIG_BOOTP_TIMEOFFSET
384ae025 WD	105
	106	#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
	107
60a0876b JL	108	/*
	109	* Command line configuration.
	110	*/
	111	#include <config_cmd_default.h>
eb6da805	112
60a0876b JL	113	#define CONFIG_CMD_ASKENV
	114	#define CONFIG_CMD_DATE
	115	#define CONFIG_CMD_DHCP
29f8f58f	116	#define CONFIG_CMD_JFFS2
60a0876b JL	117	#define CONFIG_CMD_NFS
	118	#define CONFIG_CMD_SNTP
	119
384ae025	120
29f8f58f WD	121	#define CONFIG_NETCONSOLE
	122
	123
384ae025 WD	124	/*
	125	* Miscellaneous configurable options
	126	*/
	127	#define CFG_LONGHELP /* undef to save memory */
eb6da805 WD	128	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	129
	130	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
	131	#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
	132	#ifdef CFG_HUSH_PARSER
	133	#define CFG_PROMPT_HUSH_PS2 "> "
	134	#endif
	135
60a0876b	136	#if defined(CONFIG_CMD_KGDB)
384ae025 WD	137	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	138	#else
	139	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	140	#endif
	141	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	142	#define CFG_MAXARGS 16 /* max number of command args */
	143	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	144
	145	#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
	146	#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
	147
	148	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	149
	150	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	151
	152	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	153
	154	/*
	155	* Low Level Configuration Settings
	156	* (address mappings, register initial values, etc.)
	157	* You should know what you are doing if you make changes here.
	158	*/
	159	/*-----------------------------------------------------------------------
	160	* Internal Memory Mapped Register
	161	*/
	162	#define CFG_IMMR 0xFFF00000
	163
	164	/*-----------------------------------------------------------------------
	165	* Definitions for initial stack pointer and data area (in DPRAM)
	166	*/
	167	#define CFG_INIT_RAM_ADDR CFG_IMMR
	168	#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
	169	#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
	170	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	171	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	172
	173	/*-----------------------------------------------------------------------
	174	* Start addresses for the final memory configuration
	175	* (Set up by the startup code)
	176	* Please note that CFG_SDRAM_BASE _must_ start at 0
	177	*/
	178	#define CFG_SDRAM_BASE 0x00000000
	179	#define CFG_FLASH_BASE 0x40000000
	180	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	181	#define CFG_MONITOR_BASE CFG_FLASH_BASE
	182	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	183
	184	/*
	185	* For booting Linux, the board info and command line data
	186	* have to be in the first 8 MB of memory, since this is
	187	* the maximum mapped by the Linux kernel during initialization.
	188	*/
	189	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	190
	191	/*-----------------------------------------------------------------------
	192	* FLASH organization
	193	*/
384ae025	194
29f8f58f WD	195	/* use CFI flash driver */
29f8f58f WD	196	#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
00b1883a	197	#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
29f8f58f WD	198	#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size }
	199	#define CFG_FLASH_EMPTY_INFO
	200	#define CFG_FLASH_USE_BUFFER_WRITE 1
	201	#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
	202	#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
384ae025	203
5a1aceb0	204	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	205	#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
0e8d1586 JCPV	206	#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
384ae025 WD	207
384ae025 WD	208	/* Address and size of Redundant Environment Sector */
0e8d1586 JCPV	209	#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
0e8d1586 JCPV	210	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
384ae025	211
29f8f58f WD	212	#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
	213
	214	/*-----------------------------------------------------------------------
	215	* Dynamic MTD partition support
	216	*/
	217	#define CONFIG_JFFS2_CMDLINE
	218	#define MTDIDS_DEFAULT "nor0=TQM8xxL-0"
	219
	220	#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \
	221	"128k(dtb)," \
	222	"1664k(kernel)," \
	223	"2m(rootfs)," \
cd82919e	224	"4m(data)"
29f8f58f	225
384ae025 WD	226	/*-----------------------------------------------------------------------
	227	* Hardware Information Block
	228	*/
	229	#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
	230	#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
	231	#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
	232
	233	/*-----------------------------------------------------------------------
	234	* Cache Configuration
	235	*/
	236	#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
60a0876b	237	#if defined(CONFIG_CMD_KGDB)
384ae025 WD	238	#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
	239	#endif
	240
	241	/*-----------------------------------------------------------------------
	242	* SYPCR - System Protection Control 11-9
	243	* SYPCR can only be written once after reset!
	244	*-----------------------------------------------------------------------
	245	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	246	*/
	247	#if defined(CONFIG_WATCHDOG)
	248	#define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
	249	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
	250	#else
	251	#define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
	252	#endif
	253
	254	/*-----------------------------------------------------------------------
	255	* SIUMCR - SIU Module Configuration 11-6
	256	*-----------------------------------------------------------------------
	257	* PCMCIA config., multi-function pin tri-state
	258	*/
	259	#define CFG_SIUMCR (SIUMCR_DBGC00 \| SIUMCR_DBPC00 \| SIUMCR_MLRC01)
	260
	261	/*-----------------------------------------------------------------------
	262	* TBSCR - Time Base Status and Control 11-26
	263	*-----------------------------------------------------------------------
	264	* Clear Reference Interrupt Status, Timebase freezing enabled
	265	*/
	266	#define CFG_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF)
	267
	268	/*-----------------------------------------------------------------------
	269	* RTCSC - Real-Time Clock Status and Control Register 11-27
	270	*-----------------------------------------------------------------------
	271	*/
	272	#define CFG_RTCSC (RTCSC_SEC \| RTCSC_ALR \| RTCSC_RTF\| RTCSC_RTE)
	273
	274	/*-----------------------------------------------------------------------
	275	* PISCR - Periodic Interrupt Status and Control 11-31
	276	*-----------------------------------------------------------------------
	277	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	278	*/
	279	#define CFG_PISCR (PISCR_PS \| PISCR_PITF)
	280
	281	/*-----------------------------------------------------------------------
	282	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
	283	*-----------------------------------------------------------------------
	284	* Reset PLL lock status sticky bit, timer expired status bit and timer
	285	* interrupt status bit - leave PLL multiplication factor unchanged !
	286	*/
	287	#define CFG_PLPRCR (PLPRCR_SPLSS \| PLPRCR_TEXPS \| PLPRCR_TMIST)
	288
	289	/*-----------------------------------------------------------------------
	290	* SCCR - System Clock and reset Control Register 15-27
	291	*-----------------------------------------------------------------------
	292	* Set clock output, timebase and RTC source and divider,
	293	* power management and some other internal clocks
	294	*/
	295	#define SCCR_MASK SCCR_EBDF11
	296	#define CFG_SCCR (SCCR_TBS \| \
	297	SCCR_COM00 \| SCCR_DFSYNC00 \| SCCR_DFBRG00 \| \
	298	SCCR_DFNL000 \| SCCR_DFNH000 \| SCCR_DFLCD000 \| \
	299	SCCR_DFALCD00)
	300
	301	/*-----------------------------------------------------------------------
302	* PCMCIA stuff
303	*-----------------------------------------------------------------------
304	*
305	*/
306	#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
307	#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
308	#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
309	#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
310	#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
311	#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
312	#define CFG_PCMCIA_IO_ADDR (0xEC000000)
313	#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
314
315	/*-----------------------------------------------------------------------
316	*
317	*-----------------------------------------------------------------------
318	*
319	*/
384ae025 WD	320	#define CFG_DER 0
	321
	322	/*
	323	* Init Memory Controller:
	324	*
	325	* BR0/1 and OR0/1 (FLASH)
	326	*/
	327
	328	#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
	329	#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
	330
	331	/* used to re-map FLASH both when starting from SRAM or FLASH:
	332	* restrict access enough to keep SRAM working (if any)
	333	* but not too much to meddle with FLASH accesses
	334	*/
	335	#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
	336	#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
	337
29f8f58f WD	338	/*
	339	* FLASH timing:
	340	*/
	341	#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 \| OR_TRLX \| OR_CSNT_SAM \| \
	342	OR_SCY_3_CLK \| OR_EHTR \| OR_BI)
384ae025 WD	343
	344	#define CFG_OR0_REMAP (CFG_REMAP_OR_AM \| CFG_OR_TIMING_FLASH)
	345	#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM \| CFG_OR_TIMING_FLASH)
	346	#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) \| BR_V )
	347
	348	#define CFG_OR1_REMAP CFG_OR0_REMAP
	349	#define CFG_OR1_PRELIM CFG_OR0_PRELIM
	350	#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) \| BR_V )
	351
	352	/*
	353	* BR2/3 and OR2/3 (SDRAM)
	354	*
	355	*/
	356	#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
	357	#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
	358	#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
	359
	360	/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
	361	#define CFG_OR_TIMING_SDRAM 0x00000A00
	362
	363	#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM \| CFG_OR_TIMING_SDRAM )
	364	#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) \| BR_MS_UPMA \| BR_V )
	365
	366	#define CFG_OR3_PRELIM CFG_OR2_PRELIM
	367	#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) \| BR_MS_UPMA \| BR_V )
	368
	369	/*
	370	* Memory Periodic Timer Prescaler
29f8f58f WD	371	*
	372	* The Divider for PTA (refresh timer) configuration is based on an
	373	* example SDRAM configuration (64 MBit, one bank). The adjustment to
	374	* the number of chip selects (NCS) and the actually needed refresh
	375	* rate is done by setting MPTPR.
	376	*
	377	* PTA is calculated from
	378	* PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
	379	*
	380	* gclk CPU clock (not bus clock!)
	381	* Trefresh Refresh cycle * 4 (four word bursts used)
	382	*
	383	* 4096 Rows from SDRAM example configuration
	384	* 1000 factor s -> ms
	385	* 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
	386	* 4 Number of refresh cycles per period
	387	* 64 Refresh cycle in ms per number of rows
	388	* --------------------------------------------
	389	* Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
	390	*
	391	* 50 MHz => 50.000.000 / Divider = 98
	392	* 66 Mhz => 66.000.000 / Divider = 129
	393	* 80 Mhz => 80.000.000 / Divider = 156
384ae025 WD	394	*/
384ae025 WD	395
29f8f58f WD	396	#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
29f8f58f WD	397	#define CFG_MAMR_PTA 98
384ae025	398
29f8f58f WD	399	/*
	400	* For 16 MBit, refresh rates could be 31.3 us
	401	* (= 64 ms / 2K = 125 / quad bursts).
	402	* For a simpler initialization, 15.6 us is used instead.
	403	*
	404	* #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
	405	* #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
	406	*/
384ae025 WD	407	#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
	408	#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
	409
	410	/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
	411	#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
	412	#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
	413
	414	/*
	415	* MAMR settings for SDRAM
	416	*/
	417
	418	/* 8 column SDRAM */
	419	#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
	420	MAMR_AMA_TYPE_0 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A11 \| \
	421	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
	422	/* 9 column SDRAM */
	423	#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
	424	MAMR_AMA_TYPE_1 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A10 \| \
	425	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
	426
	427
	428	/*
	429	* Internal Definitions
	430	*
	431	* Boot Flags
	432	*/
	433	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	434	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	435
29f8f58f WD	436	#define CONFIG_SCC1_ENET
29f8f58f WD	437
384ae025	438	#endif /* __CONFIG_H */