[u-boot.git] / drivers / clk / rockchip / clk_rk322x.c

// SPDX-License-Identifier: GPL-2.0
/*
 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
 */

#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
#include <log.h>
#include <malloc.h>
#include <syscon.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru_rk322x.h>
#include <asm/arch-rockchip/hardware.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dt-bindings/clock/rk3228-cru.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/log2.h>
#include <linux/stringify.h>

enum {
	VCO_MAX_HZ	= 3200U * 1000000,
	VCO_MIN_HZ	= 800 * 1000000,
	OUTPUT_MAX_HZ	= 3200U * 1000000,
	OUTPUT_MIN_HZ	= 24 * 1000000,
};

#define DIV_TO_RATE(input_rate, div)	((input_rate) / ((div) + 1))

#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
	.refdiv = _refdiv,\
	.fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ), \
	.postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
	_Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) * \
			 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz, \
			 #hz "Hz cannot be hit with PLL "\
			 "divisors on line " __stringify(__LINE__));

/* use integer mode*/
static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);

static int rkclk_set_pll(struct rk322x_cru *cru, enum rk_clk_id clk_id,
			 const struct pll_div *div)
{
	int pll_id = rk_pll_id(clk_id);
	struct rk322x_pll *pll = &cru->pll[pll_id];

	/* All PLLs have same VCO and output frequency range restrictions. */
	uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000;
	uint output_hz = vco_hz / div->postdiv1 / div->postdiv2;

	debug("PLL at %p: fb=%d, ref=%d, pst1=%d, pst2=%d, vco=%u Hz, output=%u Hz\n",
	      pll, div->fbdiv, div->refdiv, div->postdiv1,
	      div->postdiv2, vco_hz, output_hz);
	assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
	       output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);

	/* use integer mode */
	rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
	/* Power down */
	rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT);

	rk_clrsetreg(&pll->con0,
		     PLL_POSTDIV1_MASK | PLL_FBDIV_MASK,
		     (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv);
	rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,
		     (div->postdiv2 << PLL_POSTDIV2_SHIFT |
		     div->refdiv << PLL_REFDIV_SHIFT));

	/* Power Up */
	rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT);

	/* waiting for pll lock */
	while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))
		udelay(1);

	return 0;
}

static void rkclk_init(struct rk322x_cru *cru)
{
	u32 aclk_div;
	u32 hclk_div;
	u32 pclk_div;

	/* pll enter slow-mode */
	rk_clrsetreg(&cru->cru_mode_con,
		     GPLL_MODE_MASK | APLL_MODE_MASK,
		     GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
		     APLL_MODE_SLOW << APLL_MODE_SHIFT);

	/* init pll */
	rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
	rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);

	/*
	 * select apll as cpu/core clock pll source and
	 * set up dependent divisors for PERI and ACLK clocks.
	 * core hz : apll = 1:1
	 */
	aclk_div = APLL_HZ / CORE_ACLK_HZ - 1;
	assert((aclk_div + 1) * CORE_ACLK_HZ == APLL_HZ && aclk_div < 0x7);

	pclk_div = APLL_HZ / CORE_PERI_HZ - 1;
	assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf);

	rk_clrsetreg(&cru->cru_clksel_con[0],
		     CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK,
		     CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT |
		     0 << CORE_DIV_CON_SHIFT);

	rk_clrsetreg(&cru->cru_clksel_con[1],
		     CORE_ACLK_DIV_MASK | CORE_PERI_DIV_MASK,
		     aclk_div << CORE_ACLK_DIV_SHIFT |
		     pclk_div << CORE_PERI_DIV_SHIFT);

	/*
	 * select gpll as pd_bus bus clock source and
	 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
	 */
	aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1;
	assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);

	pclk_div = BUS_ACLK_HZ / BUS_PCLK_HZ - 1;
	assert((pclk_div + 1) * BUS_PCLK_HZ == BUS_ACLK_HZ && pclk_div <= 0x7);

	hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1;
	assert((hclk_div + 1) * BUS_HCLK_HZ == BUS_ACLK_HZ && hclk_div <= 0x3);

	rk_clrsetreg(&cru->cru_clksel_con[0],
		     BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK,
		     BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT |
		     aclk_div << BUS_ACLK_DIV_SHIFT);

	rk_clrsetreg(&cru->cru_clksel_con[1],
		     BUS_PCLK_DIV_MASK | BUS_HCLK_DIV_MASK,
		     pclk_div << BUS_PCLK_DIV_SHIFT |
		     hclk_div << BUS_HCLK_DIV_SHIFT);

	/*
	 * select gpll as pd_peri bus clock source and
	 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
	 */
	aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
	assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);

	hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
	assert((1 << hclk_div) * PERI_HCLK_HZ ==
		PERI_ACLK_HZ && (hclk_div < 0x4));

	pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
	assert((1 << pclk_div) * PERI_PCLK_HZ ==
		PERI_ACLK_HZ && pclk_div < 0x8);

	rk_clrsetreg(&cru->cru_clksel_con[10],
		     PERI_PLL_SEL_MASK | PERI_PCLK_DIV_MASK |
		     PERI_HCLK_DIV_MASK | PERI_ACLK_DIV_MASK,
		     PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT |
		     pclk_div << PERI_PCLK_DIV_SHIFT |
		     hclk_div << PERI_HCLK_DIV_SHIFT |
		     aclk_div << PERI_ACLK_DIV_SHIFT);

	/* PLL enter normal-mode */
	rk_clrsetreg(&cru->cru_mode_con,
		     GPLL_MODE_MASK | APLL_MODE_MASK,
		     GPLL_MODE_NORM << GPLL_MODE_SHIFT |
		     APLL_MODE_NORM << APLL_MODE_SHIFT);
}

/* Get pll rate by id */
static uint32_t rkclk_pll_get_rate(struct rk322x_cru *cru,
				   enum rk_clk_id clk_id)
{
	uint32_t refdiv, fbdiv, postdiv1, postdiv2;
	uint32_t con;
	int pll_id = rk_pll_id(clk_id);
	struct rk322x_pll *pll = &cru->pll[pll_id];
	static u8 clk_shift[CLK_COUNT] = {
		0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff,
		GPLL_MODE_SHIFT, 0xff
	};
	static u32 clk_mask[CLK_COUNT] = {
		0xff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xff,
		GPLL_MODE_MASK, 0xff
	};
	uint shift;
	uint mask;

	con = readl(&cru->cru_mode_con);
	shift = clk_shift[clk_id];
	mask = clk_mask[clk_id];

	switch ((con & mask) >> shift) {
	case GPLL_MODE_SLOW:
		return OSC_HZ;
	case GPLL_MODE_NORM:

		/* normal mode */
		con = readl(&pll->con0);
		postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT;
		fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT;
		con = readl(&pll->con1);
		postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT;
		refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT;
		return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
	default:
		return 32768;
	}
}

static ulong rockchip_mmc_get_clk(struct rk322x_cru *cru, uint clk_general_rate,
				  int periph)
{
	uint src_rate;
	uint div, mux;
	u32 con;

	switch (periph) {
	case HCLK_EMMC:
	case SCLK_EMMC:
	case SCLK_EMMC_SAMPLE:
		con = readl(&cru->cru_clksel_con[11]);
		mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
		con = readl(&cru->cru_clksel_con[12]);
		div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
		break;
	case HCLK_SDMMC:
	case SCLK_SDMMC:
		con = readl(&cru->cru_clksel_con[11]);
		mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
		div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
		break;
	default:
		return -EINVAL;
	}

	src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate;
	return DIV_TO_RATE(src_rate, div) / 2;
}

static ulong rk322x_mac_set_clk(struct rk322x_cru *cru, uint freq)
{
	ulong ret;

	/*
	 * The gmac clock can be derived either from an external clock
	 * or can be generated from internally by a divider from SCLK_MAC.
	 */
	if (readl(&cru->cru_clksel_con[5]) & BIT(5)) {
		/* An external clock will always generate the right rate... */
		ret = freq;
	} else {
		u32 con = readl(&cru->cru_clksel_con[5]);
		ulong pll_rate;
		u8 div;

		if ((con >> MAC_PLL_SEL_SHIFT) & MAC_PLL_SEL_MASK)
			pll_rate = GPLL_HZ;
		else
			/* CPLL is not set */
			return -EPERM;

		div = DIV_ROUND_UP(pll_rate, freq) - 1;
		if (div <= 0x1f)
			rk_clrsetreg(&cru->cru_clksel_con[5], CLK_MAC_DIV_MASK,
				     div << CLK_MAC_DIV_SHIFT);
		else
			debug("Unsupported div for gmac:%d\n", div);

		return DIV_TO_RATE(pll_rate, div);
	}

	return ret;
}

static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate,
				  int periph, uint freq)
{
	int src_clk_div;
	int mux;

	debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate);

	/* mmc clock defaulg div 2 internal, need provide double in cru */
	src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq);

	if (src_clk_div > 128) {
		src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
		assert(src_clk_div - 1 < 128);
		mux = EMMC_SEL_24M;
	} else {
		mux = EMMC_SEL_GPLL;
	}

	switch (periph) {
	case HCLK_EMMC:
	case SCLK_EMMC:
	case SCLK_EMMC_SAMPLE:
		rk_clrsetreg(&cru->cru_clksel_con[11],
			     EMMC_PLL_MASK,
			     mux << EMMC_PLL_SHIFT);
		rk_clrsetreg(&cru->cru_clksel_con[12],
			     EMMC_DIV_MASK,
			     (src_clk_div - 1) << EMMC_DIV_SHIFT);
		break;
	case HCLK_SDMMC:
	case SCLK_SDMMC:
		rk_clrsetreg(&cru->cru_clksel_con[11],
			     MMC0_PLL_MASK | MMC0_DIV_MASK,
			     mux << MMC0_PLL_SHIFT |
			     (src_clk_div - 1) << MMC0_DIV_SHIFT);
		break;
	default:
		return -EINVAL;
	}

	return rockchip_mmc_get_clk(cru, clk_general_rate, periph);
}

static int rk322x_ddr_set_clk(struct rk322x_cru *cru, unsigned int set_rate)
{
	struct pll_div dpll_cfg;

	/*  clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
	switch (set_rate) {
	case 400*MHz:
		dpll_cfg = (struct pll_div)
		{.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1};
		break;
	case 600*MHz:
		dpll_cfg = (struct pll_div)
		{.refdiv = 1, .fbdiv = 75, .postdiv1 = 3, .postdiv2 = 1};
		break;
	case 800*MHz:
		dpll_cfg = (struct pll_div)
		{.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1};
		break;
	}

	/* pll enter slow-mode */
	rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
		     DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
	rkclk_set_pll(cru, CLK_DDR, &dpll_cfg);
	/* PLL enter normal-mode */
	rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
		     DPLL_MODE_NORM << DPLL_MODE_SHIFT);

	return set_rate;
}
static ulong rk322x_clk_get_rate(struct clk *clk)
{
	struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
	ulong rate, gclk_rate;

	gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
	switch (clk->id) {
	case 0 ... 63:
		rate = rkclk_pll_get_rate(priv->cru, clk->id);
		break;
	case HCLK_EMMC:
	case SCLK_EMMC:
	case HCLK_SDMMC:
	case SCLK_SDMMC:
		rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);
		break;
	default:
		return -ENOENT;
	}

	return rate;
}

static ulong rk322x_clk_set_rate(struct clk *clk, ulong rate)
{
	struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
	ulong new_rate, gclk_rate;

	gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
	switch (clk->id) {
	case HCLK_EMMC:
	case SCLK_EMMC:
	case HCLK_SDMMC:
	case SCLK_SDMMC:
		new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate,
						clk->id, rate);
		break;
	case CLK_DDR:
		new_rate = rk322x_ddr_set_clk(priv->cru, rate);
		break;
	case SCLK_MAC:
		new_rate = rk322x_mac_set_clk(priv->cru, rate);
		break;
	case PLL_GPLL:
		return 0;
	default:
		return -ENOENT;
	}

	return new_rate;
}

static int rk322x_gmac_set_parent(struct clk *clk, struct clk *parent)
{
	struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
	struct rk322x_cru *cru = priv->cru;

	/*
	 * If the requested parent is in the same clock-controller and the id
	 * is SCLK_MAC_SRC ("sclk_gmac_src"), switch to the internal clock.
	 */
	if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_SRC)) {
		debug("%s: switching RGMII to SCLK_MAC_SRC\n", __func__);
		rk_clrsetreg(&cru->cru_clksel_con[5], BIT(5), 0);
		return 0;
	}

	/*
	 * If the requested parent is in the same clock-controller and the id
	 * is SCLK_MAC_EXTCLK (sclk_mac_extclk), switch to the external clock.
	 */
	if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_EXTCLK)) {
		debug("%s: switching RGMII to SCLK_MAC_EXTCLK\n", __func__);
		rk_clrsetreg(&cru->cru_clksel_con[5], BIT(5), BIT(5));
		return 0;
	}

	return -EINVAL;
}

static int rk322x_gmac_extclk_set_parent(struct clk *clk, struct clk *parent)
{
	struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
	const char *clock_output_name;
	struct rk322x_cru *cru = priv->cru;
	int ret;

	ret = dev_read_string_index(parent->dev, "clock-output-names",
				    parent->id, &clock_output_name);
	if (ret < 0)
		return -ENODATA;

	if (!strcmp(clock_output_name, "ext_gmac")) {
		debug("%s: switching gmac extclk to ext_gmac\n", __func__);
		rk_clrsetreg(&cru->cru_clksel_con[29], BIT(10), 0);
		return 0;
	} else if (!strcmp(clock_output_name, "phy_50m_out")) {
		debug("%s: switching gmac extclk to phy_50m_out\n", __func__);
		rk_clrsetreg(&cru->cru_clksel_con[29], BIT(10), BIT(10));
		return 0;
	}

	return -EINVAL;
}

static int rk322x_clk_set_parent(struct clk *clk, struct clk *parent)
{
	switch (clk->id) {
	case SCLK_MAC:
		return rk322x_gmac_set_parent(clk, parent);
	case SCLK_MAC_EXTCLK:
		return rk322x_gmac_extclk_set_parent(clk, parent);
	}

	debug("%s: unsupported clk %ld\n", __func__, clk->id);
	return -ENOENT;
}

static struct clk_ops rk322x_clk_ops = {
	.get_rate	= rk322x_clk_get_rate,
	.set_rate	= rk322x_clk_set_rate,
	.set_parent	= rk322x_clk_set_parent,
};

static int rk322x_clk_of_to_plat(struct udevice *dev)
{
	struct rk322x_clk_priv *priv = dev_get_priv(dev);

	priv->cru = dev_read_addr_ptr(dev);

	return 0;
}

static int rk322x_clk_probe(struct udevice *dev)
{
	struct rk322x_clk_priv *priv = dev_get_priv(dev);

	rkclk_init(priv->cru);

	return 0;
}

static int rk322x_clk_bind(struct udevice *dev)
{
	int ret;
	struct udevice *sys_child;
	struct sysreset_reg *priv;

	/* The reset driver does not have a device node, so bind it here */
	ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
				 &sys_child);
	if (ret) {
		debug("Warning: No sysreset driver: ret=%d\n", ret);
	} else {
		priv = malloc(sizeof(struct sysreset_reg));
		priv->glb_srst_fst_value = offsetof(struct rk322x_cru,
						    cru_glb_srst_fst_value);
		priv->glb_srst_snd_value = offsetof(struct rk322x_cru,
						    cru_glb_srst_snd_value);
		dev_set_priv(sys_child, priv);
	}

#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
	ret = offsetof(struct rk322x_cru, cru_softrst_con[0]);
	ret = rockchip_reset_bind(dev, ret, 9);
	if (ret)
		debug("Warning: software reset driver bind failed\n");
#endif

	return 0;
}

static const struct udevice_id rk322x_clk_ids[] = {
	{ .compatible = "rockchip,rk3228-cru" },
	{ }
};

U_BOOT_DRIVER(rockchip_rk322x_cru) = {
	.name		= "clk_rk322x",
	.id		= UCLASS_CLK,
	.of_match	= rk322x_clk_ids,
	.priv_auto	= sizeof(struct rk322x_clk_priv),
	.of_to_plat = rk322x_clk_of_to_plat,
	.ops		= &rk322x_clk_ops,
	.bind		= rk322x_clk_bind,
	.probe		= rk322x_clk_probe,
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0
045029cb KY	2	/*
045029cb KY	3	* (C) Copyright 2017 Rockchip Electronics Co., Ltd
045029cb KY	4	*/
045029cb KY	5
045029cb KY	6	#include <clk-uclass.h>
	7	#include <dm.h>
	8	#include <errno.h>
f7ae49fc	9	#include <log.h>
336d4615	10	#include <malloc.h>
045029cb	11	#include <syscon.h>
15f09a1a KY	12	#include <asm/arch-rockchip/clock.h>
	13	#include <asm/arch-rockchip/cru_rk322x.h>
	14	#include <asm/arch-rockchip/hardware.h>
0fd3d911	15	#include <dm/device-internal.h>
045029cb KY	16	#include <dm/lists.h>
045029cb KY	17	#include <dt-bindings/clock/rk3228-cru.h>
cd93d625	18	#include <linux/bitops.h>
c05ed00a	19	#include <linux/delay.h>
045029cb	20	#include <linux/log2.h>
1af3c7f4	21	#include <linux/stringify.h>
045029cb	22
045029cb KY	23	enum {
	24	VCO_MAX_HZ = 3200U * 1000000,
	25	VCO_MIN_HZ = 800 * 1000000,
	26	OUTPUT_MAX_HZ = 3200U * 1000000,
	27	OUTPUT_MIN_HZ = 24 * 1000000,
	28	};
	29
045029cb KY	30	#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
	31
	32	#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
	33	.refdiv = _refdiv,\
	34	.fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ), \
	35	.postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
	36	_Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) * \
	37	OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz, \
	38	#hz "Hz cannot be hit with PLL "\
	39	"divisors on line " __stringify(__LINE__));
	40
	41	/* use integer mode*/
	42	static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
	43	static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
	44
	45	static int rkclk_set_pll(struct rk322x_cru *cru, enum rk_clk_id clk_id,
	46	const struct pll_div *div)
	47	{
	48	int pll_id = rk_pll_id(clk_id);
	49	struct rk322x_pll *pll = &cru->pll[pll_id];
	50
	51	/* All PLLs have same VCO and output frequency range restrictions. */
	52	uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000;
	53	uint output_hz = vco_hz / div->postdiv1 / div->postdiv2;
	54
	55	debug("PLL at %p: fb=%d, ref=%d, pst1=%d, pst2=%d, vco=%u Hz, output=%u Hz\n",
	56	pll, div->fbdiv, div->refdiv, div->postdiv1,
	57	div->postdiv2, vco_hz, output_hz);
	58	assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
	59	output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);
	60
	61	/* use integer mode */
	62	rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
	63	/* Power down */
	64	rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT);
	65
	66	rk_clrsetreg(&pll->con0,
	67	PLL_POSTDIV1_MASK \| PLL_FBDIV_MASK,
	68	(div->postdiv1 << PLL_POSTDIV1_SHIFT) \| div->fbdiv);
	69	rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK \| PLL_REFDIV_MASK,
	70	(div->postdiv2 << PLL_POSTDIV2_SHIFT \|
	71	div->refdiv << PLL_REFDIV_SHIFT));
	72
	73	/* Power Up */
	74	rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT);
	75
	76	/* waiting for pll lock */
	77	while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))
	78	udelay(1);
	79
	80	return 0;
	81	}
	82
	83	static void rkclk_init(struct rk322x_cru *cru)
	84	{
	85	u32 aclk_div;
	86	u32 hclk_div;
	87	u32 pclk_div;
	88
	89	/* pll enter slow-mode */
	90	rk_clrsetreg(&cru->cru_mode_con,
	91	GPLL_MODE_MASK \| APLL_MODE_MASK,
	92	GPLL_MODE_SLOW << GPLL_MODE_SHIFT \|
	93	APLL_MODE_SLOW << APLL_MODE_SHIFT);
94
95	/* init pll */
96	rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
97	rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
98
99	/*
100	* select apll as cpu/core clock pll source and
101	* set up dependent divisors for PERI and ACLK clocks.
102	* core hz : apll = 1:1
103	*/
104	aclk_div = APLL_HZ / CORE_ACLK_HZ - 1;
105	assert((aclk_div + 1) * CORE_ACLK_HZ == APLL_HZ && aclk_div < 0x7);
106
107	pclk_div = APLL_HZ / CORE_PERI_HZ - 1;
108	assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf);
109
110	rk_clrsetreg(&cru->cru_clksel_con[0],
111	CORE_CLK_PLL_SEL_MASK \| CORE_DIV_CON_MASK,
112	CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT \|
113	0 << CORE_DIV_CON_SHIFT);
114
115	rk_clrsetreg(&cru->cru_clksel_con[1],
116	CORE_ACLK_DIV_MASK \| CORE_PERI_DIV_MASK,
117	aclk_div << CORE_ACLK_DIV_SHIFT \|
118	pclk_div << CORE_PERI_DIV_SHIFT);
119
120	/*
f3f6591c	121	* select gpll as pd_bus bus clock source and
045029cb KY	122	* set up dependent divisors for PCLK/HCLK and ACLK clocks.
	123	*/
	124	aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1;
	125	assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
	126
f3f6591c	127	pclk_div = BUS_ACLK_HZ / BUS_PCLK_HZ - 1;
5793e8c2	128	assert((pclk_div + 1) * BUS_PCLK_HZ == BUS_ACLK_HZ && pclk_div <= 0x7);
045029cb	129
f3f6591c	130	hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1;
5793e8c2	131	assert((hclk_div + 1) * BUS_HCLK_HZ == BUS_ACLK_HZ && hclk_div <= 0x3);
045029cb KY	132
	133	rk_clrsetreg(&cru->cru_clksel_con[0],
	134	BUS_ACLK_PLL_SEL_MASK \| BUS_ACLK_DIV_MASK,
	135	BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT \|
	136	aclk_div << BUS_ACLK_DIV_SHIFT);
	137
	138	rk_clrsetreg(&cru->cru_clksel_con[1],
	139	BUS_PCLK_DIV_MASK \| BUS_HCLK_DIV_MASK,
	140	pclk_div << BUS_PCLK_DIV_SHIFT \|
	141	hclk_div << BUS_HCLK_DIV_SHIFT);
	142
	143	/*
	144	* select gpll as pd_peri bus clock source and
	145	* set up dependent divisors for PCLK/HCLK and ACLK clocks.
	146	*/
	147	aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
	148	assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
	149
	150	hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
	151	assert((1 << hclk_div) * PERI_HCLK_HZ ==
	152	PERI_ACLK_HZ && (hclk_div < 0x4));
	153
	154	pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
	155	assert((1 << pclk_div) * PERI_PCLK_HZ ==
	156	PERI_ACLK_HZ && pclk_div < 0x8);
	157
	158	rk_clrsetreg(&cru->cru_clksel_con[10],
	159	PERI_PLL_SEL_MASK \| PERI_PCLK_DIV_MASK \|
	160	PERI_HCLK_DIV_MASK \| PERI_ACLK_DIV_MASK,
	161	PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT \|
	162	pclk_div << PERI_PCLK_DIV_SHIFT \|
	163	hclk_div << PERI_HCLK_DIV_SHIFT \|
	164	aclk_div << PERI_ACLK_DIV_SHIFT);
	165
	166	/* PLL enter normal-mode */
	167	rk_clrsetreg(&cru->cru_mode_con,
	168	GPLL_MODE_MASK \| APLL_MODE_MASK,
	169	GPLL_MODE_NORM << GPLL_MODE_SHIFT \|
	170	APLL_MODE_NORM << APLL_MODE_SHIFT);
	171	}
	172
	173	/* Get pll rate by id */
	174	static uint32_t rkclk_pll_get_rate(struct rk322x_cru *cru,
	175	enum rk_clk_id clk_id)
	176	{
	177	uint32_t refdiv, fbdiv, postdiv1, postdiv2;
	178	uint32_t con;
	179	int pll_id = rk_pll_id(clk_id);
	180	struct rk322x_pll *pll = &cru->pll[pll_id];
	181	static u8 clk_shift[CLK_COUNT] = {
	182	0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff,
	183	GPLL_MODE_SHIFT, 0xff
	184	};
	185	static u32 clk_mask[CLK_COUNT] = {
	186	0xff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xff,
	187	GPLL_MODE_MASK, 0xff
	188	};
	189	uint shift;
	190	uint mask;
	191
	192	con = readl(&cru->cru_mode_con);
	193	shift = clk_shift[clk_id];
	194	mask = clk_mask[clk_id];
	195
196	switch ((con & mask) >> shift) {
197	case GPLL_MODE_SLOW:
198	return OSC_HZ;
199	case GPLL_MODE_NORM:
200
201	/* normal mode */
202	con = readl(&pll->con0);
203	postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT;
204	fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT;
205	con = readl(&pll->con1);
206	postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT;
207	refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT;
208	return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
209	default:
210	return 32768;
211	}
212	}
213
214	static ulong rockchip_mmc_get_clk(struct rk322x_cru *cru, uint clk_general_rate,
215	int periph)
216	{
217	uint src_rate;
218	uint div, mux;
219	u32 con;
220
221	switch (periph) {
222	case HCLK_EMMC:
223	case SCLK_EMMC:
e4d0d612	224	case SCLK_EMMC_SAMPLE:
045029cb KY	225	con = readl(&cru->cru_clksel_con[11]);
	226	mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
	227	con = readl(&cru->cru_clksel_con[12]);
	228	div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
	229	break;
	230	case HCLK_SDMMC:
	231	case SCLK_SDMMC:
	232	con = readl(&cru->cru_clksel_con[11]);
	233	mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
	234	div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
	235	break;
	236	default:
	237	return -EINVAL;
	238	}
	239
	240	src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate;
3a94d75d	241	return DIV_TO_RATE(src_rate, div) / 2;
045029cb KY	242	}
045029cb KY	243
5bb616c6 DW	244	static ulong rk322x_mac_set_clk(struct rk322x_cru *cru, uint freq)
	245	{
	246	ulong ret;
	247
	248	/*
	249	* The gmac clock can be derived either from an external clock
	250	* or can be generated from internally by a divider from SCLK_MAC.
	251	*/
	252	if (readl(&cru->cru_clksel_con[5]) & BIT(5)) {
	253	/* An external clock will always generate the right rate... */
	254	ret = freq;
	255	} else {
	256	u32 con = readl(&cru->cru_clksel_con[5]);
	257	ulong pll_rate;
	258	u8 div;
	259
	260	if ((con >> MAC_PLL_SEL_SHIFT) & MAC_PLL_SEL_MASK)
	261	pll_rate = GPLL_HZ;
	262	else
	263	/* CPLL is not set */
	264	return -EPERM;
	265
	266	div = DIV_ROUND_UP(pll_rate, freq) - 1;
	267	if (div <= 0x1f)
	268	rk_clrsetreg(&cru->cru_clksel_con[5], CLK_MAC_DIV_MASK,
	269	div << CLK_MAC_DIV_SHIFT);
	270	else
	271	debug("Unsupported div for gmac:%d\n", div);
	272
	273	return DIV_TO_RATE(pll_rate, div);
	274	}
	275
	276	return ret;
	277	}
	278
045029cb KY	279	static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate,
	280	int periph, uint freq)
	281	{
	282	int src_clk_div;
	283	int mux;
	284
	285	debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate);
	286
3a94d75d KY	287	/* mmc clock defaulg div 2 internal, need provide double in cru */
3a94d75d KY	288	src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq);
045029cb	289
217273cd	290	if (src_clk_div > 128) {
3a94d75d	291	src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
217273cd	292	assert(src_clk_div - 1 < 128);
045029cb KY	293	mux = EMMC_SEL_24M;
	294	} else {
	295	mux = EMMC_SEL_GPLL;
	296	}
	297
	298	switch (periph) {
	299	case HCLK_EMMC:
	300	case SCLK_EMMC:
e4d0d612	301	case SCLK_EMMC_SAMPLE:
045029cb KY	302	rk_clrsetreg(&cru->cru_clksel_con[11],
	303	EMMC_PLL_MASK,
	304	mux << EMMC_PLL_SHIFT);
	305	rk_clrsetreg(&cru->cru_clksel_con[12],
	306	EMMC_DIV_MASK,
	307	(src_clk_div - 1) << EMMC_DIV_SHIFT);
	308	break;
	309	case HCLK_SDMMC:
	310	case SCLK_SDMMC:
	311	rk_clrsetreg(&cru->cru_clksel_con[11],
	312	MMC0_PLL_MASK \| MMC0_DIV_MASK,
	313	mux << MMC0_PLL_SHIFT \|
	314	(src_clk_div - 1) << MMC0_DIV_SHIFT);
	315	break;
	316	default:
	317	return -EINVAL;
	318	}
	319
	320	return rockchip_mmc_get_clk(cru, clk_general_rate, periph);
	321	}
	322
	323	static int rk322x_ddr_set_clk(struct rk322x_cru *cru, unsigned int set_rate)
	324	{
	325	struct pll_div dpll_cfg;
	326
	327	/* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
	328	switch (set_rate) {
	329	case 400*MHz:
	330	dpll_cfg = (struct pll_div)
	331	{.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1};
	332	break;
	333	case 600*MHz:
	334	dpll_cfg = (struct pll_div)
	335	{.refdiv = 1, .fbdiv = 75, .postdiv1 = 3, .postdiv2 = 1};
	336	break;
	337	case 800*MHz:
	338	dpll_cfg = (struct pll_div)
	339	{.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1};
	340	break;
	341	}
	342
	343	/* pll enter slow-mode */
	344	rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
	345	DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
	346	rkclk_set_pll(cru, CLK_DDR, &dpll_cfg);
	347	/* PLL enter normal-mode */
	348	rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
	349	DPLL_MODE_NORM << DPLL_MODE_SHIFT);
	350
	351	return set_rate;
	352	}
	353	static ulong rk322x_clk_get_rate(struct clk *clk)
	354	{
	355	struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
	356	ulong rate, gclk_rate;
	357
	358	gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
	359	switch (clk->id) {
	360	case 0 ... 63:
	361	rate = rkclk_pll_get_rate(priv->cru, clk->id);
	362	break;
	363	case HCLK_EMMC:
	364	case SCLK_EMMC:
	365	case HCLK_SDMMC:
366	case SCLK_SDMMC:
367	rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);
368	break;
369	default:
370	return -ENOENT;
371	}
372
373	return rate;
374	}
375
376	static ulong rk322x_clk_set_rate(struct clk *clk, ulong rate)
377	{
378	struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
379	ulong new_rate, gclk_rate;
380
381	gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
382	switch (clk->id) {
383	case HCLK_EMMC:
384	case SCLK_EMMC:
385	case HCLK_SDMMC:
386	case SCLK_SDMMC:
387	new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate,
388	clk->id, rate);
389	break;
390	case CLK_DDR:
391	new_rate = rk322x_ddr_set_clk(priv->cru, rate);
392	break;
5bb616c6 DW	393	case SCLK_MAC:
	394	new_rate = rk322x_mac_set_clk(priv->cru, rate);
	395	break;
	396	case PLL_GPLL:
	397	return 0;
045029cb KY	398	default:
	399	return -ENOENT;
	400	}
	401
	402	return new_rate;
	403	}
	404
5bb616c6 DW	405	static int rk322x_gmac_set_parent(struct clk clk, struct clk parent)
	406	{
	407	struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
	408	struct rk322x_cru *cru = priv->cru;
	409
	410	/*
	411	* If the requested parent is in the same clock-controller and the id
	412	* is SCLK_MAC_SRC ("sclk_gmac_src"), switch to the internal clock.
	413	*/
	414	if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_SRC)) {
	415	debug("%s: switching RGMII to SCLK_MAC_SRC\n", __func__);
	416	rk_clrsetreg(&cru->cru_clksel_con[5], BIT(5), 0);
	417	return 0;
	418	}
	419
	420	/*
	421	* If the requested parent is in the same clock-controller and the id
	422	* is SCLK_MAC_EXTCLK (sclk_mac_extclk), switch to the external clock.
	423	*/
	424	if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_EXTCLK)) {
	425	debug("%s: switching RGMII to SCLK_MAC_EXTCLK\n", __func__);
	426	rk_clrsetreg(&cru->cru_clksel_con[5], BIT(5), BIT(5));
	427	return 0;
	428	}
	429
	430	return -EINVAL;
	431	}
	432
	433	static int rk322x_gmac_extclk_set_parent(struct clk clk, struct clk parent)
	434	{
	435	struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
	436	const char *clock_output_name;
	437	struct rk322x_cru *cru = priv->cru;
	438	int ret;
	439
	440	ret = dev_read_string_index(parent->dev, "clock-output-names",
	441	parent->id, &clock_output_name);
	442	if (ret < 0)
	443	return -ENODATA;
	444
	445	if (!strcmp(clock_output_name, "ext_gmac")) {
	446	debug("%s: switching gmac extclk to ext_gmac\n", __func__);
	447	rk_clrsetreg(&cru->cru_clksel_con[29], BIT(10), 0);
	448	return 0;
	449	} else if (!strcmp(clock_output_name, "phy_50m_out")) {
	450	debug("%s: switching gmac extclk to phy_50m_out\n", __func__);
	451	rk_clrsetreg(&cru->cru_clksel_con[29], BIT(10), BIT(10));
	452	return 0;
	453	}
	454
	455	return -EINVAL;
	456	}
	457
	458	static int rk322x_clk_set_parent(struct clk clk, struct clk parent)
	459	{
	460	switch (clk->id) {
	461	case SCLK_MAC:
	462	return rk322x_gmac_set_parent(clk, parent);
	463	case SCLK_MAC_EXTCLK:
	464	return rk322x_gmac_extclk_set_parent(clk, parent);
	465	}
	466
	467	debug("%s: unsupported clk %ld\n", __func__, clk->id);
	468	return -ENOENT;
469	}
470
045029cb KY	471	static struct clk_ops rk322x_clk_ops = {
	472	.get_rate = rk322x_clk_get_rate,
	473	.set_rate = rk322x_clk_set_rate,
5bb616c6	474	.set_parent = rk322x_clk_set_parent,
045029cb KY	475	};
045029cb KY	476
d1998a9f	477	static int rk322x_clk_of_to_plat(struct udevice *dev)
045029cb KY	478	{
	479	struct rk322x_clk_priv *priv = dev_get_priv(dev);
	480
99b8553c	481	priv->cru = dev_read_addr_ptr(dev);
045029cb KY	482
	483	return 0;
	484	}
	485
	486	static int rk322x_clk_probe(struct udevice *dev)
	487	{
	488	struct rk322x_clk_priv *priv = dev_get_priv(dev);
	489
	490	rkclk_init(priv->cru);
	491
	492	return 0;
	493	}
	494
	495	static int rk322x_clk_bind(struct udevice *dev)
	496	{
	497	int ret;
f24e36da KY	498	struct udevice *sys_child;
f24e36da KY	499	struct sysreset_reg *priv;
045029cb KY	500
045029cb KY	501	/* The reset driver does not have a device node, so bind it here */
f24e36da KY	502	ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
	503	&sys_child);
	504	if (ret) {
	505	debug("Warning: No sysreset driver: ret=%d\n", ret);
	506	} else {
	507	priv = malloc(sizeof(struct sysreset_reg));
	508	priv->glb_srst_fst_value = offsetof(struct rk322x_cru,
	509	cru_glb_srst_fst_value);
	510	priv->glb_srst_snd_value = offsetof(struct rk322x_cru,
	511	cru_glb_srst_snd_value);
0fd3d911	512	dev_set_priv(sys_child, priv);
f24e36da	513	}
045029cb	514
a5ada25e	515	#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
538f67c3 EZ	516	ret = offsetof(struct rk322x_cru, cru_softrst_con[0]);
	517	ret = rockchip_reset_bind(dev, ret, 9);
	518	if (ret)
30850b69	519	debug("Warning: software reset driver bind failed\n");
538f67c3 EZ	520	#endif
538f67c3 EZ	521
045029cb KY	522	return 0;
	523	}
	524
	525	static const struct udevice_id rk322x_clk_ids[] = {
	526	{ .compatible = "rockchip,rk3228-cru" },
	527	{ }
	528	};
	529
	530	U_BOOT_DRIVER(rockchip_rk322x_cru) = {
	531	.name = "clk_rk322x",
	532	.id = UCLASS_CLK,
	533	.of_match = rk322x_clk_ids,
41575d8e	534	.priv_auto = sizeof(struct rk322x_clk_priv),
d1998a9f	535	.of_to_plat = rk322x_clk_of_to_plat,
045029cb KY	536	.ops = &rk322x_clk_ops,
	537	.bind = rk322x_clk_bind,
	538	.probe = rk322x_clk_probe,
	539	};